FLIR Lepton 1.5, Engineering Data Sheet

Page: 77 / 84

FLIR LEPTON® Engineering Datasheet
The information contained herein does not contain technology as defined by the EAR, 15 CFR 772, is publicly available,
and therefore, not subject to EAR. NSR (6/14/2018).
Information on this page is subject to change without notice.
Lepton Engineering Datasheet, Document Number: 500-0659-00-09 Rev: 203
77
9.3 AC Electrical Characteristics
Table 17 - AC Electrical Characteristics
Parameter Min Typ Max Units
MASTER_CLK, F
clk
24.975 MHz
See note
1
25 MHz 25.025 MHz
See note
1, 2
Master clock
rate
MASTER_CLK, F
clk duty
45% 50% 55%
Master clock
duty cycle
MASTER_CLK, t
r
-- -- 3.4ns Clock rise time
(10% to 90%)
MASTER_CLK, t
f
-- -- 3.4ns Clock fall time
(90% to 10%)
SPI_CLK, F
clk
See note 3 20 MHz VoSPI clock rate
SPI_CLK, F
clk duty
45% 50% 55% SPI-clock duty
cycle
SPI_CLK, t
r
-- -- TBD SPI clock rise time
(10% to 90%)
SPI_CLK, t
f
-- -- TBD SPI clock fall time
(90% to 10%)
SCL, F
clk
1 MHz I2C clock rate
SCL, F
clk duty
45% 50% 55% I2C-clock duty
cycle
SCL_CLK, t
r
-- -- TBD I2C clock rise time
(10% to 90%)
SCL_CLK, t
f
-- -- TBD I2C clock fall time
(90% to 10%)
Note(s)
1. Master clock frequencies significantly more or less than 25MHz may cause image degradation.
2. Master clock frequencies significantly above 25.5MHz will cause the camera to stop displaying live sensor data and display an
overclock test pattern.
3. As described in
VoSPI Protocol
, page
46
, the minimum VoSPI clock frequency is dependent upon the requirement to read
out all video packets for a given frame within the frame period. The size and number of video packets vary with user
settings.