FlexRadio Systems FLEX-1500, Service Manual

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Revision 1.0
7
Copyright FlexRadio Systems, 2010-2011
Control Busses
There are several control busses
that interconnect the radio. A USB “Full Speed” bus
interconnects the host computer running PowerSDR with the on-board CPU, the
TAS1020B. Control from the TAS1020B CPU to the rest of the radio and external
control is via an I2C bus system, and two SPI busses.
Firmware for the CPU is resident in a local (I2C) EEPROM on the transceiver board.
Upon power up, the CPU will look for the presence of a properly programmed EEPROM,
load this code, begin execution, and register with the host computer as a FLEX-1500
device. In the absence of the EEPROM, or lack of correctly identified firmware, the CPU
will execute from internal ROM, and identify itself to the host computer as a “TI DFU
device.”
The FLEX-1500 CPU will communicate via USB for both control and streaming
baseband data with the host CPU running the PowerSDR software. The CPU in the
FLEX-1500 has control of all switching, signal routing, frequency generation via the
DDS, FlexWire port, audio amplifier, as well as audio and baseband routing, CODEC
clock generation, data conversion, gain and level controls for the radio. All of the above
must be translated from local hardware and register controls to the Command and Data
structures chosen for USB transport and interface in the host to the PowerSDR software.
I2C Bus
The I2C bus exists as three instances.
(1.) The computer bus (I2C-C), which contains the (master) CPU, the EEPROM
containing program memory and calibration parameters, and the Bus Mux.
(2.) The Internal I2C bus, (I2C-I) containing the two bus expanders and the
CODEC chip.
(3.) The External I2C bus (I2C-E) which is routed to the FlexWire DB-9
connector, and is only used in conjunction with an external FlexWire device.
The I2C Bus Mux selects whether the Computer I2C bus will be connected to the Internal
or External I2C bus extension at any given time, as well as passing any interrupt requests
upwards to the CPU. Since the EEPROM and the Bus Mux are on the computer bus, their
addresses will appear in all I2C bus spaces.
I2C Bus Structure
The I2C bus address values are provided according to the TI convention, where the
address is an eight bit word, expressed as two hexadecimal characters. The least