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BIOS Setup
CPU to PCI Write Buffer
When enabled, allows data and address access to the internal buffer of
the system controller; so the processor can be released from the waiting
state. The options are: Enabled, Disabled.
PCI Dynamic Bursting
When enabled, the PCI controller allows Bursting PCI transfer if the con-
secutive PCI cycles come with the address falling in same 1KB space. This
improves the PCI bus throughput.
The options are: Enabled, Disabled.
PCI Master 0 WS Write
When enabled, allows a zero-wait-state-cycle delay when the PCI master
drive writes data to DRAM. The options are: Enabled, Disabled.
PCI Delay Transaction
Enable this feature to abort the current CPI master cycle and to accept the
new PCI master request, it reaccepts the original PCI master and returns
the PCI data phase to the original PCI master.
The options are: Disabled, Enabled.
PCI#2 Access #1 Retry
When enabled, the AGP (PCI#2) access to PCI (PCI#1) will be retried until
the maximum count. The options are: Disabled, Enabled.
AGP Master 1 WS Write
When enabled, the AGP bus master write access to DRAMs will add one
wait-state cycle. The options are: Disabled, Enabled.
AGP Master 1 WS Read
When enabled, the AGP bus master read access to the DRAMs will add
one wait-state cycle. The options are: Disabled, Enabled.
Memory Parity/ECC Check
This field enables BIOOS to perform automatic memory checking upon
detection of ECC or parity DRAM. The options are: Disabled, Enabled.
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