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FIBOCOM SU806 Series Hardware Guide
Page 35 of 86
V D D _1V 8
U A R T _T X D
U A R T _C T S
M C U _R T S
0.1uF
U A R T _R X D
V C C A
O E
V C C B
G N D
A 1
A 2
A 3
A 4
B 4
B 3
B 2
B 1
Level S hifter
0.1uF
V D D _M C U
M C U _T X D
M C U _R X D
M C U _C T S
U A R T _R T S
Figure 3-10 Level shift reference design
The other level
translator
circuit is shown as Figure 3-11, The rest input and output circuit design of dotted
line please refer to solid line part, but pay attention to signal connection direction.
Figure 3-11 Level shift reference design 2
3.5
SPI
SU806D-EAU series module provides one master only SPI interface, the pin definition is shown in the
following table:
Table 3-9 SPI pin definition
Pin Name
Pin
Number
I/O
Description
Note
SPI_CLK
116
DO
SPI clock
-