Pin
Number
Pin Name
I/O
Reset
Status
Pin Description
Type
52
CLKREQ#
DIO
T
PCIe clock request signal, active
low, open drain output, an
external pull-up resistor needs
to be reserved
CMOS
3.3V/1.8V
53
REFCLKN
DIO
*
PCIe reference clock differential
negative signal
*
54
PEWAKE#
DO
T
PCIe wake-up signal, active low,
open drain output, an external
pull-up resistor is required
CMOS
3.3V/1.8V
55
REFCLKP
DIO
*
PCIe reference clock differential
positive signal
*
56
RFFE_SCLK
DO
PD
RFFE-MIPI serial clock signal,
I2C_SCL (Reserved)
CMOS
1.8V
57
GND
- -
- -
Ground
Power
supply
58
RFFE_SDATA DIO
PD
RFFE-MIPI serial data signal,
I2C_SDA (Reserved)
CMOS
1.8V
59
GRFC7*
DO
PD
Tuning antenna control bit,
reserved
CMOS
1.8V
60
COEX3/GPIO
86
DI
*
LTE/WLAN common control
signal
CMOS
1.8V
61
GRFC6*
DO
PD
Tuned antenna control bit 1,
reserved
CMOS
1.8V
62
COEX_UART_
RXD*
DI
- -
LTE and WLAN share a serial
port receiving signal line,
reserved
CMOS
1.8V
3. Pin Definition
Copyright © Fibocom Wireless Inc.
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