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FG360-NA Hardware Guide
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Pin Name
Pin No.
Type
Power Domain Reset Value Pin Description
and RF co-exist control
signals
GPIO78/
PCIE_D_CLKREQN
162
DO
VDD_EXT_1V8 PD
MT6890 GPIO, used for
2+2+4 and 4+4+4 WIFI/BT
and RF co-exist control
signals
JTAG
TDI
183
DI
VDD_EXT_1V8 PD
JTAG TDI
，
Reserved
TCK
186
DI
VDD_EXT_1V8 PD
JTAG TCK
，
Reserved
TDO
189
DO
VDD_EXT_1V8 PD
JTAG TDO
，
Reserved
TRST_N
295
DI
VDD_EXT_1V8 PD
JTAG TRST
，
Reserved
TMS
296
DI
VDD_EXT_1V8 PD
JTAG TMS
，
Reserved
SYSRSTB
297
DI
VDD_EXT_1V8 PD
System reset
，
Reserved
I2C
I2C_SDA0
115
DIO
VDD_EXT_1V8 PU
I2C data
I2C_SCL0
112
DO
VDD_EXT_1V8 PU
I2C clock
I2S
I2S0_DO
103
DO
VDD_EXT_1V8 PD
I2S data output signal
I2S0_MCK
94
DO
VDD_EXT_1V8 PD
I2S clock output signal
I2S0_DI
104
DI
VDD_EXT_1V8 PD
I2S data input signal
I2S0_BCK
101
DO
VDD_EXT_1V8 PD
I2S data bit clock signal
I2S0_LRCK
105
DO
VDD_EXT_1V8 PD
I2S frame clock signal
ADC
ADC0
249
AI
VDD_EXT_1V8 -
A/D conversion channel 0
ADC1
252
AI
VDD_EXT_1V8 -
A/D conversion channel 1
Debug UART
DBG_UART_TX
129
DO
VDD_EXT_1V8 PU
Debug UART data
transmission
DBG_UART_RX
126
DI
VDD_EXT_1V8 PU
Debug UART data reception
UART
AP_UCTS1
79
DI
VDD_EXT_1V8 PD
UART receive ready signal
AP_URTS1
64
DO
VDD_EXT_1V8 PD
UART transmit request signal
AP_UTXD1
77
DO
VDD_EXT_1V8 PD
UART transmit signal
AP_URXD1
73
DI
VDD_EXT_1V8 PD
UART receive signal
SPI
SPI0_MISO
5
DI
VDD_EXT_1V8 PD
SPI interface input signal
SPI0_MOSI
8
DO
VDD_EXT_1V8 PD
SPI interface output signal
SPI0_CSB
6
DO
VDD_EXT_1V8 PD
SPI interface chip select
signal
SPI0_CLK
9
DO
VDD_EXT_1V8 PD
SPI interface clock signal
AUDIO CODEC
CDC_RESET_N
98
DO
VDD_EXT_1V8 PD
External CODEC reset signal
CDC_INT1_N
100
DI
VDD_EXT_1V8 PD
External CODEC interrupt
signal
