Hardware Description
2.3 Rear Panel, Clock Fan-out
At the rear panel a clock source (TTL 3.3V, 10 to 120 MHz) can be distributed from a BNC connector labeled
CLOCK IN to eight synchronous output signals at BNC connectors CLK1 - CLK8. Termination of the clock
input can be set to 50 Ohm or 3 kOhm with JP2. AC or DC coupling is selectable with jumper JP3, see Fig.
2.4
A clock signal from an external source is automatically recognized. By two LEDs it is indicated if the external
or the internal clock is used.
The internal quartz oscillator can be replaced by an oven-stabilized oscillator (option MCCDOVX) or a highly
stable Cs atomic clock (option MCCDATOM).
Also there is an optional binary divider (32 bit), which can reduce the external clock in binary steps. Divider
factor is set by internal jumpers see Fig. 2.5.
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ComTec GmbH
Fig. 2.3: The MCCD Rear Panel
Fig. 2.4 Jumpers JP2 for 50 Ohm Termination and JP3 for DC/AC coupling
