JP14-R-LP & JP14-Q-LP F
ALCOM
GPS R
ECEIVERS
V
ERSION
1.0.0
5 TECHNICAL DESCRIPTION
5.1 Receiver Architecture
The JP14-R-LP/Q-LP OEM GPS receivers from FALCOM are new OEM GPS receiver
products that feature the SiRFstarIII single chipset. The core of these units is
comprised of the GSC3LP that includes the Digital and RF in a single chip. All units
are built around re-configurable high-output segmented matched filter in
conjunction with a FFT processor, which can search all 1023 chips of the GPS code
simultaneously over a wide frequency range for fast initial acquisition with large
uncertainties. The flexibility of the core allows the core processing engine and
memory to be reconfigured to track more than 20 satellites using the same
hardware. This flexibility make the JP14-R-LP/Q-LP highly efficient engines for wide
variety of location applications. The core of JP14-R-LP/Q-LP contains a built in
sequencer, which handles all the high-rate interrupts for GPS and SBAS (WAAS,
EGNOS) tracking and acquisitions. After initialization, the receiver handles all the time
critical and low latency acquisition, tracking and reacquisition tasks of GPS and SBAS
autonomously. The on-chip SRAM size is 1-Mbit (32Kx32) memory that can be used
for either instructions or data. The SRAM is designed for a combination of low power
and high speed, and can support single cycle reads for all bus speeds. In many
applications, the 4 Mbit FLASH completely eliminates the need for external data
memory.
Figure 3:
Architecture of the JP14-R-LP/Q-LP GPS receivers.
Figure 3 above shows the block diagram of the JP14-R-LP/Q-LP architecture.
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