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©2002 Fairchild Semiconductor Corporation

Application Note 7511 Rev. A1

Insulated-Gate Transistors Simplify AC-Motor

Speed Control

An IGT’s few input requirements and low On-state resistance
simplify drive circuitry and increase power efficiency in motor-
control applications. The voltage-controlled, MOSFET-like
input and transfer characteristics of the insulated-gate transis-
tor (IGT) (see EDN, September 29, 1983, pg 153 for IGT
details) simplify power-control circuitry when compared with
bipolar devices. Moreover, the IGT has an input capacitance
mirroring that of a MOSFET that has only one-third the power-
handling capability. These attributes allow you to design sim-
ple, low-power gate-drive circuits using isolated or level-shift-
ing techniques. What’s more, the drive circuit can control the
IGT’s switching times to suppress EMI, reduce oscillation and
noise, and eliminate the need for snubber networks.

Use Optoisolation To Avoid Ground Loops

The gate-drive techniques described in the following sections
illustrate the economy and flexibility the IGT brings to power
control: economy, because you can drive the device’s gate
directly from a preceding collector, via a resistor network, for
example; flexibility, because you can choose the drive circuit’s
impedance to yield a desired turn-off time, or you can use a
switchable impedance that causes the IGT to act as a charge-
controlled device requiring less than 10 nanocoulombs of
drive charge for full turn-on.

Take Some Driving Lessons

Note the IGT’s straightforward drive compatibility with CMOS,
NMOS and open-collector TTL/HTL logic circuits in the
common-emitter configuration Figure 1A. R

3

 controls the turn-

off time, and the sum of R

3

 and the parallel combination of R

1

and R

2

 sets the turn-on time. Drive-circuit requirements,

however, are more complex in the common-collector
configuration Figure 1B.

In this floating-gate-supply floating-control drive scheme, R

1

controls the gate supply’s power loss, R

2

 governs the turn-off

time, and the sum of R

1

 and R

2

 sets the turn-on time. Figure

1C shows another common-collector configuration employing
a bootstrapped gate supply. In this configuration, R

3

 defines

the turn-off time, while the sum of R

2

 and R

3

 controls the turn-

on time. Note that the gate’s very low leakage allows the use
of low-consumption bootstrap supplies using very low-value
capacitors. Figure 1 shows two of an IGT’s strong points. In
the common-emitter Figure 1A, TTL or MOS-logic circuits can
drive the device directly. In the common-collector mode, you’ll
need level shifting, using either a second power supply Figure
1B or a bootstrapping scheme Figure 1C.

In the common-collector circuits, power-switch current flowing
through the logic circuit’s ground can create problems.
Optoisolation can solve this problem (Figure 2A.) Because of
the high common-mode dV/dt possible in this configuration,
you should use an optoisolator with very low isolation capaci-
tance; the H11AV specs 0.5pF maximum.

FIGURE 1A

.

SIMPLE DRIVING AND TRANSITION-TIME

CONTROL 

FIGURE 1B. A

 

SECOND POWER SUPPLY

FIGURE 1C. BOOTSTRAPPING SCHEME

LOAD

V

CC

R

1

R

3

R

2

ON

OFF

15

V

CC

R

2

R

1

R

2

+

--------------------

25V

R

3

 CONTROLS t

OFF

LOAD

V

CC

CONTROL

INPUT

ON

OFF

15V

R

1

R

2

R

1

 CONTROLS GATE

SUPPLY POWER LOSS

R

2

 CONTROLS t

OFF

R

1

 + R

2

 CONTROLS t

ON

LOAD

ON

OFF

15

V

CC

R

2

R

1

R

2

+

--------------------

25V

R

3

 CONTROLS t

OFF

R

2

 + R

3

 CONTROLS t

ON

τ

5C

I

CEO

I

GES

2IR

+

+

-------------------------------------------------

«

R

1

R

3

R

2

Application Note

                              September 1993

 AN-7511

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Summary of Contents for AN-7511

Page 1: ... sum of R3 and the parallel combination of R1 and R2 sets the turn on time Drive circuit requirements however are more complex in the common collector configuration Figure 1B In this floating gate supply floating control drive scheme R1 controls the gate supply s power loss R2 governs the turn off time and the sum of R1 and R2 sets the turn on time Figure 1C shows another common collector configur...

Page 2: ...ler drive along with its transient response In some applications the photovoltaic element can charge a storage capacitor that s subsequently switched with a phototransistor isolator This isolator technique similar to that used in bootstrap circuits provides rapid turn on and turn off while maintaining small size good isolation and low cost In common collector applications involving high voltage re...

Page 3: ...NTROL INPUT ON OFF GFOE1A1 EMITTER DISCONNECTED DETECTOR CONNECTED 10M 30FT QSF2000C W CONNECTORS GFOD1A1 1N914 R1 2N5354 C Q1 R2 R3 IGT FIGURE 4 ELIMINATE EMI IN HIGH FLUX OR NOISE ENVI RONMENTS BY USING FIBER OPTIC COMPO NENTS THESE PARTS ALSO ALLEVIATE PROBLEMS ARISING FROM CAPACITIVE COU PLING IN ISOLATION ELEMENTS Piezos Pare Prices OUTPUT VOLTAGE ACOUSTIC WAVE OSCILLATOR IGT 4 7k 1N914 1N914...

Page 4: ...GH ISOLATION AT LOW COST PULSE TRANSFORMERS ARE IDEAL FOR DRIVING THE IGT AT SUFFICIENTLY HIGH FREQUENCIES C1 CAN BE THE IGT S GATE EMITTERCAPACITANCE ALONE FIGURE 6B A HIGH FREQUENCY OSCILLATOR IN THE TRANS FORMER S PRIMARY YIELDS UNLIMITED ON TIME CAPABILITY In the pulse on pulse off method Figure 6A C1 stores a positive pulse holding the IGT on At moderate frequencies several hundred Hertz and ...

Page 5: ...ransformer reasonably small The volt age doubler circuitry improves the turn on time and also pro vides long on time capability Although this design uses only a 5V supply on the primary side of a standard trigger trans former it provides 15V gate to emitter voltage FIGURE 7 THIS DRIVING METHOD FOR LOW FREQUENCY SWITCHING PROVIDES 15V TO THE IGT S GATE OSCILLATOR 1 2 1N914 0 001µF 4 7k 0 001 µF IGT...

Page 6: ...r to shut off The inverter s power out put circuit is shown in Figure 9A the corresponding timing diagrams show resistive load current waveforms that indi cate the 3 phase power Figure 9B and waveforms of the out put line voltage and current Figure 9C In Figure 9 s circuit it appears that IGTs Q1 through Q6 will conduct for 180o However in a practical situation it s neces sary to provide some time...

Page 7: ... could also do the job but the 500V choice gives an additional derating safety margin You must set the current limit at 9A to limit the in rush current during start up Note that thanks to the IGT s adequate RBSOA you don t need turn off snubbers FIGURE 11A PROVIDING PROPERLY TIMED DRIVE TO THE IGTS THE CIRCUIT USES PIEZO COUPLING TO THE UPPER POWER DEVICE THE 3 TRANSISTOR DELAY CIRCUIT PROVIDES TH...

Page 8: ...65o Conduction Prevents Shoot Through Consider however using Figure 11A s novel low cost cir cuit It uses a piezo coupler to drive the isolated IGT As noted the coupler needs a high frequency square wave to induce mechanical oscillations in its primary side The 555 oscillator provides the necessary 108 kHz waveform its out put is gated according to the required timing logic and then applied to the...

Page 9: ...f the power switch and the circuit s bias conditions The IGT is very rugged during turn on and conduction but it requires time to dissipate minority carriers when turning off high currents and voltages An analysis of the possible malfunction condition FIGURE 14 THE LOWEST COST SENSOR IMAGINABLE A PIECE OF COPPER WIRE SERVES AS THE CURRENT MONITOR IN THIS SYS TEM THE CHOPPED AND AMPLIFIED VOLTAGE D...

Page 10: ...5V 5µF 25V 220k 2 2k 0 001 µF H11F3 H11F3 TO CONTROL CIRCUIT 39 470 pF 390 20A 2k 2mΩ 1 24 AWG COPPER POWER SUPPLY CURRENT SENSE AND CHOPPER AC AMPLIFIER LATCHING FAST COMPARATOR 10ms RESET IGT POWER SWITCHES A139M 50µH 10k 180k 47k 39k 0 001 µF 1k 2N5306 C203B 0 02 µF 22k H11AV2 TO PZO SHUTDOWN H11AV2 TO HI V SHUTDOWN 22 0 2µF 2 1 TO DRIVE DT230F TO MOTOR TIMER 555 1 3 CHOPPER DRIVE TO PIEZO DRIV...

Page 11: ...ich the IGT latches on while in forward conduction is typically three to four times the device s maximum rated collector current When the collector current drops below the value that provokes Q2 turn on normal operation resumes if chip temperature is still within ratings If the gate to emitter resistance is too low the Q2 Q3 parasitic SCR can cause the IGT to latch up during turn off During this p...

Page 12: ...EAT ER THAN THAT OF THE IGT S GATE DRIVE SO THE IGT UNDER TEST IS SWITCHED THROUGH Q1 WHEN REVERSE BIAS LATCH UP OCCURS PULSE GENERATOR PULSE GENERATOR TRIGGER 1000pF A114A A114A 1k 100 100 50 10 D38H1 D44D6 Q1 D66EV7 Q2 DUT D94FQ4 DS0026x2 5V 1N914 10V PE 63385 A114A 15V D66EV7 Q1 RGE 1 10k VCE A139M 10 VCC VCLAMP 400V MAX 0 02µF 10µF A139P L 100µH 2k Q2 Application Note 7511 ...

Page 13: ...support device or system or to affect its safety or effectiveness PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data ...

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