
Model
MASS 2
Version
V_1.0
Prepared by
H/W
Date
22/01/2008
Subject Technical
Manual Page
2/59
-. ARM7EJ-S 32bit RISC processor
-. High Performance Multi-layer AMBA bus
-. Java hardware acceleration for fast Java-based games and applets.
-.Operating frequency : 25/52/104Mhz
-. Dedicated DMA Bus
-. 14 DMA channels
-. 48K Bytes on-chip SRAM
-. 72K Bytes MCU dedicated Tightly Coupled memory
-. 16K Bytes CODE cache
-. On-chip boot ROM for factory flash programming
-. Watchdog timer for system crash recovery
-. 2sets of General purpose timer
-. Circuit Switch Data coprocessor
-. Division coprocessor.
z
External Memory Interface
-. Supports up to 3 external devices
-. Supports 8-bit or 16-bit memory components with maximum size of up to 64M bytes each.
-. Supports Mobile RAM and Cellular RAM
-. Supports Flash and SRAM/PSRAM with page mode or burst mode
-. Supports Pseudo SRAM
-. Industry standard Parallel LCD interface
-. Supports Multi-media companion chips with 8/16bits data width.
-. Flexible I/O voltage of 1.8V ~ 2.8V for memory interface.
z
User Interface
-. 6-row x 7-column keypad controller with hardware scanner.
-. Supports multiple key presses for gaming.
-. SIM/USIM controller with hardware T=0/T=1 protocol control.
-. Real Time Clock(RTC) operating with a separate power supply.
-. General Purpose I/Os (GPIOs)
-. 2sets of Pulse Width Modulation(PWM) output.
-. Alerter Output with enhanced PWM or PDM.
-. 4 ~ 10 external interrupt lines.
z
Security
-. Supports security key for code protection
-. 143-bit unique/secret chip ID
z
Connectivity
-. 3 UARTs with hardware flow control and speed up to 921600pbs.
-. IrDA modulator/Demodulator with hardware framer. Supports SIR/MIR/FIR operating Speeds.
-. Full speed USB 1.1 Device controller
Summary of Contents for MASS2
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