Chapter 2
Channel Operation
M4K708 Module: User’s Manual
page 2 - 7
2.3
Channel Control Registers and Memory Map
The Channel Control Registers must be set for each channel separately.
Write
Writing any value to the Channel Software Reset register resets the whole channel.
Register
Channel #0
Channel #1
Channel Software Reset [W]
00000 H
00400 H
Channel Control [W/R]
00002 H
00402 H
Channel Start/Stop [W/R]
00004 H
00404 H
Channel Status [R]
00006 H
00406 H
Channel Interrupt Mask [W/R]
00008 H
00408 H
Channel Interrupt Status [R]
0000A H
0040A H
Channel Interrupt Clear [W]
0000C H
0040C H
Channel Event Frequency [W/R]
0000E H
0040E H
Channel FIFO Counter [R]
00010 H
00410 H
Channel Output Triggers Mask [W/R]
00012 H
00412 H
Reserved
00014 – 00001E H
00414 – 0041E H
Receive FIFO Read [R]
00020 H
00420 H
Receive FIFO Word Type [R]
00022 H
00422 H
Receive FIFO Word Count [R]
00024 H
00424 H
Receive Spare
00026 H
00426 H
Reserved
00028 – 0003E H
00428 – 0043E H
Transmit FIFO Data Write [W]
00040 H
00440 H
Transmit FIFO First Write [W]
00042 H
00442 H
Transmit FIFO Last Write [W]
00044 H
00444 H
Reserved
00046 –00048 H
00446 – 00448 H
Transmit Interval Value [W/R]
0004A H
0044A H
Reserved
0004C – 003FE H
0044C – 007FE H
Figure 2-2
Channel Memory Maps
2.3.1
Channel Software Reset Register
Address:
xx000 (H)
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