Chapter 2
Channel Operation
page 2 - 2
Excalibur Systems
2.1
Channel Operation
Each channel’s mode of operation, either transmit or receive, is selected through
bits in the
Global Configuration Register
. Selecting the mode sets also the direction of
the channel’s FIFO. Within the channel’s Memory space there are three groups of
registers:
•
The first group is common to transmit and receive modes
•
The second group is dedicated to receive mode only
•
The third group of registers is dedicated to transmit mode only
Each channel provides interrupts/triggers or polling bits on two occasions. The first
occasion (Word Over) is set by the
Channel Event Frequency Register
with the number of
708 Words received/sent between the occasions. The second occasion (FIFO Over)
indicates a FIFO overrun/underrun Error condition. In addition the channels can be
set up in an Internal loopback configuration. This crosswire connection allows the
user to perform a full module’s internal self test by transmitting, receiving and
comparing in both directions, including interrupts and all other registers
functionality.
2.1.1
Channel Receive Operation
In receive mode, after start is activated, each 708 Word is stored in the FIFO as a
block of 103 16-bit words (see
Figure 2-3 Received 708 Word Block Structure,
on page 2-12).
The first two words in the FIFO block are Time_Tag_Lo (first) and Time_Tag_Hi,
indicating the word time stamp, then follow the 100 words comprising the 1600-bits
of the 708 Word, and finally comes the Status Word, indicating the word status
(valid or not). During the storing process, the Channel FIFO Counter is
incremented each write to the FIFO. The
Receive FIFO Word Count Register
is
incremented by 1 at the end of receiving the 708 Word. The next received 103 word
block is pushed into the FIFO immediately after it. The user can read the FIFO in
conjunction with interrupts or polling bits or counters value or
Channel Status Register
bits (FIFO not empty or half full). Each 16-bit word read from the FIFO can be
evaluated by reading the
Receive FIFO Word Type Register
immediately after it in order
to follow the block structure.
Note:
The first bit received from the 708 bus is located at the least significant bit
(LSB) of the first data word read from the fifo. In the same way each
following 16 bits are shifted in (shift right).
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