Excalibur Excalibur EPXA1 Hardware Reference Manual Download Page 39

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Altera Corporation

EPXA1 Development Board Hardware Reference Manual

Configuration

The EPXA1 device pins listed in

Table 28 on page 39

are used exclusively

for configuring the device. Refer to

“Device Configuration” on page 28

for

more information about EPXA1 configuration.

Table 28. EPXA1 Device Configuration Pins (Part 1 of 2)

Signal Name

EPXA1 Device

Pin

Board

Reference

Description

MSEL0

Configuration mode select (tied to

GND

)

MSEL1

Configuration mode select (tied to

GND

)

BOOT_FLASH

Tied high (mandatory boot from flash)

NSTATUS

AB12

Pulled high

NCONFIG

Connected to SOFT_RESET line

DCLK

R16

Pulled high

CONF_DONE

V12

Pulled high

INIT_DONE

Initialization complete LED

nCE

P19

Pulled low

nCEO

Not connected

DATA0

P18

Pulled low

DATA1

Unused. Used as general-purpose I/O

DATA2

DATA3

DATA4

DATA5

DATA6

L22

DATA7

M18

TDI

T20

J6.9

JTAG data input

TDO

J6.3

JTAG data output (to next device in the chain

TCK

Y11

J6.1

JTAG clock

TMS

U11

J6.5

JTAG mode select

TRST

JTAG reset (pulled high)

PROC_TDI

J8.5

JTAG data input

PROC_TDO

J8.13

JTAG data output (to next device in the chain)

PROC_TCK

J8.9

JTAG clock

PROC_TMS

J8.7

JTAG mode select

PROC_TRST

J8.3

JTAG reset (pulled high)

DEV_CLR_n

R20

T15, T14

FPGA clear signal taken to test pad T15, placed next to
grounded test pad T14 near SW1; allows use of this signal, if
required

Summary of Contents for Excalibur EPXA1

Page 1: ...MNL EPXA1DEVBD 1 1 EPXA1 Development Board 101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com Hardware Reference Manual September 2002 Version 1 1 ...

Page 2: ...r numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use...

Page 3: ...ou to search the contents of a PDF file Click on the binoculars icon in the top toolbar to open the Find dialog box Bookmarks serve as an additional table of contents Thumbnail icons which provide miniature previews of each page provide a link to the pages Numerous links shown in green text allow you to jump to related information Table 1 Revision History Date Description August 2002 First publica...

Page 4: ...e 1 You can also contact your local Altera sales office or sales representative Table 2 How to Contact Altera Information Type USA Canada All Other Locations Technical support http www altera com mysupport http www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time 408 544 7000 1 7 00 a m to 5 00 p m Pacific Time Product literature http www altera com http www altera com Alte...

Page 5: ...file name project name pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of Quartus II Help topics are shown in quotation marks Example Configuring a FLEX 10K or FLEX 8000 Device with the BitBlaster Download Cable Courier type Signal and port ...

Page 6: ...Notes ...

Page 7: ...umper Configuration for the Clock Inputs 26 Sources for the Stripe Clock Reference 27 Sources for CLK3 CLK4 28 Device Configuration 28 Booting from Flash Memory 28 Using the Quartus II Software 29 JTAG Interfaces 29 Power Supply 30 Test Points Test Pads 32 Signals 33 UART 33 Expansion Headers 34 Configuration Debugging Interfaces 37 Development Board Pin Outs 38 Configuration 39 SDR SDRAM Interfac...

Page 8: ...viii Altera Corporation Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual Anti Static Handling 48 Power Consumption 48 Test Core Functionality 49 Unused I O Pins 50 ...

Page 9: ...ulti ICE header for debugging Expansion headers for greater flexibility and capacity 5 V standard expansion header 5 V long expansion card header Additional user interface features One user definable 8 bit dual in line package DIP switch block Four user definable push button switches plus reset switch Ten user definable LEDs plus function specific LEDs Test points provided to facilitate system dev...

Page 10: ...XA1 development board features the lowest cost member of the Excalibur family the EPXA1 The EPXA1 device contains an ARM922T 32 bit RISC microprocessor combined with an APEX 20KE FPGA in a 484 pin FineLine BGA package Table 1 on page 10 lists the main features of the device Table 1 EPXA1 Device Features Feature Capacity Maximum system gates 263 000 Typical gates 100 000 LEs 4 160 ESBs 26 Maximum R...

Page 11: ...on the development board Table 2 EPXA1 Device Peripherals Peripheral Description ARM922T 32 bit RISC processor For speed grade 1 up to 200 MHz For speed grade 2 up to 166 MHz Interrupt controller Used for the interrupt system Internal single port SRAM 32 Kbytes Internal dual port SRAM 16 Kbytes SDRAM controller Interfaces between the internal system bus and SDRAM External SDRAM Refer to the Excali...

Page 12: ... Altera Corporation EPXA1 Development Board Hardware Reference Manual Figure 2 Prototyping Area on the EPXA1 Development Board Figure 3 on page 13 shows how the pins are located in the prototyping area A1 ...

Page 13: ...face Description 10 100 Ethernet with full and half duplexing This interface consists of an RJ45 connector and transformer connected to the EPXA1 using an external MAC PHY device connected to the EBI Expansion headers These headers are used to connect Altera daughter cards or customer designed daughter cards to develop and test custom circuitry IEEE Std 488 RS 232 serial interfaces This is a 250 k...

Page 14: ...are used as outputs contention occurs because the bus transceiver is always active If these pins are not used as part of a design ensure that they remain in the high impedance state All unused I O pins can be set to tri state mode in the Quartus II software see Unused I O Pins on page 50 See Table 23 on page 33 for information on the RS 232 signals Table 4 shows the UART interface characteristics ...

Page 15: ...select signal registers The Ethernet and flash memory device share addresses and data on the EBI Memory Interfaces The EPXA1 development board supports the following types and capacities of on board memory as listed in Table 7 Figure 4 on page 16 shows the location of the on board memory Table 6 Ethernet LEDs Board Reference Signal Description RJ1 LEDA LEDA Green LED This defaults to being set on ...

Page 16: ...Board Memory Two flash memory chips FLASH1 and FLASH2 are connected to the EBI of the EPXA1 development board see Figure 5 Figure 5 Flash Memory Interface SDRAM pin 1 indicated Flash memory pin 1s indicated EPXA1 EBI A1 A22 D0 D15 OE WE CE A0 A21 Flash Memory 2 x 4 Mbyte EBI_CS0 EBI_CS1 FLASH1 FLASH2 PHY MAC ...

Page 17: ...elopment board Figure 6 Switches LEDs on the EPXA1 Development Board User Defined LEDs On the EPXA1 development board there are ten user definable LEDs in a graph type LED package DG1 They connect directly to the EPXA1 device I O pins and can be used for any kind of application Table 8 on page 18 lists the user LEDs on the development board Ethernet TX RX LEDs UART LEDs NPOR SOFT_RESET_N SW6 pin 1...

Page 18: ...F W22 USER_LED5 3 3 DG1_E Y17 USER_LED4 3 3 DG1_D Y18 USER_LED3 3 3 DG1_C Y19 USER_LED2 3 3 DG1_B Y20 USER_LED1 3 3 DG1_A Y21 USER_LED0 3 3 Table 9 Function Specific LED Usage Signal Board Reference EPXA1 I O Pin or Board Connector Description Voltage V INIT_DONE D15 K7 Used by FPGA initialization signifies that initialization is complete 3 3 VCC_5V D12 5 V power indicator 5 VCC_3V3 D13 3 3 V powe...

Page 19: ...Low Switch Name EPXA1 I O Pin Signal Voltage V SW6_1 V20 USER_SW7 3 3 SW6_2 V19 USER_SW6 3 3 SW6_3 V18 USER_SW5 3 3 SW6_4 V17 USER_SW4 3 3 SW6_5 V16 USER_SW3 3 3 SW6_6 U21 USER_SW2 3 3 SW6_7 U20 USER_SW1 3 3 SW6_8 U19 USER_SW0 3 3 Table 11 Push Button Switches Push Button EPXA1 I O Pin Signal Use Voltage V SW1 H1 NPOR Active low switch that generates a full power on reset when pressed for more tha...

Page 20: ...er pins 7 2 10 2 20 2 plus an extra 20 2 header pins Figure 7 on page 20 shows the location of the expansion headers on the EPXA1 development board Figure 7 EPXA1 Development Board Expansion Header Connectors The expansion header interfaces can be used to interface to special function daughter cards contact your Altera representative for details of the daughter cards available for use with the exp...

Page 21: ... J1 power input plug Numerous ground connections Card select I O RC filtered I O Long Expansion Header The long expansion header interface shares the same characteristics as the standard interface and has the following additional pins in use Two regulated 3 3 V power supply pins Sixteen address pins Sixteen data pins Expansion Header Pin Details In addition the following points apply to either sta...

Page 22: ...eaders Table 13 on page 22 shows the definitions for the EPXA1 device signals available to the standard expansion header interface The definitions are used with Altera daughter cards The general purpose I O signals can be used as required See Table 24 on page 34 for standard expansion header pin out details The long expansion header includes the signals in Table 13 plus the additional signals in F...

Page 23: ...etails about the expansion header interface Jumper Configuration The jumpers on the EPXA1 development board serve several functions Clock distribution Enabling clocks JTAG configuration Figure 8 on page 23 shows the location of jumpers on the development board Figure 8 Jumper Locations on the EPXA1 Development Board Table 15 on page 24 lists the jumper settings and their uses JSELECT J5 CLKA Selec...

Page 24: ...clock input via SMA connector SMA1 The location of the clocks on the development board is shown in Figure 9 Figure 9 Clocks on the EPXA1 Development Board Table 15 Jumpers on the EPXA1 Development Board Jumper Function Pins 1 2 Connected Pins 2 3 Connected JSELECT J5 1 JTAG connector selection ARM922 TAP available on Multi ICE connector ARM922 TAP available on JTAG connector CLKA Select J13 Clock ...

Page 25: ...ck used to drive the embedded stripe of the EPXA1 Dedicated input selected from either the SMA connector or the 25 MHz crystal oscillator using jumper CLKA Select J13 EPXA1 CLKA_1 U1 CLK1p Dedicated pin that drives PLL1 EPXA1 CLKA_2 R21 CLK2p Dedicated pin that drives PLL2 EPXA1 CLKA_3 OSC_BUFF1 J3 9 H5V_OSC Clock to long expansion header Long expansion header CLKA_4 OSC_BUFF2 J11 9 H5V_OSC Clock ...

Page 26: ...n which devices are used Two clocks drive each expansion header two from the main clock buffer and two from buffered copies of the EPXA1 PLL2 outputs Jumper Configuration for the Clock Inputs Jumpers CLKA Select J13 and CLKB Select J14 are used to select different clock inputs CLKA Select is used to determine the clock supply to the EPXA1 device clock reference two of the four PLLs in the FPGA and...

Page 27: ...the 25 MHz On board Oscillator To use the 25 MHz on board oscillator set CLKA Select to position 1 2 to select it Using the SMA Connector To select the SMA connector follow the steps below 1 Remove any alternative 5 V DIL14 oscillator from the socket XSKT1 2 Apply an external clock source to the SMA connector The clock signal should be a maximum 5 VPP 3 Set CLKA Select to position 2 3 Table 17 CLK...

Page 28: ...on There are two methods of programming and configuring the EPXA1 device Booting from flash memory Using the Quartus II software to configure the device via JTAG See JTAG Interfaces on page 29 for more details about using the JTAG interface On the EPXA1 device the settings of BOOT_FLASH MSEL0 and MSEL1 determine the configuration mode and method On the EPXA1 development board BOOT_FLASH MSEL0 and ...

Page 29: ...e EPXA1 device via JTAG using either the MasterBlaster or ByteBlasterMV download cables f For further details of how to create a sof file and configure the EPXA1 device via JTAG consult the Quartus II Help JTAG Interfaces There are two JTAG connectors on the EPXA1 development board as shown in Figure 10 Figure 10 JTAG Interfaces on the EPXA1 Development Board The JTAG connector J6 is used to conne...

Page 30: ...using Altera RDI via a ByteBlasterMV or MasterBlaster cable the JSELECT jumper must be set to 2 3 when using Multi ICE or a compatible device on the Multi ICE connector JSELECT must be set to 1 2 f For further details about jumper settings refer to Table 15 on page 24 Tables 26 and 27 starting on page 37 list the pin outs of the JTAG and Multi ICE connectors Power Supply A 12 V 20 W supply unit po...

Page 31: ...header depends on how much power is consumed by the rest of the board but should not exceed 100 mA Three function specific status LEDs indicate the presence of 1 8 V 3 3 V and 5 V to the board as listed in Table 18 on page 31 Tables 19 through 22 list the estimated maximum power supply requirements for the development board modules The typical power supply requirement for the development board is ...

Page 32: ... signals test pads are provided on the board annotated as Tx they are listed in Table 36 on page 45 Table 21 3 3 V Supply Requirements Module Max mA EPXA1 I O 500 sum over all I O pins SDRAM 285 Flash memory 45 2 90 UARTs 20 Ethernet 140 LEDs 15 18 270 5 2 10 280 Crystal oscillator 10 Clock buffers 37 22 59 Expansion headers 500 per header Table 22 1 8 V Supply Requirements Module mA EPXA1 device ...

Page 33: ...ure 12 UART DB9 Male Connector Table 23 lists the UART DB9 signals Note 1 The EPXA1 development board has two DB9 male connectors Table 33 on page 44 lists pin out information for the UARTs on the development board 1 2 3 4 5 6 7 8 9 Table 23 DTE UART DB9 Male Connector Signals 1 Pin Signal Description 1 DCD Data carrier detect 2 RXD Receive data 3 TXD Transmit data 4 DTR Data terminal ready 5 GND ...

Page 34: ...4 B_H5V_IO29 9 B_H5V_IO34 14 B_H5V_IO39 5 B_H5V_IO30 10 B_H5V_IO35 10 2 Header J10 1 Vcc_UNREG 8 GND 15 VCC_3V3 2 GND 9 H5V_OSC 16 GND 3 VCC_A2 10 GND 17 NC 4 GND 11 H5V_CLK 18 GND 5 VCC_3V3 12 GND 19 NC 6 GND 13 H5V_CLKOUT 20 GND 7 VCC_3V3 14 GND 20 2 Header J15 1 H5_RST_N 15 B_H5V_IO12 29 B_H5V_IO21 2 GND 16 B_H5V_IO13 30 GND 3 B_H5V_IO0 17 B_H5V_IO14 31 B_H5V_IO22 4 B_H5V_IO1 18 B_H5V_IO15 32 B...

Page 35: ...15 VCC_3V3 2 GND 9 H5V_OSC 16 GND 3 VCC_A 10 GND 17 NC 4 GND 11 H5V_CLK 18 GND 5 VCC_3V3 12 GND 19 NC 6 GND 13 H5V_CLKOUT 20 GND 7 VCC_3V3 14 GND 20 2 Header J9 1 H5_RST_N 15 B_H5V_IO12 29 B_H5V_IO21 2 GND 16 B_H5V_IO13 30 GND 3 B_H5V_IO0 17 B_H5V_IO14 31 B_H5V_IO22 4 B_H5V_IO1 18 B_H5V_IO15 32 B_H5V_IO23 5 B_H5V_IO2 19 GND 33 B_H5V_IO24 6 B_H5V_IO3 20 Removed 34 NC 7 B_H5V_IO4 21 B_H5V_IO16 35 B_...

Page 36: ...p_A0 17 B_eup_A6 31 B_eup_A12 4 B_eup_D0 18 B_eup_D6 32 B_eup_D12 5 B_eup_A1 19 B_eup_A7 33 B_eup_A13 6 B_eup_D1 20 B_eup_D7 34 B_eup_D13 7 B_eup_A2 21 B_eup_A8 35 B_eup_A14 8 B_eup_D2 22 B_eup_D8 36 B_eup_D14 9 B_eup_A3 23 B_eup_A9 37 B_eup_A15 10 B_eup_D3 24 B_eup_D9 38 B_eup_D15 11 B_eup_A4 25 B_eup_A10 39 GND 12 B_eup_D4 26 B_eup_D10 40 GND 13 GND 27 GND 14 GND 28 GND Table 25 Long Expansion H...

Page 37: ...G Mode Signal Description 1 TCK Clock signal 2 GND Signal ground 3 TDO Data from device 4 VCC Power supply 5 TMS JTAG state machine control 6 VIO Reference voltage for MasterBlaster output driver 7 NC No connect 8 No connection 9 TDI Data to device 10 GND Signal ground Table 27 Multi ICE Connector Signals Part 1 of 2 Pin Signal Description Direction 1 VCC Power supply N A 2 VCC Power supply N A 3 ...

Page 38: ...ft in a high impedance state to avoid contention This section details the pins on the EPXA1 device which are assigned to the following purposes Configuration SDR SDRAM EBI for the Ethernet and flash memory devices UARTs 1 and 2 Fast I O pins Expansion headers Prototyping area Test pads Pin assignments are grouped into tables for control pins address pins and data bus pins where appropriate The tab...

Page 39: ...FT_RESET line DCLK R16 Pulled high CONF_DONE V12 Pulled high INIT_DONE K7 Initialization complete LED nCE P19 Pulled low nCEO H3 Not connected DATA0 P18 Pulled low DATA1 K3 Unused Used as general purpose I O DATA2 J1 DATA3 L5 DATA4 L4 DATA5 L6 DATA6 L22 DATA7 M18 TDI T20 J6 9 JTAG data input TDO J4 J6 3 JTAG data output to next device in the chain TCK Y11 J6 1 JTAG clock TMS U11 J6 5 JTAG mode sel...

Page 40: ...able GPIO nWS M21 Write strobe GPIO nRS P16 Read strobe GPIO nCS N20 Signal providing handshaking between devices GPIO CS P17 Chip select GPIO RDYnBSY K4 Ready busy GPIO CLKUSR L7 Clock signal GPIO Table 28 EPXA1 Device Configuration Pins Part 2 of 2 Signal Name EPXA1Device Pin Board Reference Description Table 29 SDR SDRAM Control Signal Pin Outs Signal Name EPXA1 Device Pin Board Reference Descr...

Page 41: ... F18 U13 5 SD_DQ3 C21 U13 7 SD_DQ4 E20 U13 8 SD_DQ5 F19 U13 10 SD_DQ6 F20 U13 11 SD_DQ7 G18 U13 13 SD_DQ8 H19 U13 42 SD_DQ9 G20 U13 44 SD_DQ10 E22 U13 45 SD_DQ11 H18 U13 47 SD_DQ12 G21 U13 48 SD_DQ13 H20 U13 50 SD_DQ14 H17 U13 51 SD_DQ15 H22 U13 53 SD_A0 B17 U13 23 SD_A1 G16 U13 24 SD_A2 D16 U13 25 SD_A3 F16 U13 26 SD_A4 A19 U13 29 SD_A5 E16 U13 30 SD_A6 B18 U13 31 SD_A7 F17 U13 32 SD_A8 C17 U13 3...

Page 42: ... Output enable EBI_WE_N G8 U9 34 FLASH1 11 FLASH2 11 Write enable EBI_CS0 C2 FLASH1 26 Chip select flash memory 1 EBI_CS1 B3 FLASH2 26 Chip select flash memory 2 EBI_CS2 D3 Chip select not used EBI_CS3 C4 U9 43 Chip select ethernet EBI_CLK C3 U9 44 EBI clock EBI_ACK B4 EBI acknowledge not used Table 32 EBI Data Bank and Address Bus Pin Outs Part 1 of 2 Signal Name EPXA1 Device Pin Ethernet Board R...

Page 43: ...I_A7 A6 U9 86 FLASH1 19 FLASH2 19 EBI_A8 F8 U9 87 FLASH1 18 FLASH2 18 EBI_A9 B7 U9 88 FLASH1 8 FLASH2 8 EBI_A10 D8 U9 89 FLASH1 7 FLASH2 7 EBI_A11 C8 U9 90 FLASH1 6 FLASH2 6 EBI_A12 E8 U9 91 FLASH1 5 FLASH2 5 EBI_A13 A7 U9 92 FLASH1 4 FLASH2 4 EBI_A14 G9 U9 93 FLASH1 3 FLASH2 3 EBI_A15 B8 U9 94 FLASH1 2 FLASH2 2 EBI_A16 F9 FLASH1 1 FLASH2 1 EBI_A17 A8 FLASH1 48 FLASH2 48 EBI_A18 E9 FLASH1 17 FLASH...

Page 44: ... Connector Pin Device Signal EPXA1 Device Pin Connector Pin Device Signal K4 P1 4 DTR E6 P2 4 XA_DTR J1 P1 3 TXD G5 P2 3 XA_TXD K5 P1 2 RXD F2 P2 2 XA_RXD L5 P1 6 DSR G4 P2 6 XA_DSR K3 P1 7 RTS E2 P2 7 XA_RTS L7 P1 9 RI F3 P2 9 XA_RI L6 P1 1 DCD F6 P2 1 XA_DCD L4 P1 8 CTS F1 P2 8 XA_CTS P1 5 GND P2 5 GND Table 34 EPXA1 Fast I O Pins EPXA1 Pin Name Board Signal Description EPXA1 Pin ExpansionHeader...

Page 45: ... Connected To TP1 GND TP6 1V8 TP2 GND TP7 GND TP3 EBI_CLK TP8 GND TP4 GND TP9 5V TP5 3V3 TP10 GND Table 36 EPXA1 Development Board Test Pads Test Pad Connected To Test Pad Connected To T1 EBI chip select 3 T9 EBI byte enable 1 T2 EBI write enable T10 JTAG clock T3 Ethernet loopback active output T11 JTAG data output T4 EBI output enable T12 JTAG mode select T5 EBI chip select 0 T13 JTAG data input...

Page 46: ...toIO_17 L21 protoIO_7 N20 D VCC_5V GND VCC_3V3 protoIO_26 K19 protoIO_16 L22 protoIO_6 N22 E VCC_5V GND VCC_3V3 protoIO_25 K20 protoIO_15 M16 protoIO_5 P16 F VCC_5V GND VCC_3V3 protoIO_24 K21 protoIO_14 M17 protoIO_4 P17 G VCC_5V GND VCC_3V3 protoIO_23 L15 protoIO_13 M18 protoIO_3 P20 H VCC_5V GND VCC_3V3 protoIO_22 L16 protoIO_12 M19 protoIO_2 P22 J VCC_5V GND VCC_3V3 protoIO_21 L17 protoIO_11 M2...

Page 47: ...J2 4 R1 J2 33 R7 J9 10 Y3 J2 5 W2 J2 34 N2 J9 11 Y2 J2 6 P7 J2 35 R3 J9 12 W11 J2 7 W1 J2 36 N1 J9 13 W10 J2 8 P6 J2 37 R2 J9 14 W9 J2 9 V3 J2 38 M7 J9 15 W8 J2 10 P5 J4 3 AB9 J9 16 W7 J2 11 V2 J4 4 T10 J9 17 W5 J2 12 P4 J4 5 T9 J9 18 V11 J2 15 U4 J4 6 R10 J9 21 V10 J2 16 P3 J4 7 AB10 J9 23 V9 J2 17 U3 J4 8 M6 J9 25 V8 J2 18 P2 J4 9 M5 J9 27 V7 J2 19 U2 J4 10 M4 J9 28 V6 J2 20 P1 J4 11 M3 J9 29 V5...

Page 48: ...unning diagnostics is approximately 250 mA A 20 W power supply is supplied as part of the EPXA1 development kit It is capable of meeting the maximum power requirement imposed by the board if all interfaces are used within specification Table 39 Development Board Standard Expansion Header Header 2 I O Pin Outs Board Connector EPXA1 Device Board Connector EPXA1 Device Board Connector EPXA1 Device J1...

Page 49: ... memory test t Toggle terminal output between UARTS The Ethernet internal loopback test checks that the Ethernet chip is working properly the external loopback test is for manufacturing test only The toggle between the UARTS switches the output of the program between P1 and P2 P2 is connected to the UART in the EPXA1 embedded stripe P1 is connected to a UART which has been programmed into the FPGA...

Page 50: ...ate mode in the Quartus II software To set the unused I O pins to tri state mode run the Quartus II software open the appropriate project and follow the steps below 1 Choose Compile Mode Processing menu 2 Choose Compiler Settings Processing menu 3 Click the Chips Devices tab 4 Click Device Pin Options 5 Click the Unused Pins tab 6 Select As inputs tri stated 7 Click Apply ...

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