Excalibur Excalibur EPXA1, Hardware Reference Manual

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26 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Note:
(1) See “Jumper Configuration for the Clock Inputs” for details of selecting a source for the stripe
CLK_REF
pin.
Up to two sources can be selected to clock the devices on the development
board at any given time. Of the three sources available, the dedicated
25-MHz on-board oscillator cannot be varied in frequency.
As detailed in Table 16 , four of the clock buffer outputs drive dedicated
inputs on the EPXA1 device.
One is the dedicated input providing the embedded stripe reference clock
CLK_REF
. The four FPGA clocks service the ClockLock ™ and ClockBoost ™
circuitry on the Excalibur device. The clocks on the development board
can be configured as required, depending on which devices are used.
Two clocks drive each expansion header: two from the main clock buffer
and two from buffered copies of the EPXA1 PLL2 outputs.
Jumper Configuration for the Clock Inputs
Jumpers CLKA Select (J13) and CLKB Select (J14) are used to select
different clock inputs. CLKA Select is used to determine the clock supply
to the EPXA1 device clock reference, two of the four PLLs in the FPGA,
and the two expansion headers. CLKB Select can be used to route an
additional, alternative clock input to the EPXA1 device.
During development, if you need to run the clock at a rate other than
25 MHz, you can do so using the SMA connector or an alternative 5-V
DIL14 oscillator.
CLKLK_FB2p N21
CLKLK_FB2p
Dedicated pin that allows external feedback to
PLL2. Available on test pad T14 (see
Table 36
on page 45 )
EPXA1
Table 16. EPXA1 Development Board Clocks (Part 2 of 2)
Clock Source EPXA1 Pin
(or Board
Connection)
Signal Name Description Target
Device