Excalibur DAS-429PCI/Mx User Manual Download Page 46

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Chapter 3

Transmit Mode

DAS-429PCI/Mx: User’s Manual

page 3 - 7

word in

instruction
block

The Word Count is used to specify the number of 32 bit ARINC-429 Data Words

in this instruction block (1 – 65535).

The Interword delay is used to set the delay (4 - 65504) between words in the

block and between the final word in this block and the first word in the following

block. Its resolution is 1 bit time. For high speed this gives it a range of 40

microseconds (interword value 4) to just over 655 milliseconds (interword value

65504). For low speed the range is 320 microseconds (interword value 4) to over 5

seconds (interword value 65504).

Note:

The ARINC-429 specification does not allow interword times less than 4

bit times, so interword delay values of less than 4 will be interpreted as

the minimum legal interword time.

The Transmit Data Pointer register is used to set the start address of the

transmit data buffer. The address must be a word boundary. The size of the

buffer is determined by the Word Count value.

3.3.1

Control Word Definition

Bit

Bit Name

Description

01-15

Reserved

Parity Error

0 = Normal Odd Parity (Standard

ARINC-429 parity)

1 = Even Parity (Error Injection)

Control Word Definition

3.3.2

Word Count

3.3.3

Interword Delay

3.3.4

Transmit Data Pointer

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Summary of Contents for DAS-429PCI/Mx

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com DAS 429PCI Mx Multi channel ARINC 429 Test and Simulation Board for PCI Systems User s Manual Artisan Technology Group Quality Inst...

Page 3: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 4: ...ss Register XROM 1 15 1 5 13 Interrupt Line Register INTLN 1 15 1 5 14 Interrupt Pin Register INTPIN 1 16 1 5 15 Minimum Grant Register MINGNT 1 16 1 5 16 Maximum Latency Register MAXLAT 1 16 1 6 PCI...

Page 5: ...3 3 3 2 3 Channel x Transmit Instruction Counter 3 4 3 2 4 Channel x Transmit Loop Counter 3 4 3 2 5 Channel x Transmit Current Word Register 3 4 3 2 6 Channel x Transmit Current Loop Register 3 4 3...

Page 6: ...eive Filter Table Start Address 4 15 4 5 7 Channel x Receive Data Word Count Register 4 16 4 5 8 Channel x Receive Buffer Wraparound Register 4 16 4 5 9 Channel x Receive Data Word Counter Trigger Reg...

Page 7: ...eive Sequential Mode Buffer Structure 4 3 Figure 4 2 Receive Data Word Format 4 4 Figure 4 3 Receive Word Order 4 4 Figure 4 4 Time Tag Word Description 4 5 Figure 4 5 Receive Sequential Mode Filter T...

Page 8: ...PCISTS 1 9 1 5 5 Revision Identification Register RID 1 10 1 5 6 Class Code Register CLCD 1 10 1 5 7 Cache Line Size Register CALN 1 11 1 5 8 Latency Timer Register LAT 1 11 1 5 9 Header Type Registe...

Page 9: ...can be accessed directly in real time The board supports filtering of receive data and multiple data storage modes Status and time tag information are appended to each word The transmit channels opera...

Page 10: ...ARINC 429 MODULE 0 M429R4T2 ARINC 429 MODULE 1 M429R4T2 ARINC 429 MODULE 2 M429R4T2 ARINC 429 MODULE 3 M429R4T2 RX0 i TX0 j RX1 i TX1 j RX2 i TX2 j RX3 i TX3 j 40 MHz OSC i Receive channel index 0 1 3...

Page 11: ...oards The DAS 429PCI Mx complies with the Plug and Play specification of the PCI standard and as such its absolute address is determined by the BIOS at system start up Warning Wear a suitably grounded...

Page 12: ...ure is shown below in Figure 1 3 Figure 1 3 DAS 429PCI Mx Memory Structure Note Throughout this manual the following terms are used interchangeably Page 1 and Module 0 Page 2 and Module 1 Page 3 and M...

Page 13: ...ation Space Header MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3C H Reserved 0s 38 H Reserved 0s 34 H Expansion ROM Base Address not used 30 H Reserved 0s 2C H Reserved 0s 28 H Base Address Register...

Page 14: ...register contains the vendor assigned device identification number 1 5 1 Vendor Identification Register VID Address 00 01 H Power up value 1405 H Boot load External nvRAM offset 040 41 H Attribute Rea...

Page 15: ...rs When a parity error is detected the PCI bus signal PERR is asserted This bit is cleared parity testing disabled upon the assertion of RESET 05 Palette Snoop Enable Always set to 0 04 Memory Write a...

Page 16: ...location 12 Received Target Abort R WC This bit is set whenever this device has one of its own initiated cycles terminated by the currently addressed target This bit can be reset by writing a 1 to thi...

Page 17: ...value 00 H Boot load External nvRAM EPROM offset 048 H Attribute Read only Size 8 bits Bit Description 00 07 Revision identification number Revision Identification Register 1 5 6 Class Code Register C...

Page 18: ...d Boot load Not used Attribute Read only Size 8 bits Bit Description 00 07 Cache Line Size RO Cache Line Size Register 1 5 8 Latency Timer Register LAT Address 0D H Power up value 00 H Boot load Exter...

Page 19: ...ribute Read only Size 8 bits Bit Description 07 0 PCI Controller is a single function PCI device 00 06 Always returns 0 Header Type Register 1 5 10 Built In Self Test Register BIST Address 0F H Power...

Page 20: ...ess register from the PCI bus and then reading that register back The number of 0s returned starting from D4 for memory space and D2 for I O space toward the high order bits reveals the amount of addr...

Page 21: ...o bits identify whether the memory space is 32 or 64 bits wide and if the space location is restricted to be in the first megabyte of memory space The encoding is as follows Bits 02 01 Description 0 0...

Page 22: ...r unknown or no connection for the system interrupt This register is boot loaded from the external boot memory if present and may be written by the PCI interface 1 5 12 Expansion ROM Base Address Regi...

Page 23: ...nvRAM offset 7D H Attribute Read only Size 8 bits Bit Bit Name Description 03 07 Reserved All zeros RO 00 02 Pin Number Bit 02 Bit 01 Bit 00 Description 0 0 0 0 0 1 None INTA Interrupt Pin Register 1...

Page 24: ...upt Status Register Address 1CH Attribute Read Write Size 32 bits Bit Bit Name Description 28 31 Not Used Don t Care 27 IFLAG3 When set indicates that Module 3 generated interrupt 26 IFLAG2 When set i...

Page 25: ...Chapter 1 Introduction page 1 18 Excalibur Systems Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 26: ...iver Merge Buffer Wraparound Register 2 12 2 5 7 Receiver Merge Word Count Trigger Register 2 12 2 5 8 Receiver Merge Interval Count Trigger Register 2 12 2 5 9 Receiver Merge Label Trigger Register 2...

Page 27: ...e Transmitter related Channel Control registers Program the Channel Configuration registers bit rate rise time etc Update the Transmit Instruction Stack pointer for each channel Update the Transmit In...

Page 28: ...0 00AE H Channel Control Register Block 1 00B0 00DE H Channel Control Register Block 2 00E0 010E H Channel Control Register Block 3 0110 013E H Channel Control Register Block 4 0140 016E H Channel Con...

Page 29: ...tart Address registers are written by the board after reset operation has been completed Reserved 0000 0001 H Global Software Reset Register 0002 H Global Interrupt Reset Register 0004 H Global Interr...

Page 30: ...ule active interrupt A value of 0 indicates no interrupt has been generated 2 3 2 Global Interrupt Reset Register Address 0004 H Bit Description 04 15 X Don t Care 03 Module 3 Interrupt Reset 02 Modul...

Page 31: ...nter 0020 H Receiver Merge End Pointer 0022 H Receiver Merge Current Pointer 0024 H Receiver Merge Filter Table Start Address 0026 H Receiver Merge Word Counter 0028 H Receiver Merge Buffer Wraparound...

Page 32: ...A change in a channel s Configuration register or in the Receiver Data Storage Mode register is acted upon by the firmware only after the Start Stop register contains a 0 for at least 1 sec 2 When a t...

Page 33: ...n this register will be cleared except for the Internal Error bit which will be set An example of an illegal condition would be setting a pointer register to a byte boundary address odd address Read T...

Page 34: ...e Status Word in this case is tagged with Channel Code information The Merge Module Control registers are used only when the Merge Mode option is selected See Receiver Merge Mode Control Registers pag...

Page 35: ...gister is busy Write Writing any non zero value to the Reset Time Tag register resets the Time Tag to 0 Read The module will write the value E429 H into the Module ID register when it has finished its...

Page 36: ...e Receiver Merge Current pointer indicates the current address where the next ARINC receive word is to be placed in the Receiver buffer This pointer value is incremented after the entire receiver bloc...

Page 37: ...ter must also be set See Receiver Merge Interrupt Condition Register page 2 14 Note This trigger is set when the value in the Receiver Merge Word Counter matches the value set in this register Write T...

Page 38: ...ge Label Trigger Register Address 0032 H 00 LABEL 15 8 7 0 Receiver Merge Label Trigger Register 2 5 10 Receiver Merge Configuration Register Address 0034 H Bit Bit Name Description 10 15 Reserved 0 0...

Page 39: ...ith interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit To reset status bits write a 0 to this regis...

Page 40: ...annel x Transmit Current Loop Register 3 4 3 2 7 Channel x Interrupt Condition Register 3 5 3 2 8 Channel x Status Register 3 5 3 3 Transmit Instruction Stack 3 6 3 3 1 Control Word Definition 3 7 3 3...

Page 41: ...hannel 2 Interrupt Condition Register 0106 H Channel 2 Status Register 0108 H Reserved 010A 010E H Figure 3 1 Channel 2 Control Register Block Map Channel 5 Configuration Register 0170 H Reserved 0172...

Page 42: ...been modified Write The Channel x Transmit Instruction Stack pointer sets the starting address of the Transmit Instruction Stack The address must be a word boundary within the Transmit Instruction St...

Page 43: ...currently being sent out The register is updated as the last bit of the word is transmitted After the first word in a loop goes out the register will be incremented to 1 After the final word in a loo...

Page 44: ...ant bits are used for transmit channels and only bits 02 through 06 are used for receive channels See Channel x Status Register on page 4 18 in Chapter 4 Receive Monitor Mode 3 2 7 Channel x Interrupt...

Page 45: ...third word the Interword Delay determines the delay time between words from the same data buffer The fourth word contains a 16 bit user supplied data pointer This Transmit Data Pointer is a 16 bit add...

Page 46: ...value 4 to over 5 seconds interword value 65504 Note The ARINC 429 specification does not allow interword times less than 4 bit times so interword delay values of less than 4 will be interpreted as t...

Page 47: ...word bits are transmitted in the following order Figure 3 6 32 bit ARINC Word Bit order 3 Bits 09 through 29 are ordered from LSB to MSB opposite from the Label field which is organized MSB to LSB It...

Page 48: ...ontrol Register Block Map 4 10 4 4 2 Channel 1 Control Register Block Map 4 11 4 4 3 Channel 3 Control Register Block Map 4 12 4 4 4 Channel 4 Control Register Block Map 4 13 4 5 Receive Channel Contr...

Page 49: ...ernatively Sequential Mode offers the user the capability of storing only the ARINC data without the Time Tag and Status Words This global selection affects all receive channels See Receiver Data Stor...

Page 50: ...ointer is reached or will wrap around to the beginning of the buffer depending upon the condition of the Receiver Wrap Around bit in the Channel Configuration Register The Time tag resolution is 10 se...

Page 51: ...d parity received while 1 denotes even parity received 2 The ARINC word bits are received in the following order Figure 4 3 Receive Word Order 3 Bits 09 through 29 are ordered from LSB to MSB opposite...

Page 52: ...ed in dual port RAM This latency is affected by the number of channels and data rate of these channels The Time tag reflects the time the Word is written to dual port RAM rather than the time the Word...

Page 53: ...escription 02 07 Reserved 01 1 Interrupt 0 Don t Interrupt 00 1 Store Word 0 Don t Store Label Control Byte Structure Write Control Byte Label 377 Octal Control Byte for Label x Control Byte for Label...

Page 54: ...data is in memory Receive Sequential Mode Status Word Read Bit Bit Name Description 12 15 Reserved 08 11 Merge Channel Code 100 Data received over channel 4 011 Data received over channel 3 001 Data r...

Page 55: ...a Receiver Look up Table Pointer that you can program You can poll the operational status of each channel and generate interrupts in various circumstances 4 3 2 Receive Look Up Table Mode Diagram Fig...

Page 56: ...4 Reserved 07 Valid Word Global Bit Indicates that the received ARINC 429 word was valid in all respects 04 06 Reserved 03 Parity Error Indicates that an even parity error was detected in the ARINC 42...

Page 57: ...s 008A H Channel 0 RCV Filter Table Start Address 008C H Channel 0 RCV Data Word Count Register 008E H Channel 0 RCV Buffer Wraparound Register 0090 H Channel 0 RCV Word Counter Trigger 0092 H Reserve...

Page 58: ...RCV Filter Table Start Address 00BC H Channel 1 RCV Data Word Count Register 00BE H Channel 1 RCV Buffer Wraparound Register 00C0 H Channel 1 RCV Word Counter Trigger 00C2 H Reserved 00C4 H Channel 1...

Page 59: ...ilter Table Start Address 011C H Channel 3 RCV Data Word Count Register 011E H Channel 3 RCV Buffer Wraparound Register 0120 H Channel 3 RCV Word Counter Trigger 0122 H Reserved 0124 H Channel 3 RCV I...

Page 60: ...RCV Filter Table Start Address 014C H Channel 4 RCV Data Word Count Register 014E H Channel 4 RCV Buffer Wraparound Register 0150 H Channel 4 RCV Word Counter Trigger 0152 H Reserved 0154 H Channel 4...

Page 61: ...ed for channels 3 and 4 must be the same Therefore bit 00 of the Channel Configuration Register is not used for channels 1 and 4 4 5 1 Channel x Configuration Register Bit Bit Name Description 10 15 0...

Page 62: ...presents the byte offset into the modules memory of the first location of the look up table The module will store one ARINC 429 data block for each Label received The data block contains 32 bit ARINC...

Page 63: ...65535 If you want to generate an interrupt you must also set the appropriate bit in the Channel x Interrupt Condition Register See Channel x Interrupt Condition Register page 4 17 Note This trigger is...

Page 64: ...ive Label Trigger Register Write 00 Label 15 8 7 0 Channel x Receive Label Trigger Register 4 5 12 Channel x Interrupt Condition Register Write Bit Description Interrupt Conditions 07 15 0 06 Receiver...

Page 65: ...e Channel x Status Register on page 3 5 In Look Up Mode the Label Received Status bit is set upon receipt of any label for which an interrupt has been requested via the label s Control byte In Sequent...

Page 66: ...x board 5 1 Board Layout 5 1 5 2 LED Indicators 5 2 5 3 Connectors 5 2 5 3 1 Connector J1 Layout 5 2 5 3 2 Connector J1 Pin Assignments 5 3 5 3 3 Connector J1 Communication I O Signals Description 5 4...

Page 67: ...contains two connectors Front panel mounted female DB 62 connector J1 Contains all communication I O signals P N HDL 62SLC PCB Mating connectors P N HDT 62 PD with plastic hoods are included PCI Bus E...

Page 68: ...49 TXL10 8 CASE 29 CASE 50 CASE 9 RXH11 30 RXH13 51 TXH11 10 RXL11 31 RXL13 52 TXL11 11 RXH20 32 RXH22 53 TXH20 12 RXL20 33 RXL22 54 TXL20 13 CASE 34 CASE 55 CASE 14 RXH21 35 RXH23 56 TXH21 15 RXL21 3...

Page 69: ...annels 2 5 Hi connection RXL20 23 Module 2 Receive channels 0 1 3 4 Lo connection RXH20 23 Module 2 Receive channels 0 1 3 4 Hi connection TXL20 21 Module 2 Transmit channels 2 5 Lo connection TXH20 2...

Page 70: ...GND A28 AD 22 AD22 B29 AD 21 AD21 A29 AD 20 AD20 B30 AD 19 AD19 A30 GROUND GND B31 3 3V A31 AD 18 AD18 B32 AD 17 AD17 A32 AD 16 AD16 B33 C BE 2 C_BE2n A33 3 3V B34 GROUND GND A34 FRAME FRAMEn B35 IRDY...

Page 71: ...installed 5V 310 mA Each installed module requires 5V 400mA 12V 90mA see Note 12V 90mA see Note Note Conditions Both transmit channels at full speed and full load Example Full M4 board maximum power...

Page 72: ...ion DAS 429PCI Mx ARINC 429 interface board for PCI systems Supports 4 x Receive and 2 x Transmit channels x Number of modules required 1 4 Each module is configured as R4T2 M429R4T2 Additional module...

Page 73: ...s assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice June 2003 Re...

Page 74: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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