xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
342
For every Sa bit that is selected to carry Data Link information, the Transmit Overhead Input Interface will
supply a clock pulse, via the TxOHClk_n output pin, such that:
•
The Data Link equipment interfaced to the Transmit Overhead Input Interface should update the data on the
TxOH_n line upon detection of the rising edge of TxOHClk_n.
•
The Transmit Overhead Input Interface will sample and latch the data on the TxOH_n line on the falling edge
of TxOHClk_n.
Figure 49 below shows the timing diagram of the input and output signals associated with the E1 Transmit
Overhead Input Interface module in E1 framing format mode.
6.5
E1 Receive Overhead Interface
6.5.1
Description of the E1 Receive Overhead Output Interface Block
6
Transmit Sa7 Data
Link Select
R/W
0 - Source of the Sa7 Nation bit is not from the data link interface.
1 - Source the Sa7 National bit from the data link interface.
5
Transmit Sa6 Data
Link Select
R/W
0 - Source of the Sa6 Nation bit is not from the data link interface.
1 - Source the Sa6 National bit from the data link interface.
4
Transmit Sa5 Data
Link Select
R/W
0 - Source of the Sa5 Nation bit is not from the data link interface.
1 - Source the Sa5 National bit from the data link interface.
3
Transmit Sa4 Data
Link Select
R/W
0 - Source of the Sa4 Nation bit is not from the data link interface.
1 - Source the Sa4 National bit from the data link interface.
F
IGURE
49. E1 T
RANSMIT
O
VERHEAD
I
NPUT
I
NTERFACE
T
IMING
TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (ADDRESS = 0XN10AH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
