EVGA Z270 Classified – K (134-KS-E279)
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PCI-E Slot Breakdown
PCI-E Lane Distribution (All Socket 1151
processors are 16 lanes.)
PE1 – x1 (Gen3, x1 lanes from PCH)
PE2 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE4)
PE3 – x1 (Gen3, x1 lanes from PCH)
PE4 – x16 (Gen3, x8 lanes from CPU, Shares 8 of PE2’s 16 lanes)
PE5 – x1 (Gen3, x1 lanes from PCH)
PE6 – x16 (Gen3, x1 lanes from PCH)
M.2 and U.2 Slot Breakdown
M.2 Lane Distribution
M.2 Key M (110mm, Top) – x4 (Gen 3, 4 lanes from PCH)
o
Using M.2 disables U.2
o
M.2 Enable/Disable is set within the BIOS
M.2 Key M (80mm, Bottom) – x4 (Gen 3, 4 lanes from PCH)
o
Using the PCI-E M.2 DISABLES SATA port 2/3 and PE 3/5
o
Using the SATA M.2 DISABLES SATA port 2/3
o
M.2 Enable/Disable is set within the BIOS
M.2 Key E (32mm) – x1 (Shares with PE3)
o
M.2 Enable/Disable is set within the BIOS
U.2 4x PCI-E Gen 3 lanes (Shares with M.2 Key M 110mm)
o
U.2 Enable/Disable is set within the BIOS
This motherboard does NOT have any lane replication via PLX; all lanes are
native and derived from CPU or PCH. This also allows for improved
backwards compatibility for Gen 2 devices.
