
Schematic Diagrams
ICH9-M 3/5, GPIO, PWR Management B - 15
B.Sch
e
m
a
tic D
iag
rams
ICH9-M 3/5, GPIO, PWR Management
Sheet 14 of 37
ICH9-M 3/5, GPIO,
PWR Management
3. 3 VS
C L _VR EF0
3. 3V
C L _VR EF1
C L_ VR EF1
3 .3 V
CL _VR EF0
3 .3 VS
3. 3VS
AC_ PR ESEN T 2 2
MCH _I C H_ SYN C #
5
SUS _PW R_ AC K 2 2
SC I#
2 2
O D D_ DETEC T#
2 3
3 . 3VS
5 ,8 ,9 ,1 0, 1 1, 12 ,1 3 ,1 5, 17 , 18 ,1 9, 2 0, 21 ,2 2 ,2 3, 24 ,2 5 ,2 9
CL GP IO5
1 3
CL K_ PWR G D 1 7
CL _ RST#1 1 9
P M_ CL KR UN #
1 9 ,2 2
SW I#
2 2
CL _ CL K0 5
SER IR Q
1 9, 22
I CH _S MBC LK 1
19
PM_ SY NC #
5
I C H_ SPKR
2 1
I CH _S MBC LK 0
1 0 ,1 1, 17
I CH _S MBD AT0
1 0 ,1 1, 17
CL K_ IC H1 4 17
SB_ BLO N
1 8
SB_ PWR OK 16
CL _ CL K1 1 9
C LK EN#
29
SLP _S3 # 1 6
3. 3V
2, 1 2, 13 ,1 5 ,1 6, 18 , 19 ,2 3, 2 4, 27 ,2 8
R SMR ST# 1 6, 2 2
SMI#
2 2
CL _ DATA1 19
PM_ D PRSL PVR 5, 2 9
PM_ TH R M#
2
CL _ DATA0 5
P M_ STP CPU #
1 7
CL _ RST#0 5
CL _ PWR OK 5, 16 ,1 8 ,2 2
CL K_ IC H4 8 17
SUS C#
2 2
PWR _ BTN # 22
I CH _S MBD AT1
19
P CI E_W AKE#
1 9 ,2 3
PM_ STP PCI #
1 7
SBSPI _W P#
1 3
SATA_ CL KR EQ#
1 7
C R _C PPEN #
2 0
LPC PD #
1 9
PM_ STPC PU #
PM_STPPC I#
SATA1G P
SB_ PWR O K
SL P_S3
G PIO 17
PC I E_W AKE#
C L_ CL K0
I CH _SMBC LK1
L AN_ PW R
R SMRST#
PM_TH RM#
I CH _ SMBC L K0
G PIO 20
PM_D PR SLPVR
SU S_PW R _AC K
VR M_ PW RGD
PM_ STPPC I #
PM_ CL KRU N #
SATA0 GP
SU S_ PWR _ ACK
G PIO 24
MCH _ IC H_ SY NC #
SU SCL K
SMI #
I CH _ SMBD AT0
C LG PIO 5
G PI O1 3
SATA4 GP
C L_ RST# 1
SB_ BL ON
SB_ BATLOW #
C LK_ IC H 14
C L_ PWR O K
C L_ RST# 0
I CH _SMBC LK0
I CH _SMBD AT1
SL P_M#
G PIO 18
SC I #
G PI O2 4
SB_ L ANR ST#
SATA4G P
PW R_ BTN#
PM_SY SR ST#
C L_ DATA1
SC I#
G PI O1 7
SATA1 GP
PM_ TH RM#
PM_STPC PU#
G PI O9
SW I #
SER IR Q
SL P_S5 #
O DD _ DETEC T#
SATA5 GP
VR M_PW RG D
G PIO 60
S4 _STATE#
C L_ DATA0
C LK_ PW RGD
SMI#
L PCPD #
PW R _BTN#
SATA_ C LKR EQ#
SATA_ CL KR EQ#
I CH _SMBD AT0
C L_ CL K1
SB_ BLO N
VR M_ PW RG D
SBSPI _ WP#
RSMR ST#
PC IE_ W AKE#
SATA5G P
AC _PR ESEN T
O DD _D ETECT#
SW I#
SB_ LAN R ST#
PM_ DPR SL PVR
G PIO 9
SU SC#
G PIO 13
SATA0G P
C LK_ IC H 48
PM_C L KRU N#
I CH _ SMBD AT1
SB_ BATLO W#
I CH _SP KR
I CH _ SMBC L K1
MCH _I C H_ SY NC #
SER I RQ
L AN _PW R
G PI O6 0
PM_ SYSR ST#
AC _ PRESE NT
C R_ CP PEN#
R 30 0
1 00 K_ 04
C 2 09
0 . 03 3U _ 16 V_X7R _ 04
C4 70
0. 1U _1 0 V_X7R _ 04
R 13 2
1 0K_ 0 4
R 28 6
*1 00 K_ 04
R 11 0
1 0K_ 0 4
R 28 5
8 .2 K_ 04
R1 13
45 3_ 1 %_0 6
R 29 8
8 .2 K_ 04
C 19 2
1 00 P_ 50 V_0 4
R 29 7
*1 0K_ 0 4
SA
T
A
SM
B
SYS
G
PIO
GP
I
O
G
PIO
Clo
ck
s
Po
we
r MG
T
Co
nt
roll
e
r
Li
n
k
MISC
U 19 C
I CH 9- M BASE SL B8Q
AH 23
AF1 9
AE2 1
AD 20
G1 6
A1 3
E1 7
C1 7
B1 8
R 4
G1 9
M6
AG1 9
AH2 1
AG2 1
A2 1
C1 2
A1 7
AE1 8
K1
AJ2 2
L 1
A1 4
E1 9
AE1 9
AG2 2
L 4
AF2 1
E2 0
M5
AJ2 3
D2 1
H 1
AF3
P1
C 16
E1 6
G17
G20
M2
B1 3
R 3
D 20
D 22
F1 9
C 10
A9
D1 9
A2 0
R 5
R 6
B1 6
AF8
F2 4
B1 9
F2 2
C 19
C 25
A1 9
F2 1
C 18
C 20
C 11
A1 6
M7
B2 1
D 18
AH2 4
C2 1
A8
AJ2 1
AH2 0
AJ2 4
AJ2 0
SATA0GP/ GPI O 21
SATA1GP/ GPI O 19
SATA4GP/ GPI O 36
SATA5GP/ GPI O 37
SMBC L K
SMBD ATA
LI NK ALER T# / GPI O6 0 /C LG PI O4
SML I NK0
SML I NK1
SUS_ STAT# / LPC PD #
SYS_ R ESET#
PMSY N C# /GPI O0
GPI O 1
GPI O 6
GPI O 7
GPI O 8
GPI O 12
SMBA LER T# / GPI O1 1
GPI O 17
GPI O 18
SCL O CK/ GP IO22
SATA CL KRE Q# /G PI O3 5
STP_ PC I#
STP_ C PU#
SLOAD /G PIO 3 8
SDATAOUT0 /GPIO3 9
CL KR UN #
SDATAOUT1 /GPIO4 8
WAK E#
SERI R Q
TH RM#
VRMPW RGD
C L K14
C L K48
SUSC L K
SL P_ S3#
SL P_ S4#
SL P_ S5#
PWR O K
D PR SLPV R/ GPI O 16
BATL OW#
PWR BTN#
L AN_ R ST#
RSMR ST#
RI #
S4 _STATE#/ GPI O 26
GPI O 27
GPI O 28
TP1 1
C K_PW R GD
CL PWR OK
SL P_ M#
GPI O 20
C L_ C LK0
C L_ C LK1
C L_ DA TA0
C L_ DA TA1
CL _VR EF0
CL _VR EF1
CL _R ST0#
G PIO 1 0/ SUS_ PW R_ AC K
WOL_ EN /G PI O9
GPI O 14 /AC _ PRESE NT
MEM_ LE D/ GPI O 24
SPKR
TP3
CL _R ST1#
GPI O 49
GPI O 13
GPI O 57 /C LGPI O5
TP1 0
TP8
MC H _SY NC #
TP9
R 16 2
1 00 K_ 04
R 10 0
1 0K_ 0 4
R 25 4
*1 0K_ 0 4
R 25 2
4 53 _1 %_ 06
R 13 1
*1 0K_ 0 4
R 12 0
1 00 _0 4
R 11 9
1 0K_ 0 4
R 28 8
*1 0K_ 0 4
R 13 6
8 .2 K_ 04
R 25 9
2 .2 K_ 04
R 11 1
1 M_ 04
R 25 7
1 0K_ 0 4
R 13 3
2 .2 K_ 04
C 20 5
0 .1 U_ 1 0V_ X7 R _0 4
R N1 5
8P 4R X1 0K _0 4
1
2
3
4
5
6
7
8
R 25 3
3 .2 4K _1 %_0 4
R1 08
3. 24 K_ 1%_ 0 4
R 10 6
1 0K_ 0 4
R N2 2
8P 4R X1 0K _0 4
1
2
3
4
5
6
7
8
R 25 8
*1 00 K_ 04
R N1 8
8P 4R X1 0K _0 4
1
2
3
4
5
6
7
8
R 28 2
1 0K_ 0 4
R 17 4
1 00 K_ 04
Q7
2N 70 02 W
G
D
S
R 30 1
1 00 K_ 04
R 25 6
1 00 K_ 04
R 1 12
1 0 K_0 4
Zo= 55O? 5%
CL_VRET0/1=0.405V
12mil s
DDR 2, CLK G EN
1 2mils
Zo= 55O? 5%
NEW CARD, M INI CARD
VCORE PWRGD
All manuals and user guides at all-guides.com