ETOP P/I-P3BVL, User Manual

Page: 24 / 68

Chapter 2 Installations
18 P/I-P3BVL User's Manual
JP10: CMOS RAM Data
This 3-pin Jumper allows the user to disconnect the built-in 3V
battery power to clear the information stored in the CMOS RAM.
To clear the CMOS data: (1) Turn off the system power, (2) Remove
Jumper cap from pin1&2, (3) Short the pin2 and pin3 for three
seconds, (4) Put Jumper cap back to pin1& 2. (5) Turn on your
computer, (6) Hold Down <Delete> during bootup and enter BIOS
setup to enter your preferences.
JP10 Setting Function
Pin 1-2
Short/Closed Normal Operation
(default)
Pin 2-3
Short/Closed Clear CMOS
Content
JP12: WatchDog Timer Mode Selection
The WatchDog Timer is enabled by reading I/O port 443H. The
WatchDog Timer should be triggered before the Watch-Dog Timer
time-out period ends, otherwise the Watch-Dog Timer assumes the
program operation is abnormal and will issue either a reset signal to
re-boot system again, or activate NMI (By pull-low IOCHK#) to the
CPU. The WatchDog Timer is disabled by reading I/O port 043H.
The JP12 jumper is used to select time-out signal. It can be RESET
to re-boot system or NMI to signal CPU.
JP12 Time-out
Mode
1
RESET
1
NMI