Chapter 3 BIOS Configuration
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ISA-E2 User’s Manual
Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing By SPD [Enabled]
X
DRAM
Clock
[HOST
CLK]
X DRAM Cycle Length [3]
Memory
Hole
[Disabled]
P2C/C2P Concurrency
[Enabled]
System BIOS Cacheable
[Enabled]
Video RAM Cacheable
[Enabled]
Frame Buffer Size [16M]
AGP Aperture Size
[16M]
Panel Type [07]
Boot Device Select [Auto]
Power Supply Type
[AT]
OnChip
USB [Enabled]
USB Keyboard Support
[Disabled]
USB Mouse Support
[Disabled]
OnChip Sound [Auto]
Item Help
Menu Level
↑↓←→
Move Enter: /-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the specific features of
the installed chipset. This chipset manages bus speeds and access to system
memory resources, such as DRAM and the external cache. It also coordinates
communications between the conventional ISA bus and the PCI bus. It must be
stated that these items should never need to be altered. The default settings have
been chosen because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if you
discovered that data was being lost while using your system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access
memory (DRAM). The default timings have been carefully chosen and should
only be altered if data is being lost. Such a scenario might well occur if your
system had mixed speed DRAM chips installed so that greater delays may be
required to preserve the integrity of the data held in the slower memory chips.
