ETAS
Technical Data
ETK-T2.2 User Guide
41
7.10
Switching Characteristics
The ETK-T2.2A, the ETK-T2.2B and the ETK-T2.2C have the same timing.
The following diagrams show the timings the ETK-T2.2 can process.
7.10.1
Read Timing: Data Emulation and Measurement Data DPR
Fig.
7
-
1
Read Cyle: Data Emulation and Measurement Data DPR
7.10.2
Write Timing: Data Emulation and Measurement Data DPR
Fig.
7
-
2
Write Cycle: Data Emulation and Measurement Data DPR
Para. Description
Min
Max Unit
t
1
Address access time
15
ns
t
2
Chip select access time
15
ns
t
3
Read access time
10
ns
t
4
Byte enable access time
10
ns
t
5
Data to Chip select hold time
8
ns
t
6
Data to Read hold time
8
ns
t
7
Data to Byte enable hold time
8
ns
t
10
Chip select setup to end of write
18
ns
t
11
Write pulse width
12
ns
t
12
Data setup to end of write
10
ns
t
13
Data hold from end of write
2
ns
NOTE
All timings are measured at a reference level of 1.5 V. Output signals are mea
-
sured with 10
pF to ground and 50
to 1.5
V.
Addr[31:0]
CS
RD
BC[3:0]
ETK_Data[31:0]
Addr
Addr
Data
Data
t1
t2
t3
t4
t5
t6
t7
Addr[31:0]
CS
WR
BC[3:0]
Data[31:0]
Addr
Addr
t12
t13
t10
t11
t11
