ETAS BR XETK-S2.0, User Manual

Page: 15 / 78

ETAS Introduction
BR_XETK-S2.0 - User Guide 15
3.2 Features
• Measurement interface:
– 3.3 V JTAG output levels, 5.0 V tolerant JTAG input
– Configurable JTAG interface clock speed: 20 MHz, 40 MHz, 50 MHz
– Pinless startup protocol for XETK recognition and data acquisition
triggering
• Calibration:
– Microcontroller capability of internal Flash emulation can be used
– BR_XETK
- S2.0 powers Emulation Device RAM (for calibration pur -
pose)
– Supports “Start on Any Page”
• Supports special coldstart mechanism (“Calibration Wake Up”):
– Calibration Wake Up: Wake up mechanism to wake up the power sup -
ply of the ECU via the Calibration Wake up pin
– Pull CalWakeUp until Startup Handshake: duration of the Wake up
mechanism is configurable
• ECU flashing via BR_XETK - S2.0
– Braindead flashing under ProF control
• Permanent storage of configuration in EEPROM
• Automotive Ethernet Interface 100BASE-T1:
– Connection to PC via Automotive to Standard Ethernet Media Con -
verter or via ES88x ECU and Bus Interface Module
– Open XCP on Ethernet Protocol
– Supports a variety of standard applications
• “ETK Drivers and Tools” update to support ETAS software tools (INCA,
XCT)
• Firmware update (programming of the logic device) through HSP soft -
ware service packs; removal of the BR_XETK - S2.0 or ECU is not neces -
sary
• Mounting possibilities inside or on top of ECU
• Temperature range suitable for automotive application
For more technical data on the BR_XETK - S2.0 consult the chapter “Technical
Data” on page 34.
NOTE
The max. allowed JTAG clock depends on the core frequency of the micro-
controller. Max. clock speed is typically 1/4 of the core frequency.