Bootloader
9. Bootloader
9.1 License
The XMC-CPU/T10 module uses the open source bootloader
„Das U-Boot“
. The U-Boot source
code is published in terms of the GNU public license (GPL). Please see esd's „3
rd
party licensor
notice“ document that is part of the product's documentation for the full license text. Please contact
esd for a copy of the full bootloader source code for the XMC-CPU/T10.
The U-Boot source is available from esd on request.
9.2 Configuration and Console Access
Use an USB cable with mini-B connector (XMC-CPU/T10 side) and type A connector (PC side) to
connect the XMC-CPU/T10 to a PCs USB port. The U-Boot console is accessible via the front
panel's USB 'CON' device port (mini-B socket). After the first connection of the XMC-CPU/T10
module you will be prompted for a driver.
Current drivers can be downloaded from:
Most Linux distributions bring their own driver for the used on-board FTDI USB-serial converter.
When driver installation has been done you have a new virtual serial port (COMx on Windows and
typically
/dev/ttyUSBx
on Linux). Now open a terminal program and point to the virtual COM
port of the XMC-CPU/T10.
The default communication parameters are 115 200 baud, 8N1 (8 data bits, no parity, 1 stop-bit, no
hardware handshake).
After the next power-on you will see the bootloader start-up messages being output on the serial
console. When you see the message 'Press SPACE ....', hit the space key to stop booting and to
access the interactive bootloader console. At the prompt you can use an extensive command set to
do configuration, debugging or testing tasks. Enter help (followed by hitting the RETURN key) to
get a full list of all supported commands. See page 39 for a list of special commands.
U-Boot 2016.03.02-rc2-17445-g1f88f26-dirty (Oct 28 2016 - 10:17:47 +0200)
CPU0: T1022, Version: 1.1, (0x85210211)
Core: e5500, Version: 2.1, (0x80241021)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz,
CCB:400 MHz,
DDR:600 MHz (1200 MT/s data rate) (Asynchronous), IFC:66.667 MHz
QE:200 MHz
FMAN1: 400 MHz
QMAN: 200 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 080c000c 0c000000 00000000 00000000
00000010: 06000000 00008002 ec027000 21002000
00000020: 00600000 affebaff 60000000 00033760
00000030: 00000200 c1160a04 00000000 00000006
Board: T1022, Boot from SPI
SERDES Reference Clocks:
SD1_CLK1=100.00MHZ, SD1_CLK2=125.00MHz
I2C: ready
SPI: ready
DRAM: Detected UDIMM esd_CPU-T10_512MB
Found timing match: n_ranks 1, data rate 1666, rank_gb 0
clk_adjust 11, wrlvl_start 14, wrlvl_ctrl_2 0xe0f0f11, 0 of 1 controllers are
interleaving.
512 MiB (DDR3, 64-bit, CL=9, ECC on)
L2: 256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Page 38 of 41
Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2
XMC-CPU/T10