ESD ECS-FPGA Hardware Manual Download Page 24

Connector Assignments

7.2 XMC - P15

Device Connector:

  Samtec ASP-103614-04, header, 114 position, 6 rows, P15

See figure 7 on page 14 for the position of the connector and the pin position. 

PIN

Row A

Row B

Row C

Row D

Row E

Row F

1

PCIe_Tx_L0p

PCIe_Tx_L0n

3.3V

PCIe_Tx_L1p

PCIe_Tx_L1n

n.c.

2

GND

GND

JTAG_TRST#

GND

GND

PCIe_RST_IN#

3

PCIe_Tx_L2p

PCIe_Tx_L2n

3.3V

PCIe_Tx_L3p

PCIe_Tx_L3n

n.c.

4

GND

GND

JTAG_TCK

GND

GND

n.c.

5

n.c.

n.c.

3.3V

n.c.

n.c.

n.c.

6

GND

GND

JTAG_TMS

GND

GND

n.c.

7

n.c.

n.c.

3.3V

n.c.

n.c.

n.c.

8

GND

GND

JTAG_TDI

GND

GND

n.c.

9

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

10

GND

GND

JTAG_TDO

GND

GND

EEPROM_GA0

11

PCIe_Rx_L0p

PCIe_Rx_L0n

FPGA-BIST#

PCIe_Rx_L1p

PCIe_Rx_L1n

n.c.

12

GND

GND

EEPROM_GA1

GND

GND

GND

13

PCIe_Rx_L2p

PCIe_Rx_L2n

n.c.

PCIe_Rx_L3p

PCIe_Rx_L3n

n.c.

14

GND

GND

EEPROM_GA2

GND

GND

EEPROM_SDA

15

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

16

GND

GND

EEPROM_WE

GND

GND

EEPROM_SCL

17

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

18

GND

GND

n.c.

GND

GND

n.c.

19

REFCLK_0p

REFCLK_0n

n.c.

WAKE#

n.c.

n.c.

Page 24 of 27

Hardware Manual • Doc. No.: E.1102.21 / Rev. 1.3

ECS-XMC/FPGA

Summary of Contents for ECS-FPGA

Page 1: ...ace Hardware Manual to Product E 1102 02 ECS XMC FPGA Hardware Manual Doc No E 1102 21 Rev 1 3 Page 1 of 27 esd electronics gmbh Vahrenwalder Str 207 30165 Hannover Germany http www esd eu Phone 49 0...

Page 2: ...ocument in any form whole or in part are subject to esd electronics s written approval 2019 esd electronics gmbh Hannover esd electronics gmbh Vahrenwalder Str 207 30165 Hannover Germany Phone 49 511...

Page 3: ...Conformity note inserted in Safety Instructions 2015 04 13 5 Hardware Installation revised description of conductive O ring added 7 1 Note supplemented 8 New chapter Declaration of Conformity 1 2 New...

Page 4: ...ments indicate a hazardous situation which if not avoided will result in death or serious injury WARNING Warning statements indicate a hazardous situation that if not avoided could result in death or...

Page 5: ...hazardous voltages mains voltage before opening the system Ensure the absence of voltage before starting any electrical work NOTICE Electrostatic discharges may cause damage to electronic components T...

Page 6: ...ective in the long run have to be disposed in an appropriate way or have to be returned to the manufacturer for proper disposal Please make a contribution to environmental protection Typographical Con...

Page 7: ...of the LEDS 15 4 2 LED Indication 15 5 Hardware Installation 17 6 Technical Data 19 6 1 General Technical Data 19 6 2 Hardware Components 19 6 3 FPGA 20 6 4 XMC Interface 20 6 5 Ethernet Interface 20...

Page 8: ...Workbench and full version of the EtherCAT Stack object for Windows and Linux are included in delivery of ECS XMC FPGA 1 2 Steps Following steps have to be performed 1 Install the ECS XMC FPGA into yo...

Page 9: ...k for the driver files select Browse my computer for driver software Select the folder that matches your operating system e g driver ECS win64 when using 64 bit Windows and click Next Figure 2 Update...

Page 10: ...kbench In case of changes to the application the EEPROM content and xml ESI file have to be adapted accordingly 1 5 Testing the Sample App with the Workbench At first the xml ESI file has to be import...

Page 11: ...network For this sample the first two entries belong to the ECS XMC FPGA As described earlier outputs are written and inputs are read here So click one of the two Reread all buttons to have the input...

Page 12: ...eded from the xml ESI others might rely solely on EEPROM ESI The binary ESI can be created by the xml ESI e g with the Workbench The xml ESI is described in the ETG 2000 document You also have to foll...

Page 13: ...ware topology and the use of a soft controller the design offers a maximum of flexibility The XMC system can act as an I O node An EtherCAT master can use several EtherCAT protocols like CoE FoE and E...

Page 14: ...ors 3 PCB View with Connectors Figure 7 PCB top view See also chapter Connector Assignments from page 23 on for the signal assignments of the connectors Page 14 of 27 Hardware Manual Doc No E 1102 21...

Page 15: ...ing LED blinking cycle 200 ms on 200 ms off flickering LED blinking cycle 50 ms on 50 ms off single flash LED blinking cycle 200 ms on 1000 ms off double flash LED blinking cycle 200 ms on 200 ms off...

Page 16: ...ages U1 User LED1 yellow user defined via FPGA and driver LED800A ERR Error LED green off no error LED900C blinking EtherCAT state change failed single flash EtherCAT state change because of configura...

Page 17: ...ER Hazardous Voltage Risk of electric shock due to unintentional contact with uninsulated live parts with high voltages inside of the system into which the ECS XMC FPGA is to be integrated Disconnect...

Page 18: ...ECS XMC FPGA 10 Connect the system to mains again mains connector or safety fuse 11 Switch on the system and the peripheral devices 12 End of hardware installation 13 For the installation of the softw...

Page 19: ...oundary Scan Signal Tap First time initialisation Temperature range Operating temperature 0 65 C ambient temperature Humidity max 90 non condensing Altitude max 2000 m Protection class IP20 in mounted...

Page 20: ...ID Vendor ID constant 0x0703 0x12FE Subsystem Device ID Subsystem Vendor ID 0x0703 0x12FE as endpoint Revision ID 0x0001 Class Code 0x28000 Table 6 Data of the XMC interface 6 5 Ethernet Interface Nu...

Page 21: ...ection against electrostatic discharge or over voltage The lines include a 33 series resistors near to the FPGA Controller Integrated in FPGA Table 9 Data of the SYNC Latch interface 6 8 Spare I O on...

Page 22: ...load the CPU from copying the output process image data into the host memory This is utilized by the esd EtherCAT Slave Stack Please refer to the EtherCAT Slave Stack manual see Order Information page...

Page 23: ...a 4 5 6 RxD Receive Data 7 8 S Shield The pins 4 5 7 and 8 are connected to termination Signal Description TxD RxD data lines of EtherCAT port reserved for future applications do not connect Shield ca...

Page 24: ...5 n c n c 3 3V n c n c n c 6 GND GND JTAG_TMS GND GND n c 7 n c n c 3 3V n c n c n c 8 GND GND JTAG_TDI GND GND n c 9 n c n c n c n c n c n c 10 GND GND JTAG_TDO GND GND EEPROM_GA0 11 PCIe_Rx_L0p PCI...

Page 25: ...19 LVTTL_IO_12 DIFFIO_Rx_R23n L18 n c LVTTL_IN Latch_1 DIFFIO_Rx_R21p K17 LVTTL_IO_13 DIFFIO_Rx_R21n L17 n c 8 GND GND n c GND GND n c 9 LVTTL_OUT Sync_0 DIFFIO_Tx_R20p M22 LVTTL_IO_14 DIFFIO_Tx_R20n...

Page 26: ...Declaration of Conformity 8 Declaration of Conformity Page 26 of 27 Hardware Manual Doc No E 1102 21 Rev 1 3 ECS XMC FPGA...

Page 27: ...Please download the manuals as PDF documents from our esd website www esd eu for free Manuals Order No ECS XMC FPGA ME Hardware manual in English E 1102 21 EtherCAT Slave Stack ME EtherCAT Slave Stac...

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