8.4.
Interrupt-Enable-Register
The interrupt-enable-register is used to enable or disable some or all interrupt
sources. Interrupts are enabled if the corresponding bit is set.
Read and write BaseAd 16
Bit 0
Interrupt if status changes to “Counter 1 running”
Bit 1
Interrupt if status changes to “Counter 1 stopped”
Bit 2
Interrupt if status changes to “Counter 1 fifo not empty"
Bit 3
Interrupt if fifo overflow on counter 1
Bit 4
Interrupt if incremental step error on counter 1
Bit 12
Interrupt if status changes to “Counter 2 running”
Bit 13
Interrupt if status changes to “Counter 2 stopped”
Bit 14
Interrupt if status changes to “Counter 2 fifo not empty"
Bit 15
Interruptif fifo overflow on counter 2
Bit 16
Interrupt if incremental step error on counter 2
Bit 22
Interrupt on changes at digital input 0
Bit 23
Interrupt on changes at digital input 1
Bit 24
Interrupt on changes at digital input 2
Bit 25
Interrupt on changes at digital input 3
Bit 26
Interrupt if status changes to “Reference counter running”
Bit 27
Interrupt if status changes to “Reference counter stopped”
Bit 28
Interrupt if incremental step error on reference counter
Bit 31
Global interrupt enable
0 All interrupts disabled
1 Interrupts enabled
8. The registers of the PCI 1389-S02
ERMA-Electronic GmbH
16
Summary of Contents for PCI 1389-S02
Page 10: ...7 1 1 Component layout 7 Installation 9 ERMA Electronic GmbH ...
Page 27: ......