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SR3225SAA

 

 

 

Page - 16 

ETM54E-07 

 

 

SPI checksum 

6.2.3.

SPI checksum is available (

Figure 6.8

). 

The XOR arithmetic calculation of c address 8 bits and data 8 bits is operated during SFR write access. 
The checksum result is stored in 0x16 SFR address. The checksum is reset by transiting to Powerdown mode or 
writing any data to checksum register (address 0x16). 

 

 

 

 

Figure 6.8 SPI Checksum Process Block Diagram 

 

Table 6.3

 shows SPI checksum example. If you write 0x02 in address 0x04 and 0x01 in address 0x05, the value 

0x02 is stored in checksum register. 
 

Table 6.3 SPI Checksum Calculation Example 

 

Transmission byte by SPI 

Checksum result 

0100 0100 (Write + Address) 

0100 0100 

0000 0010 (Data) 

0100 0110 

0100 0101 (Write + Address) 

0000 0011 

0000 0001 (Data) 

0000 0010 

 
 

 

SPI shift register

XOR

Checksum SFR

Address:0x16

Read Access
/ Write Clear

8

8

8

Summary of Contents for SR3225SAA

Page 1: ...ETM54E 07 RF Transmitter Module SR3225SAA Application Manual ...

Page 2: ...nformation furnished herewith for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested not to make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment For specific applications that require extremely high accuracy precisio...

Page 3: ...for the frequency setting value 23 6 4 1 6 5 FSK Modulator 25 FSK deviation setting 25 6 5 1 Soft FSK 26 6 5 2 6 6 Output Power Setting 26 ASK modulation 26 6 6 1 Soft ASK 28 6 6 2 Antenna tuning 28 6 6 3 6 7 Fail safe Function 29 PLL Loss of Lock detection 29 6 7 1 VCO auto calibration error detection 29 6 7 2 Under voltage detection 29 6 7 3 6 8 Clock Output CKOUT Function 31 Frequency divider 3...

Page 4: ...lation Control 0 38 7 11 ASK Modulation Control 1 38 7 12 ASK Modulation Control 2 39 7 13 Soft ASK Modulation Setting 39 7 14 Soft FSK Modulation Setting 40 7 15 CKOUT Bitrate Signal Divider Setting 1 40 7 16 CKOUT Bitrate Signal Divider Setting 2 41 7 17 Under Voltage Detection Antenna Tuning Setting 42 7 18 Error Detection Status 43 7 19 Transmitter Control 44 7 20 SPI Checksum 45 8 Dimensions ...

Page 5: ...onal N PLL Programmable power amplifier PA output power 15 dBm to 1dBm 5 dBm to 11 dBm for each 64 steps Modulation types ASK OOK FSK with Soft ASK and or Soft FSK shaping Multi channel up to 4 channels channel hopping capability 3 wire 4 wire SPI interface for Special Function Register SFR SFR Special Function Register Fail safe mechanism PLL Loss of Lock LOL VCO auto calibration error Under Volt...

Page 6: ...SR3225SAA Page 2 ETM54E 07 2 Part Number SR3225SAA A Model name Crystal resonator frequency A 32 MHz ...

Page 7: ...SR3225SAA Page 3 ETM54E 07 3 Block Diagram Figure 3 1 Block Diagram ...

Page 8: ...face pin Leave floating and make no external connections to this pin if the function of this pin is unused 2 EN Input Pull down Enable input SPI interface pin 3 SCK Input Pull down SPI clock input 4 SDIO Input Output Pull down SPI data input output 5 CKOUT Output Clock output 6 VSSPA Power GND for PA 7 PAOUT Output Power Amp output 8 RFC Output RF choke coil 9 VDD Power Positive power supply 10 VS...

Page 9: ...trical Characteristics 5 1 Absolute Maximum Rating Item Symbol Condition Standard Unit Min Typ Max Supply voltage VDD VSS 0 V 0 3 4 0 V Input voltage Vin VSS 0 V VSS 0 3 VDD 0 3 V Storage temperature Tstg Store as bare product 40 125 C ...

Page 10: ...DUTY 10b Pout 5 dBm AM 0x1A 1 10 0 11 0 mA Pout 8 dBm AM 0x29 1 12 7 13 7 Pout 10 dBm AM 0x36 15 0 16 0 FTX 433MHz HPWR 1 PADUTY 10b Pout 5 dBm AM 0x16 1 10 11 mA Pout 8 dBm AM 0x24 1 12 5 13 5 Pout 10 dBm AM 0x30 1 14 5 15 5 FTX 868 MHz HPWR 1 PADUTY 01b Pout 5 dBm AM 0x19 1 11 7 12 7 mA Pout 8 dBm AM 0x28 1 14 4 15 4 Pout 10 dBm AM 0x35 1 16 5 17 5 FTX 915 MHz HPWR 1 PADUTY 01b Pout 5 dBm AM 0x1...

Page 11: ... 1 V VOL２ CKOUT If the SR 11b is set Io 1 mA If the SR 10b is set Io 0 7 mA If the SR 01b is set Io 0 5 mA If the SR 00b is set Io 0 2 mA VDD x 0 1 V Pull down resistor 1 RDOWN EN SCK SDIO TEST1 250 kΩ Input capacitance 1 CIN EN SCK SDIO TEST1 5 pF 1 Guaranteed by design characterization and or simulation only and not by production test Table 5 3 Under Voltage Detector Characteristics VSS 0 V Ta 4...

Page 12: ... 2 ppm Internal crystal frequency temperature characteristics 1 FTC 40 C to 85 C 20 20 ppm Internal crystal oscillator start up time tXTAL See Figure 6 15 500 μs CKOUT output frequency FCKOUT See Figure 6 20 0 00049 32 MHz CKOUT rise fall time 1 tr tf Load capacitance15 pF 20 to 80 VDD SR 11b 5 ns SR 10b 7 ns SR 01b 10 ns SR 00b 20 ns CKOUT symmetry 1 SYM SR 11b load capacitance 15 pF FCKOUT 32MHz...

Page 13: ...Hz HPWR 1 PADUTY 01b AM 0x3F 9 5 11 12 5 dBm AM 0x01 7 0 5 5 4 0 Ta 25 C VDD 3 0 V FTX 315 MHz HPWR 0 PADUTY 10b AM 0x3F 1 0 2 0 3 0 dBm AM 0x01 16 0 15 0 14 0 Output power temperature dependence 1 2 PTMP Ta 40 C to 85 C VDD 3 0 V 1 1 dB Output power supply voltage dependence 1 2 PVDD Ta 25 C VDD 1 8 V to 3 6 V VDD 3 0V AM 0x20 4 1 dB AM 0x20 1 1 dB Harmonics level 1 2 PdBc Ta 25 C VDD 3 0 V AM 0x...

Page 14: ...pF 7 pF 82 pF 10 pF 100 nH 39 nH 433 MHz 0 1 μF 560 pF 7 pF 22 pF 10 pF 82 nH 27 nH 868 MHz 0 1 μF 100 pF 3 pF 33 pF 5pF 22 nH 10 nH 915 MHz 0 1 uF 100 pF 3 pF 22 pF 5pF 22 nH 10 nH Figure 5 1 PAOUT AC Test Circuit Inductor TDK MLG1005S series Capacitor TDK C1005C0G1 series ...

Page 15: ...ns SCK H pulse width tWH 150 ns SCK L pulse width tWL 150 ns SCK rise and fall time tRF 20 ns SCK setup time tSCKS 100 ns EN setup time tES 150 ns EN hold time tEH 100 ns EN recovery time tER 100 ns EN rise and fall time tENRF 30 ns Write data setup time tDS 20 ns Write data hold time tDH 20 ns Read data delay time tRD CL 50 pF 0 100 ns SDIO output disable time tRZ CL 50 pF 0 100 ns ...

Page 16: ...ignals using transmit commands EN The EN pin is used to input SPI enable signal control SPI communications and input the timing to latch transmission data When the EN pin rises the mode of SR3225SAA is transited from Powerdown mode to ATOSC Active mode and 2 MHz 32 MHz divided by 16 is outputted from the CKOUT pin after tXTAL Max 500 μs When the EN pin falls the SPI interface is initialized If the...

Page 17: ...ure 6 1 When connecting SR3225SAA with MCU in 4 wire SPI mode you can write data without setting IFSEL 1 0 To read data set IFSEL 1 0 Table 6 1 Interface Mode Setting IFSEL 1 0 SPI mode Transmission data input pin 00b 3 wire SPI mode default SDIO 01b 4 wire SPI mode SDIO 10b 3 wire SPI mode TEST1 11b Invalid 3 wire SPI mode 4 wire SPI mode Figure 6 1 HOST Interface Example ...

Page 18: ... 2 depicts the timing for writing access in 3 wire and 4 wire SPI modes Figure 6 3 shows the timing for read access in 3 wire SPI mode and Figure 6 4 shows the timing for read access in 4 wire SPI mode Figure 6 2 Write Access to SFR Figure 6 3 3 wire SPI Read Access to SFR Figure 6 4 4 wire SPI Read Access to SFR ...

Page 19: ...t command SR3225SAA supports burst write and read Figure 6 5 depicts the timing for burst write access in 3 wire and 4 wire SPI modes Figure 6 6 shows the timing for burst read access in 3 wire SPI mode and Figure 6 7 shows the timing for burst read access in 4 wire SPI mode While burst writing reading the SFR address is incremented automatically from any address sent by the command address bit It...

Page 20: ...ny data to checksum register address 0x16 Figure 6 8 SPI Checksum Process Block Diagram Table 6 3 shows SPI checksum example If you write 0x02 in address 0x04 and 0x01 in address 0x05 the value 0x02 is stored in checksum register Table 6 3 SPI Checksum Calculation Example Transmission byte by SPI Checksum result 0100 0100 Write Address 0100 0100 0000 0010 Data 0100 0110 0100 0101 Write Address 000...

Page 21: ...ester code Bit A must be set to 1 D ASK Modulation Control Setting Selection 0 ASKMC0 1 ASKMC1 E F Frequency Channel selection 00 Frequency channel 1 01 Frequency channel 2 10 Frequency channel 3 11 Frequency channel 4 After sending transmit command wait for PLL settling time tFSTE rise SCK PA is activated and RF data transmission starts If you rise SCK before PLL is settled tFSTE an unexpected fr...

Page 22: ...iding the frequency for the internal crystal oscillator thus the bitrate signal has same accuracy as the internal crystal oscillator Users can output divide clock synchronized with the bitrate signal from CKOUT pin If divided clock are supplied to MCU as system clock please note that clock pulse width may be changed by divider initialization with PA start up There may be 1 prescaler clock delay in...

Page 23: ...ssion example in the following settings Synchronous transmission bit A 1 PA is OFF bit B 0 when EN falls transmission sign is Manchester code bit C 1 CKSRC 2 0 010b ASC 2 0 1 See section 6 8 for CKOUT settings and details Figure 6 11 Synchronous Transmission Example ...

Page 24: ...ronous transmission mode and the asynchronous transmission mode See Figure 6 12 for transmission signal input timing details through the SDIO pin and Figure 6 13 for transmission signal input timing details through the TEST1 pin Figure 6 12 Transmission Signal Input Timing Details through SDIO Pin Figure 6 13 Transmission Signal Input Timing Details through TEST1 Pin ...

Page 25: ...Active mode 2 MHz 32 MHz divided by 16 is outputted from CKOUT Users can set other dividing frequency and stop CKOUT with SFR settings See section 6 8 for more details of CKOUT SFR can be accessed through SPI interface even if the crystal oscillator is in its start up time SR3225SAA enters ATOSC Active mode when it turns on Therefore even if the EN pin is set low before SR3225SAA is turned on CKOU...

Page 26: ...transition to PLL Standby mode becomes available Since PLL_EN is set to 1 in the SFR_Init process in Figure 6 15 the mode is changed to PLL Standby mode immediately after tXTAL Max 500 μs has elapsed It is recommended to perform the process for quick start if there is no need to stay in ATOSC Active mode The mode is changed to Transmitter Active mode when a transmit command is sent and the PA is a...

Page 27: ...FVCO must be 600 MHz to 930 MHz The output divider ODIV is determined by this rule and FTX in formula 1 See Table 6 5 for details Powerdown ATOSC Active PLL Transmitter PLL Powerdown Standby Active Standby PLL_EN Internal signal PA_EN Internal signal RF_OUT VDD EN SCK SDIO Command control VREG Voltage Regulator ATOSC Internal signal CKOUT SFR_Init Write PLL_EN 1 Transmit command Crystal oscillator...

Page 28: ... For example if reference frequency FREF is 32 MHz and output frequency should be 315 MHz ODIV is calculated to be 2 by Table 6 5 Then the division settings of feedback divider N NINT and NFRAC are calculated by formulas 4 to 6 based on formula 2 𝑁 𝑁𝐼𝑁𝑇 4 𝑁𝐹𝑅𝐴𝐶 3 218 𝐹𝑂𝑈𝑇 𝑂𝐷𝐼𝑉 𝐹𝑅𝐸𝐹 315 106 2 32 106 19 6875 4 𝑁𝐼𝑁𝑇 𝑓𝑙𝑜𝑜𝑟 𝑁 𝑓𝑙𝑜𝑜𝑟 19 6875 19 5 𝑁𝐹𝑅𝐴𝐶 𝑁 𝑁𝑖𝑛𝑡 218 3 4 19 6875 19 218 3 4 45055 0𝑥𝐴𝐹𝐹𝐹 6 Tab...

Page 29: ...ddress 0x0B FSK modulation FDEV is calculated by formula 7 FREF is the reference frequency of crystal oscillator FDEV FDEV4X and FDEV2X are SFR setting values 𝐹𝐷𝐸𝑉 𝐹𝑅𝐸𝐹 𝐹𝐷𝐸𝑉 216 4𝐹𝐷𝐸𝑉4𝑋 2𝐹𝐷𝐸𝑉2𝑋 7 For example if you set FDEV to 31 FDEV4X to 0 and FDEV2X to 0 FSK deviation FDEV is calculated by formula 8 𝐹𝐷𝐸𝑉 𝐹𝑅𝐸𝐹 𝐹𝐷𝐸𝑉 216 4𝐹𝐷𝐸𝑉4𝑋 2𝐹𝐷𝐸𝑉2𝑋 32 106 31 216 40 20 15 136 𝑘𝐻𝑧 8 Carrier frequency is modulat...

Page 30: ...gs for PA output power and ASK modulation in SFR address 0x0C to 0x0E See chapter 7 for details of SFR addresses This section provides the details of each bit ASKMC0 ASKMC1 selection 8 bits are assigned to SFR address 0x0C ASKMC0 and 0x0D ASKMC1 The ASKMC means ASK Modulation Control The 8 bits consist of ASK FSK modulation setting output power range setting and output power minor adjustment You c...

Page 31: ...mode PADUTY 1 0 The function of changing duty cycle is implemented to improve the PA efficiency See Table 6 9 for setting values and nominal duty cycle You may improve PA efficiency by making the shape duty small and the on time in output transistor small However since harmonics spurious is also changed check output power current consumption and harmonics spurious before use if you change recommen...

Page 32: ...is assigned to SFR address 0x0F 𝑡𝐴𝑀𝑅𝐶 AMH AML 𝐴𝑀𝑅𝐶 1 𝐹𝑅𝐸𝐹 10 The AMRC setting also works for FSK modulation The load for power supply is reduced by applying ramp shape to start up PA current consumption Antenna tuning 6 6 3 The PA has a variable capacitor array for antenna tuning It is connected between the PAOUT pin and the VSS pin Its capacitance is controlled by ATT 4 0 in SFR address 0x13 See ...

Page 33: ...gnals and feedback signals are the same If the frequency difference between reference signals and feedback signals exceeds threshold the detector judges it as an error Error detection results are stored in the PLLDER in SFR address 0x14 VCO auto calibration error detection 6 7 2 After sending transmit command VCO in the PLL is automatically calibrated during tFSTE 100 μs If the result of this cali...

Page 34: ...SR3225SAA Page 30 ETM54E 07 Figure 6 18 Reset of Under Voltage Detection Results by SFR Write Clear Figure 6 19 Reset of Under Voltage Detection Results by Transition to Powerdown Mode ...

Page 35: ...z Fref 16 is outputted from the CKOUT pin right after the mode is changed from Powerdown mode to ATOSC Active mode The Bitrate Signal shown in Figure 6 20 is a signal for latch of SDIO pin data in synchronous communication mode It is same as the Bitrate Signal shown in Figure 6 10 and Figure 6 11 Figure 6 20 Frequency Divider Structure for CKOUT Bitrate Signal Table 6 11 CKSRC 2 0 Setting CKSRC 2 ...

Page 36: ... 1 1 2 2 1 4 3 1 8 4 1 16 5 1 32 6 1 64 7 1 128 The settings for Comparator shown in Figure 6 20 is made in BRS 7 0 in SFR address 0x11 See Table 6 13 Table 6 13 BSC 7 0 Setting BRS 7 0 Division ratio 0 1 1 1 1 2 2 1 3 3 1 4 4 1 5 255 1 256 The settings for Afterscaler shown in Figure 6 20 is made in ASC 2 0 in SFR address 0x12 See Table 6 14 for details Table 6 14 ASC 2 0 Setting ASC 2 0 Division...

Page 37: ...ies Table 6 15 Recommended SR 1 0 Setting CKOUT frequency MHz PSC 2 0 Division ratio SR 1 0 recommended setting 32 0 1 1 11b 16 1 1 2 10b 8 2 1 4 01b 4 3 1 8 00b 2 4 1 16 00b CKOUT pin load capacitance 15 pF 6 9 Status Monitor Transition counter 6 9 1 The TXCOUNT 3 0 in SFR address 0x14 stores the number of transition to Transmitter Active mode Users can check the number by reading SFR The value i...

Page 38: ...WR0 AMH0 5 0 xxxx xxxx b ASKMC1 ASK Modulation Control 1 0x0D ASK1 HPWR1 AMH1 5 0 xxxx xxxx b ASKMC2 ASK Modulation Control 2 0x0E PADUTY 1 0 AML 5 0 xxxx xxxx b PARAMP ASK Modulation Ramp Control 0x0F AMRC 7 0 xxxx xxxx b FSKRAMP FSK Modulation Ramp Control 0x10 FMRC 7 0 xxxx xxxx b BRS1 Bitrate Setting 1 0x11 BRS 7 0 xxxx xxxx b BRS2 Bitrate Setting 2 0x12 CKSRC 2 0 PSC 2 0 ASC 1 0 000x xxxx b A...

Page 39: ...2FRAC0 F2FRAC 7 0 Type R W Default 0 0 0 0 0 0 0 0 Bit Name Function 7 0 F2FRAC 15 8 F2FRAC 7 0 Fractional portion of the feedback divider NFRAC of frequency channel 2 e g If NFRAC is 0x5678 F2FRAC 15 8 0x56 F2FRAC 7 0 0x78 7 4 PLL Integer Setting Frequency Channel 1 and 2 Address Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x04 F1_2INT F1INT 3 0 F2INT 3 0 Type R W Default 0 0 0 0 0 ...

Page 40: ...4FRAC0 F4FRAC 7 0 Type R W Default 0 0 0 0 0 0 0 0 Bit Name Function 7 0 F4FRAC 15 8 F4FRAC 7 0 Fractional portion of the feedback divider NFRAC of frequency channel 4 e g If NFRAC is 0xDEF0 F4FRAC 15 8 0xDE F4FRAC 7 0 0xF0 7 7 PLL Integer Setting Frequency Channel 3 and 4 Address Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x09 F3_4INT F3INT 3 0 F4INT 3 0 Type R W Default 0 0 0 0 0 ...

Page 41: ...s max 2 Tr Tf 7 ns max 3 Tr Tf 5 ns max 3 F1ODIV Settings for output divider of frequency channel 1 FnODIV settings and output divider ratio ODIV 0 1 1 1 1 2 2 F2ODIV Settings for output divider of frequency channel 2 1 F3ODIV Settings for output divider of frequency channel 3 0 F4ODIV Settings for output divider of frequency channel 4 7 9 FSK Deviation Setting Address Register name Bit Bit7 Bit6 ...

Page 42: ... Max See Table 5 5 ASKMC0 ASKMC0 is selected when the bit D of transmit command is 0 See section 6 2 4 for details 7 11 ASK Modulation Control 1 Address Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x0D ASKMC1 ASK1 HPWR1 AMH1 5 0 Type R W Default 0 0 0 0 0 0 0 0 Bit Name Function 7 ASK1 Modulation type 0 FSK 1 ASK 6 HPWR1 PA output power range 0 15 dBm to 0 dBm 1 4 dBm to 11 dBm 5 0 A...

Page 43: ...10b 36 Not available 11b 30 Not available 5 0 AML 5 0 PA output power setting In ASK this setting is applied for High level transition data In FSK this setting is not used 1 Min 63 Max See Table 5 5 0 The PAOUT pin goes OFF which means OOK mode 7 13 Soft ASK Modulation Setting Address Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x0F PARAMP AMRC 7 0 Type R W Default 0 0 0 0 0 0 0 0 Bi...

Page 44: ...7 0 Soft FSK Modulation setting You can set FMRC calculated as follows See section 6 5 2 for details 𝑡𝐹𝑀𝑅𝐶 O𝐷𝐼𝑉 2 𝐹𝐷𝐸𝑉 𝐹𝑀𝑅𝐶 1 𝐹𝑅𝐸𝐹 7 15 CKOUT Bitrate Signal Divider Setting 1 Address Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x11 BRS1 BRS 7 0 Type R W Default 0 0 0 0 0 0 0 0 Bit Name Function 7 0 BRS 7 0 Compare settings for CKOUT bitrate signal divider 0 1 1 1 1 2 2 1 3 3 1 4 4 1 ...

Page 45: ...b PAON 0 Low PAON 1 Divided clock 011b PAON 0 High PAON 1 Inverted divided clock 100b PAON 0 High Z PAON 1 Fref 16 101b PAON 0 High Z PAON 1 Prescaler clock 110b PAON 0 High Z PAON 1 Divided clock 111b PAON 0 High Z PAON 1 Inverted divided clock Note PAON 0 PA is disabled PAON 1 PA is enabled 4 2 PSC 2 0 Prescaler setting for CKOUT bitrate signal divider 0 1 1 1 1 2 2 1 4 3 1 8 4 1 16 5 1 32 6 1 6...

Page 46: ... ATUNE VDET 1 0 ATT 4 0 Type R W Default 0 0 0 0 0 0 0 0 Bit Name Function 6 5 VDET 1 0 Under voltage detection release setting Detection threshold Release threshold 0 1 8 V 2 0 V 1 2 0 V 2 2 V 2 2 2 V 2 4 V 3 2 4 V 2 6 V 4 0 ATT 4 0 Antenna tuning capacitance array setting About 40fF divide capacitance available 0 184 fF 1 223 fF 2 262 fF 31 1393 fF ...

Page 47: ...he number of transitions to Transmitter Active mode The value is reset to zero when the counter overflows 3 OSCDET Crystal oscillation amplitude check result 0 Not enough amplitude 1 Enough amplitude 2 VDETER Under voltage detection flag 0 No under voltage 1 Under voltage detected 1 VCOCER VCO auto calibration error flag 0 No VCO auto calibration error 1 VCO auto calibration error detected 0 PLLDE...

Page 48: ...OUT output disable setting 0 Enable output 1 CKOUT pin is Hi Z 5 FSOFF Fail safe function disable If the fail safe function is disabled PA does not stop even if an error is detected 0 Enable fail safe function 1 Disable fail safe function 4 3 IFSEL 1 0 Interface mode setting IFSEL 1 0 SPI mode Transmission data input pin 00b 3 wire SPI mode default SDIO 01b 4 wire SPI mode SDIO 10b 3 wire SPI mode...

Page 49: ...ddress Register name Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x16 SPICKSUM SPICKSUM 7 0 Type R C Default 0 0 0 0 0 0 0 0 Bit Name Function 7 0 SPICKSUM SPI checksum calculation result The XOR result of SPI transmission address and data is stored ...

Page 50: ...SR3225SAA Page 46 ETM54E 07 8 Dimensions Unit mm ...

Page 51: ...SR3225SAA Page 47 ETM54E 07 9 Marking This figure shows letters and their rough positions but does not show their fonts and sizes ...

Page 52: ...SR3225SAA Page 48 ETM54E 07 10 Soldering Pattern Unit mm ...

Page 53: ...ease carefully verify whether the device is properly secured to prevent falling 5 Ultrasonic cleaning may damage the oscillator under some conditions Please exercise adequate caution before use 6 Protection against periodic mechanical vibration If this device is subject to periodic mechanical vibrations and or shock such as cooling fans piezoelectric sounders piezoelectric buzzers and speakers out...

Page 54: ...hat exceeds the conditions for reliability test AM 0x28 Pout approximately 8 dBm please perform a check 11 VDD and VSS pattern shall be as large as possible so that high frequency impedance shall be small In addition it is recommended to install an approximately 0 1 μF decoupling capacitor near the product 12 Do not power on the device from neutral potential and rise supply voltage extremely fast ...

Page 55: ...of insulation resistance Leads on the opposite side are not electrically connected to the IC and crystal Side leads on the 1 pin side shown below are connected to IC and crystal internally Therefore be careful for short or a fall of insulation resistance Leads on the opposite side are connected to VSS pin Please take necessary precautions to prevent short circuit to VSS by contacting the opposite ...

Page 56: ...TM54E 07 Model name SR3225SAA Specification control No ETM54E Revision History Revision Date of Revision Change Description of changes p XX Old New Reason 07 Feb 16 2017 22 State diagram State diagram correction of errors ...

Page 57: ...h 7F Block B High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch 12F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen 518057 China Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Shenzhen Branch Fax 86 755 2699 3838 ...

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