Technical Description
18
Seiko Epson Corporation
S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
6 Technical Description
6.1 PCI Bus Support
The S1D13A05
does not
have on-chip PCI bus interface support. The S1D13A05B00C
uses the on-board PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13A05B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13A05 directly supports many other host
bus interfaces. Connectors H4 and H5 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 13.
Note
If a direct host bus interface is used, the PCI Bridge FPGA must be disabled using SW1-
8.
6.3 S1D13A05 Embedded Memory
The S1D13A05 has 256K bytes of embedded SRAM. The 256K byte display buffer address
space is directly and contiguously available through the 18-bit address bus.
6.4 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide
between -14V and -24V (I
out
=45mA). Such a power supply (VLCD) has been provided on
the S5U13A05B00C board. VLCD can be adjusted using potentiometer R21 to provide an
output voltage from -14V to -24V, and is enabled/disabled using the S1D13A05 general
purpose signal, GPO0 (active high).
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements
before connecting the panel.
