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S2R72A21 Application Note

Seiko Epson Corporation

3

(Rev.1.00)

1. Description

This document is the application note of the USB2.0 Re-Synchronization IC: S2R72A21.

This document explains the USB connection description, system implementation, compliance test for products
which equip S2R72A21 as well as the remark point during PCB designing using this Re-Synchronization IC.
Please refer to the S2R72A21 data sheet for Hardware related information.

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Summary of Contents for S2R72A21

Page 1: ...Rev 1 00 S2R72A21 Application Note ...

Page 2: ...plication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party When exporting the products or technology described in this material you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You...

Page 3: ... Role Switch control 15 5 1 4 Method to detect disconnection of Portable Device 15 5 2 Connection ex Host SoC on the separate board INT port Portable Device EXT port 17 5 2 1 ADJ settings 17 5 2 2 BC control 17 5 2 3 Role Switch control 17 5 2 4 Method to detect disconnection of Portable Device 17 5 3 Connection ex Host SoC on the separate board EXT port Portable Device INT port 19 5 3 1 ADJ setti...

Page 4: ...1 Application Note Rev 1 00 7 PCB design guide 27 7 1 Power supply and reset 27 7 2 DP DM signal line 27 7 2 1 Circuit board wiring 27 7 2 2 Additional component 27 7 3 Oscillator circuit 29 7 4 Others precautions 29 Revision History 31 ...

Page 5: ...e USB2 0 Re Synchronization IC S2R72A21 This document explains the USB connection description system implementation compliance test for products which equip S2R72A21 as well as the remark point during PCB designing using this Re Synchronization IC Please refer to the S2R72A21 data sheet for Hardware related information ...

Page 6: ...en it is pulled out Device Device which is defined within the USB specification Disconnect Condition where the USB connection via the S2R72A21 is shut down electrically EOP End of Packet EXT port External port of S2R72A21 FS Full Speed FS_J Bus state J during FS Differential 1 FS_K Bus state K during FS Differential 0 Host Host which is defined within the USB specification The host issues the SOF ...

Page 7: ...ure here shows an example where S2R72A21 is mounted on the Car Navigation or Display Audio s board Host SoC board S2R72A21 intervenes between the Host SoC s USB port and the USB type A receptacle and connects the Host SoC as Host and Portable device such as smart phones as Device The following is the pin connection example of S2R72A21 with this structure Figure 3 2 1 Basic system structure of S2R7...

Page 8: ...ice and set 0 when the Device is disconnected EN_DETACH Please set and stable it either to 0 or 1 on the boards In this chapter the case EN_DETACH 0 is explained as the basic setting FRC_THR Please set and stable it to 0 on the boards SEL_I2C Please set and stable it either to 0 or 1 on the boards In this chapter the case SEL_I2C 1 I2C is in use is explained as the basic setting ADJ 4 0 Please set...

Page 9: ...State INT_DP DM EXT_DP DM INITIAL DISCON NECT Bus Switch INT EXT HS Synchronizer FS_LS HS Attach RESET 10ms USB signal path Hi Z Reset Reset released Operation start FS operation Chirp operation HS opearation 1 Detect ENABLE 1 BC J J K K K K J J K K J J K K J J K K J J FS D_Chirp H_Chirp 5us SOF Bus Switch OFF 10ms passed Detect SE0 for 3ms HVDD XRESET ENABLE State INT_DP DM EXT_DP DM DISCONNECT B...

Page 10: ...ion if you attach the Portable Device BC capable to the EXT port as Device a negotiation would start between Portable Device and BC Regulator based on the BC protocol below 0 6V signal level 3 3 2 4 FS operation When the BC negotiation finishes the Portable Device would indicate the FS_J to the EXT port and notify the IDLE condition During this time the Bus Switch path of the USB signal would conn...

Page 11: ...he transition to FS_LS state would occur to prepare for any Suspend detection During this time the USB signal path would switch from HS Synchronizer to Bus Switch and the INT and EXT port would be connected Please do not make the Host SoC and Portable Device transmit any HS signal after 2 95ms from the last HS signal delivery After the USB signal path switches to Bus Switch it would detect the EXT...

Page 12: ... to the EXT port is omitted from the USB signal path so the Host SoC can detect the Portable Device detach with less influence of the returning wave When 3ms has passed the S2R72A21 would transit to FS_LS state Figure 3 3 2 10 1 shows the disconnection operation waveform in case EN_DETACH 1 Figure 3 3 2 10 1 Disconnection operation waveform in case EN_DETACH 1 3 3 2 11 Operation end The Host SoC c...

Page 13: ...ye pattern Figure 3 4 1 A USB system example and schematic diagrams of HS signal amplitude HS packets transmitted from the Host are re synchronized by S2R72A21 and reach the Device through the USB Cable P1 is the signal measuring point at the S2R72A21 pin and P2 is the signal measuring point at the Device The HS signal transmitted from the S2R72A21 is attenuated by the USB cable etc thus the signa...

Page 14: ...nd pulling down the DP and DM of the Portable Device side ex 1MΩ 4 1 Connection ex Host SoC on the same board INT port Portable Device EXT port Figure 4 1 1 Connection ex Host SoC on the same board INT port Portable Device EXT port The same as the basic system structure shown on Figure 3 2 1 Host SoC board S2R72A21 XRESET HVDD ENABLE EN_DETACH FRC_THR TESTEN ADJ2 ADJ1 ADJ0 SEL_I2C INT_DP INT_DM AD...

Page 15: ...t SoC board S2R72A21 board S2R72A21 XRESET HVDD ENABLE EN_DETACH FRC_THR TESTEN ADJ4 ADJ3 ADJ2 ADJ1 ADJ0 SEL_I2C INT_DP INT_DM EXT_DP EXT_DM EP VSS FVDD LVDDC LVDDM R1 XI XO STAT1 STAT0 HS transmission current control BC Regulator Host SoC DP DM VBUS Portable Device DP DM VBUS HVDD Regulator VBUS HVDD POR Host SoC board S2R72A21 board S2R72A21 XRESET HVDD ENABLE EN_DETACH FRC_THR TESTEN ADJ4 ADJ3 ...

Page 16: ...d play as a Host and issue the Bus reset and resume the HS communication again via FS to HS connection As mentioned on the S2R72A21 Data sheet section 6 1 1 S2R72A21 would transit from HS state to FS_LS state automatically when over 3ms of SE0 is detected and the Bus Switch connection between INT EXT would be valid In other words within the above Role switch operation sequence S2R72A21 would detec...

Page 17: ... In this case the Portable Device and the Host SoC would change its role nevertheless it s naming However for the convenience within this documents would keep calling the name as Portable Device and Host SoC If the Bus becomes Floating during the Role Switch period we recommend to pull down the Bus by 1MΩ and etc 5 1 4 Method to detect disconnection of Portable Device When the Portable Device does...

Page 18: ...tuation of the connector during detach since the Portable Device is detached while packets are exchanged This may provoke malfunction of the S2R72A21 2 Host SoC would judge HS disconnection by Bus invalid condition From the Bus Switch path connection the Host SoC will judge the disconnection of the Portable Device by detecting the EXT port s Bus invalid condition for a certain period of time 3 Not...

Page 19: ...tch as a Device In this case the Portable Device and the Host SoC would change its role nevertheless it s naming However for the convenience within this documents would keep calling the name as Portable Device and Host SoC If the Bus becomes Floating during the Role Switch period we recommend to pull down the Bus by 1MΩ and etc 5 2 4 Method to detect disconnection of Portable Device When the Porta...

Page 20: ...nnection by Bus invalid condition From the Bus Switch path connection the Host SoC will judge the disconnection of the Portable Device by detecting the INT port s Bus invalid condition for a certain period of time 3 S2R72A21 is stopped by Host SoC Notification from the Host SoC to S2R72A21 of the disconnection detection is done by shut off VBUS supply This initializes the state which deviated from...

Page 21: ... as a Device In this case the Portable Device and the Host SoC would change its role nevertheless it s naming However for the convenience within this documents would keep calling the name as Portable Device and Host SoC If the Bus becomes Floating during the Role Switch period we recommend to pull down the Bus by 1MΩ and etc 5 3 4 Method to detect disconnection of Portable Device When the Portable...

Page 22: ...nnection by Bus invalid condition From the Bus Switch path connection the Host SoC will judge the disconnection of the Portable Device by detecting the EXT port s Bus invalid condition for a certain period of time 3 S2R72A21 is stopped by Host SoC Notification from the Host SoC to S2R72A21 of the disconnection detection is done by shut off VBUS supply This initializes the state which deviated from...

Page 23: ... condition With these specific features USB compliance test can be done with combing the general Host 6 2 General Test method 6 2 1 High speed Signal Quality This is the explanation of HS eye pattern acquisition method In order to acquire the HS eye pattern it is required to set the S2R72A21 to HS state HS synchronizer ON 1 Please connect the HS Host to the INT port and HS Device to the EXT port a...

Page 24: ...ase make the HS Host into Test J K mode and input the Test J K signal from the Host to the INT port Herewith the S2R72A21 would output the High speed J K from the EXT port 3 Please measure the voltage level using the High speed J K signal which is output from the EXT port When doing another testing after Test_J K output please either set the ENABLE pin or XRESET pin of S2R72A21 0 1 or turn off the...

Page 25: ...ical_tests usbhset HS USB memory IO Data U2 ADP8G Test Fixture USB IF USB 2 0 Hi Speed Signal Quality Test Fixture Host test fixture Oscilloscope Tektronix MSO70404 SMA cable Keysight 15443A Matched Cable Pair 6 3 2 Test procedure 1 Connect the Host PC and the S2R72A21 Evaluation board INT port side Figure 6 3 2 1 Procedure 1 connection 2 Connect the HS USB memory to the S2R72A21evaluation board s...

Page 26: ...6 3 2 3 Procedure 3 HS Electrical Test Tool picture 4 Select TEST_PACKET via Port Control Figure 6 3 2 4 Procedure 4 HS Electrical Test Tool picture 5 Push EXECUTE after inputting the Port connected to the S2R72A21evaluation board With this operation the Test Packet would be output from the Host PC and then output from the EXT port via S2R72A21 s HS Synchronizer Figure 6 3 2 5 Procedure 5 HS Elect...

Page 27: ...ion 6 3 of the data sheet a packet delay would occur during HS packet re synchronization When the system with S2R72A21 is tested as a Host the total period of the Host Controller s response and the round trip delay of S2R72A21 would be observed as the total system s period Due to this there would be a possibility exceeding the max response period of 192 bit times stated on the EL_22 Detail would b...

Page 28: ...btained TID 120001008 Epson has explained the product characteristics of the USB2 0 Re Synchronization IC to Allion and Granite River Labs Japan Ltd GRL Please contact the following Allion or GRL window for compliance testing in relates to product using S2R72A21 If the contact person is unknown please ask Epson s local sales window Allion Japan Inc Standards Compliance Division Email SCDivision al...

Page 29: ...nsideration for the DP DM signal wiring to ensure impedance matching and prevent reflection The differential impedance in the DP DM signal line must be 90Ω Sufficient attention must be paid to impedance matching if other connectors and cables are inserted between the S2R72A21 and the USB receptacle The inner layer right under the signal line must be a non separated GND plane Signal lines that coul...

Page 30: ...e 7 2 2 2 Typical varistor wiring Connector The DP DM signal quality may deteriorate if a non USB certified connector is used It is recommended that USB certified connectors be used The same applies to the cables used Connection example of additional components Figure 7 2 2 3 Connection example of additional components Remarks In case when you add some capacity components such as Chip varistor and...

Page 31: ...reference current which determines the USB analog circuit characteristics so the analog characteristics will be affected if the tolerances are overly large A resistance with the specified accuracy must always be used FVDD pin LVDDC pin LVDDM pin Each of these 3 pins needs 0 1uF and 10uF capacitors to be placed between the VSS These capacitors should be mounted as close as possible to these pins in...

Page 32: ...30 Seiko Epson Corporation S2R72A21 Application Note Rev 1 00 Each HVDD pin 0 1uF Power supply source 10uF VSS pins The VSS pins must be connected to a non separated GND plane via low impedance ...

Page 33: ...S2R72A21 Application Note Seiko Epson Corporation 31 Rev 1 00 Revision History Attachment 1 Rev No Date Section Category Contents Rev 1 00 9 12 2020 All New New issue ...

Page 34: ...hina Phone 86 21 5330 4888 FAX 86 21 5423 4677 Shenzhen Branch Room 804 805 8 Floor Tower 2 Ali Center No 3331 Keyuan South RD Shenzhen bay Nanshan District Shenzhen 518054 China Phone 86 10 3299 0588 FAX 86 10 3299 0560 Epson Taiwan Technology Trading Ltd 15F No 100 Songren Rd Sinyi Dist Taipei City 110 Taiwan Phone 886 2 8786 6688 Epson Singapore Pte Ltd 438B Alexandra Road Block B Alexandra Tec...

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