3. Endian Settings for 16-bit Bus Width Connection
4
EPSON
S1R72V17 CPU Connection Guide
(Rev. 1.0)
3. Endian Settings for 16-bit Bus Width Connection
This section describes endian settings when connecting to a CPU with a 16-bit bus width.
The discussion of the S1R72V17 registers divides them into the following three types. For register details,
refer to the
S1R72V17 Technical Manual
.
1) Word register:
Registers with _H/_L/_HH/_HL/_LH/_LL at the end of the register name
2) Byte register:
Registers not corresponding to Word or FIFO registers
3) FIFO register:
RAM_Rd_00 to _1F/RAM_WrDoor_0,1/FIFO_Rd_0,1/FIFO_Wr_0,1/
FIFO_ByteRd registers
3.1
Connection to Big-endian CPU
Access is normally in the mode with “0” set in the CPU_Config register (0x075h address)
CPU_Endian bit.
1) Access to Word register
The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0]
bus to the last byte of the Word register.
The example below illustrates the writing and reading of 0x1234h data to/from the Word register.
Writing:
The data (12h) in the CPU memory even-number address is saved to the first byte
of the S1R72V17 Word register.
Reading:
The first byte data (12h) of the S1R72V17 Word register is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
12h
Even-number address
34h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8]
Lower byte [7:0]
12h
34h
CPU register
D[15:8]
D[7:0]
CPU data bus
D[15:0] bus connected unchanged
S1R72V17
D[15:8]
D[7:0]
V17 data bus
12h
34h
V17 Word register
Higher byte [15:8]
Lower byte [7:0]
_H, _HH, _LH registers
_L, _HL, _LL registers
Fig. 3-1 Access to Word registers (big-endian CPU)
