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S5U13513P00C100 Board Layout

S5U13513P00C100 Evaluation Board

Seiko Epson Corporation

Rev. 1.2

Figure 7-2: S5U13513P00C100 Board Layout - Bottom View

Summary of Contents for S1D13513

Page 1: ...Rev 1 2 S1D13513 Display Controller S5U13513P00C100 Evaluation Board User Manual Document Number X78A G 003 01 2 ...

Page 2: ... to export and or to otherwise dispose of the products and any technical information furnished if any for the devel opment and or manufacture of weapon of mass destruction or for other military purposes All brands or product names mentioned herein are trademarks and or registered trademarks of their respective companies SEIKO EPSON CORPORATION 2006 2018 All rights reserved Evaluation Board Kit and...

Page 3: ...ower 13 4 2 Clocks 14 4 3 Reset 14 4 4 Host Interface 15 4 4 1 Connecting to the Epson S5U13U00P00C100 USB Adapter Board 15 4 4 2 Connecting to the Epson PC Card Extender Board 15 4 4 3 Direct Host Bus Interface Support 16 4 5 LCD Panel Interface 17 4 6 Camera Interface 18 4 7 YUV Output for TV Display 19 4 8 Keypad Interface 19 4 9 PWM Outputs 19 4 10 GPIO Connections 19 4 11 JTAG Connector 20 5 ...

Page 4: ...4 Seiko Epson Corporation S5U13513P00C100 Evaluation Board Rev 1 2 ...

Page 5: ...2 0 With some minor modifications it is possible to connect the S5U13513P00C100 evaluation board to a Epson PC Card Extender board instead of a USB Adapter board The S5U13513P00C100 evaluation board can also be used with many other native platforms via the host connectors which provide the appropriate signals to support a variety of CPUs This document is updated as appropriate Please check for the...

Page 6: ...it Headers for connection to the S5U13U00P00C100 USB Adapter board or to the PC Card Extender board Headers for connecting to various Host Bus Interfaces Headers for connecting to LCD panels Headers for connecting to cameras On board 10MHz crystal used for OSC1 clock input On board 27MHz crystal used for OSC2 clock input 14 pin DIP socket used to install an oscillator for CLKI3 clock input 3 3V in...

Page 7: ...0 Figure 3 1 Configuration DIP Switch SW1 Location All S1D13513 configuration inputs CNF 8 0 are fully configurable using DIP switch SW1 as described below Table 3 1 Summary of Power On Reset Options SDU13513B00C SW1 10 1 Config S1D13513 CNF 8 0 Config Power On Reset State 1 ON 0 OFF SW1 10 Not used SW1 9 8 CNF 8 7 00b CLKI3 is the PLL1 clock source 01b BUSCLK is the PLL1 clock source 10b OSC1 is ...

Page 8: ...2 CS 01001b Reserved 01010b Reserved 01011b Reserved 01100b Parallel Direct 80 Type 1 2 CS 01101b Parallel Direct 68 2 CS 01110b Reserved 01111b Reserved 10000b Serial on HVDD1 Data valid on falling edge 10001b Serial on HVDD2 Data valid on falling edge 10010b Reserved 10011b Reserved 10100b Reserved 10101b Reserved 10110b Reserved 10111b Reserved 11000b Serial on HVDD1 Data valid on rising edge 1...

Page 9: ...e HIgh WAIT with tri state 01011b Reserved 01100b MC68000 Big Endian Active High WAIT with tri state 01101b Reserved 01110b MC68030 Big Endian Active High WAIT with tri state 01111b Reserved 10000b PR31500 31700 TX3912 Little Endian Active Low WAIT with tri state 16 bit memory accesses only 10001b PR31500 31700 TX3912 Little Endian Active Low WAIT always driven 16 bit memory accesses only 10010b R...

Page 10: ...sition 2 3 No Jumper JP1 COREVDD Normal COREVDD current measurement JP2 PLLVDD1 Normal PLLVDD1 current measurement JP3 PLLVDD2 Normal PLLVDD2 current measurement JP4 OSCVDD1 Normal OSCVDD1 current measurement JP5 OSCVDD2 Normal OSCVDD2 current measurement JP6 HVDD1 Normal HVDD1 current measurement JP7 HVDD2 Normal HVDD2 current measurement JP8 HVDD3 Normal HVDD3 current measurement JP9 HVDD4 Norma...

Page 11: ...talled the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper The jumper associated to each power supply is as follows JP1 for COREVDD JP2 for PLLVDD1 JP3 for PLLVDD2 JP4 for OSCVDD1 JP5 for OSCVDD2 JP6 for HVDD1 Host interface JP7 for HVDD2 LCD Panel interface JP8 for HVDD3 Camera2 interface JP9 for HVDD4 Camera1 interface JP10 for HVDD...

Page 12: ... jumper is at position 1 2 the external SDRAM is 32 bit wide and memory size is 32MB The memory consists of 2 chips in parallel each 16MB and 16 bit wide When the jumper is at position 2 3 the external SDRAM is 16 bit wide and memory size is 16MB In this position one memory chip is disabled and only one chip is active 16MB and 16 bit wide Figure 3 3 Configuration Jumper Location JP11 JP11 ...

Page 13: ...13513 Display Controller requires 1 8V and 3 3V power supplies 1 8V power is provided by the on board linear voltage regulator It is used for CoreVDD PLLVDD1 PLLVDD2 OSCVDD1 OSCVDD2 3 3V power must be provided by the external power supply It is used for HVDD1 host interface HIOVDD HVDD2 LCD panel interface PIOVDD HVDD3 camera 2 interface CIOVDD2 HVDD4 camera 1 interface CIOVDD1 and HVDD5 SDRAM int...

Page 14: ...SC2 use crystals 10MHz for OSC1 and 27MHz for OSC2 For the S5U13513P00C100 evaluation board CLKI3 is not used and is pulled to ground by a 10k resistor However if CLKI3 is required connect a 14 pin DIP package oscillator in the Y1 footprint For the S5U13513P00C100 evaluation board BUSCLK is not used and is pulled to ground by a 10k resistor However if BUSCLK is required the BUSCLK pin is connected...

Page 15: ...to the S5U13513P00C100 board The modifications required for the S5U13513P00C100 board are 1 Remove R107 and R108 0 ohm resistors size 0603 2 Remove R109 and R112 0 ohm resistors size 0402 3 Populate R110 and R111 with 0 ohm resistors size 0402 or short the pads on the board 4 Set DIP switch SW1 5 1 to 00100b CNF 4 0 00100b to select Parallel Direct 80 Type 1 1CS host interface To use a modified S5...

Page 16: ...3P00C100 to be connected to a variety of development platforms However connectors H2 and H3 are not populated on the S5U13513P00C100 evaluation board If connectors H2 and H3 are added all host interface signals must match HVDD1 of the S1D13513 For the maximum minimum values of the voltages refer to the S1D13513 Hardware Functional Specification document number X78B A 001 xx The following diagram s...

Page 17: ...H5 see Schematic Diagrams on page 24 On the evaluation board there is an adjustable 6 24V 40mA max power supply This voltage is provided only on connector H4 it is not used elsewhere on the board It is intended for use to power the LED backlight on some LCD panels The voltage is adjusted by the R106 pot Note For LCD panels that use CCFL backlight an external power supply must be used to pro vide p...

Page 18: ... configured as GPIO pins Camera2 interface pins Keypad interface pins or PWM output pins For detailed S1D13513 GPIO pin mapping refer to the S1D13513 Hardware Functional Specification document number X78B A 001 xx Connector H6 and H7 may be used to evaluate any function for which the GPIOA 7 0 GPIOB 7 0 GPIOC 7 0 GPIOD 3 0 can be configured The S1D13513 has an I2C interface which uses two signals ...

Page 19: ... used to control the brightness of 4 LEDs It also has an input AUDIN which is used to control the overall operation of the PWM outputs The PWM output function is multiplexed on the GPIOA 7 5 and GPIOB 7 pins AUDIN is multiplexed on the GPIOD 3 pin These pins are routed to connector H6 and H7 4 10 GPIO Connections The S1D13513 Display Controller GPIO pins have multiple functions All the GPIO pins a...

Page 20: ...e S1D13513 design includes a JTAG interface All the JTAG signals are available on connector H1 however connector H1 is not populated on the board For the pinout of connector H1 see Schematic Diagrams on page 24 The following diagram shows the location of the JTAG connector H1 Figure 4 4 JTAG Connector Location H1 ...

Page 21: ...a 0402ZRY5V7BB103 3 2 C20 C23 1nF Yageo America 04022R102K9B20D 4 2 C21 C24 10uF Panasonic ECG ECJ CV50J106M 5 4 C61 C62 C63 C64 18pF Panasonic ECG ECJ 0EC1H180J 6 2 C67 C68 10uF Panasonic ECG ECJ 2FB1A106K 7 2 C97 C99 1uF Panasonic ECG ECJ 0EB0J105M 8 1 C101 4 7uF 10V T Kemet T491B475K010AS 9 1 C102 10pF Panasonic ECG ECJ 0EC1H100D 10 1 C103 1uF 50V TDK C3216X7R1H105K 11 1 D1 DIODE DIODE SCHOTTKY...

Page 22: ... R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R32 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R68 R69 R77 33 1 26 7 R31 R33 R34 R70 R96 R107 R108 0 27 12 R59 R60 R61 R62 R63 R64 R65 R66 R67 R78 R79 R81 10k 28 6 R71 R76 R80 R102 R109 R112 0 29 2 R72 R73 1M 30 2 R74 R75 220 31 1 R82 270 1 32 15 R83 R85 R87 R88 R89 R90 R91 R92 R93 R94 R95 R97 R99 R101 R1...

Page 23: ... S1D13513 PBGA256 44 2 U2 U3 IS42S16800D 7TL alternate Micron MT48LC8M16A2P 7E ISSI IS42S16800D 7TL 45 1 U4 TPS3801L30DCKR IC 2 64V SUPPLY MON SOT 323 5 Texas Instruments TPS3801L30DCKR 46 1 U5 MIC37100 1 8WS Alternate MIC39100 1 8WS Micrel MIC37100 1 8WS 47 1 U6 TPS61040 IC CONV DC DC BOOST LP SOT 23 5 TI TPS61040DVBR 48 1 X1 MA 506 10 0000M 49 1 X2 MA 506 27 0000M 50 0 Y1 14 Pin DIP AMP 2 641609...

Page 24: ... VSS G13 OSCVSS1 L3 OSCVSS2 M4 PLLVSS1 N2 PLLVSS2 R2 COREVDD L6 VSS H9 COREVDD P3 COREVDD P14 HVDD1 E2 HVDD1 G4 HVDD2 L5 HVDD2 L8 HVDD2 T6 HVDD3 R11 HVDD4 L12 HVDD4 M13 HVDD4 T15 HVDD5 B9 HVDD5 C12 HVDD5 E15 HVDD5 G11 HVDD5 H12 HVDD5 J12 OSCVDD1 L4 OSCVDD2 M3 PLLVDD1 P1 PLLVDD2 P2 AB0 B1 AB19 B7 AB20 E7 FPDAT18 R5 FPDAT19 K5 FPDAT20 P5 FPDAT21 T3 FPDAT22 R3 FPDAT23 K4 BUSCLK G2 INT2 H6 BS H3 Reser...

Page 25: ...2 NC 3 C83 0 01uF C83 0 01uF C77 0 1uF C77 0 1uF R76 0 R76 0 C63 18pF C63 18pF C89 0 01uF C89 0 01uF C72 0 1uF C72 0 1uF C95 0 01uF C95 0 01uF R78 10k R78 10k C105 0 1uF C105 0 1uF C65 0 1uF C65 0 1uF C84 0 01uF C84 0 01uF C78 0 1uF C78 0 1uF SW2 SW TACT SPST SW2 SW TACT SPST 2 4 3 1 C90 0 01uF C90 0 01uF C62 18pF C62 18pF C73 0 1uF C73 0 1uF C96 0 01uF C96 0 01uF SH11 100 in Jumper Shunt SH11 100...

Page 26: ...t of Doc 1 0 Host connectors B 3 4 Friday January 19 2007 Title Size Document Number Rev Date Sheet of Doc 1 0 Host connectors B 3 4 Friday January 19 2007 This resistor is used to pull down BUSCLK input when it is not used If BUSCLK input is used then this resistor can be removed R109 0 R109 0 R108 0 R108 0 R110 NP R110 NP TPGND3 TP_SMT TPGND3 TP_SMT 1 R111 NP R111 NP TPGND2 TP_SMT TPGND2 TP_SMT ...

Page 27: ...amera GPIO connectors B 4 4 Friday January 19 2007 Place these capacitors close to pin 15 of the header These resistors are to prevent GPIOA 7 0 and GPIOB7 GPIOB 4 0 from floating if they are not used GPIOB 6 5 are pulled up If any of GPIOA 7 0 GPIOB7 or GPIOB 4 0 are used the corresponding pull down resistor may be removed Place these capacitors close to pin 15 of the header Internal Step Up 6 to...

Page 28: ...S5U13513P00C100 Board Layout 28 Seiko Epson Corporation S5U13513P00C100 Evaluation Board Rev 1 2 7 S5U13513P00C100 Board Layout Figure 7 1 S5U13513P00C100 Board Layout Top View ...

Page 29: ...S5U13513P00C100 Board Layout S5U13513P00C100 Evaluation Board Seiko Epson Corporation 29 Rev 1 2 Figure 7 2 S5U13513P00C100 Board Layout Bottom View ...

Page 30: ...tion updated some formatting X78A G 003 01 Revision 1 1 Issued September 6 2010 remove references to type 3 interface X78A G 003 01 Revision 1 0 Issued March 30 2007 minor edits updated schematics updated parts list added board layout X78A G 003 00 Revision 0 02 revised manual due to design changes added new schematics added new parts list X78A G 003 00 Revision 0 01 Initial draft of manual ...

Page 31: ...ort For more information on Epson Display Controllers visit the Epson Global website https global epson com products_and_drivers semicon products display_controllers For Sales and Technical Support contact the Epson representative for your region https global epson com products_and_drivers semicon information support html ...

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