Schematic Diagrams
S5U13513P00C100 Evaluation Board
Seiko Epson Corporation
25
Rev. 1.2
Figure 6-2: S5U13513P00C100 Schematics (2 of 4)
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
MEM
D
Q
4
MEM
D
Q
2
7
MEM
D
Q
2
1
MEM
D
Q
2
MEM
D
Q
1
9
MEM
D
Q
7
MEM
D
Q
3
1
MEM
D
Q
1
3
MEM
D
Q
3
MEM
D
Q
2
4
MEM
D
Q
3
0
MEM
D
Q
2
2
MEM
D
Q
1
MEM
D
Q
1
5
MEM
D
Q
1
1
MEM
D
Q
1
0
MEM
D
Q
8
MEM
D
Q
2
3
MEM
D
Q
1
6
MEM
D
Q
2
6
MEM
D
Q
1
4
MEM
D
Q
2
5
MEM
D
Q
9
MEM
D
Q
0
MEM
D
Q
1
2
MEM
D
Q
6
MEM
D
Q
5
MEM
D
Q
1
8
MEM
D
Q
2
9
MEM
D
Q
2
8
MEM
D
Q
2
0
MEM
D
Q
1
7
MEM
A
5
MEM
A
2
MEM
A
3
MEM
A
9
MEM
A
6
MEM
A
8
MEM
A
1
MEM
A
0
MEM
A
1
0
MEM
A
7
MEM
A
1
1
MEM
A
4
MEM
A
7
MEM
A
8
MEM
A
5
MEM
A
0
MEM
A
1
MEM
A
4
MEM
A
3
MEM
A
6
MEM
A
1
0
MEM
A
1
1
MEM
A
2
MEM
A
9
ME
M
BA1
ME
M
BA0
ME
M
W
E
#
ME
M
C
A
S
#
ME
M
R
A
S
#
ME
M
C
S
#
ME
M
C
K
E
ME
M
C
LK
ME
M
BA0
ME
M
C
A
S
#
ME
M
R
A
S
#
ME
M
C
LK
ME
M
BA1
ME
M
C
K
E
ME
M
W
E
#
ME
MC
S
#
3.
3
V
DD
3.
3V
D
D
3.
3V
D
D
3.
3V
D
D
3.
3V
D
D
G
ND1
GN
D
2
G
ND2
HI
O
V
DD
HI
O
V
DD
GN
D
1
3.
3
V
DD
1.
8V
D
D
ME
M
D
Q
[3
1
:0
]
1
ME
M
D
Q
[3
1
:0
]
1
ME
MA
[1
1:
0
]
1
ME
MA
[1
1:
0
]
1
MEM
B
A
0
1
MEM
B
A
1
1
MEM
C
S#
1
MEM
W
E
#
1
MEM
C
AS
#
1
MEM
R
AS
#
1
MEM
D
Q
M
0
1
MEM
D
Q
M
1
1
MEM
D
Q
M
2
1
MEM
D
Q
M
3
1
MEM
C
KE
1
MEM
C
LK
1
OS
C
I1
1
CLK
I3
1
OS
C
I2
1
OS
C
O
2
1
OS
C
O
1
1
RE
S
E
T
#
1
CM
_
R
S
T
#
4
H
O
S
T
_
R
ES
ET
#
3
Ti
tle
S
iz
e
Do
cu
m
ent
Nu
m
be
r
Re
v
Dat
e
:
Sh
ee
t
of
<D
oc
>
1
.0
SD
R
A
M
/ C
lo
cks
/ R
ese
t /
1
.8
V
S
u
pp
ly
B
24
F
rid
ay
, J
anu
ar
y
1
9,
20
07
Ti
tle
S
iz
e
Do
cu
m
ent
Nu
m
be
r
Re
v
Dat
e
:
Sh
ee
t
of
<D
oc
>
1
.0
SD
R
A
M
/ C
lo
cks
/ R
ese
t /
1
.8
V
S
u
pp
ly
B
24
F
rid
ay
, J
anu
ar
y
1
9,
20
07
Ti
tle
S
iz
e
Do
cu
m
ent
Nu
m
be
r
Re
v
Dat
e
:
Sh
ee
t
of
<D
oc
>
1
.0
SD
R
A
M
/ C
lo
cks
/ R
ese
t /
1
.8
V
S
u
pp
ly
B
24
F
rid
ay
, J
anu
ar
y
1
9,
20
07
S
DRA
M
W
idt
h
S
el
e
ct
1 2
x
3
2 S
DRA
M
(
32
M
B
)
2 3
x
1
6 S
DRA
M
(
16
M
B
)
P
lac
e a
0.
01
u
F
a
n
d a
0.
1u
F
c
ap o
n
ea
ch
V
DD p
owe
r pi
n
of
th
e t
w
o S
DRA
M
c
h
ip
s.
P
lac
e
a
0.
01
uF
a
nd
a
0.
1u
F
c
a
p o
n ea
ch
V
DDQ
p
owe
r pi
n of
th
e t
w
o S
DRA
M
c
h
ip
s.
T
T
L/
C
M
O
S
O
sc
ill
at
or
T
his
r
es
is
to
r
is
u
se
d
to
pul
l down CLK
I3 i
n
put
w
h
en
o
sc
illa
to
r is
n
ot
us
e
d.
If
a
n
o
sc
illa
to
r
is
us
e
d,
th
en t
hi
s r
es
is
tor
ca
n
be
re
m
ov
ed.
C82
0.
1u
F
C82
0.
1u
F
R7
4
22
0
R7
4
22
0
C71
0.
1u
F
C71
0.
1u
F
C9
4
0.
01
uF
C9
4
0.
01
uF
U4
T
P
S
3
80
1L
30D
CK
R
U4
T
P
S
3
80
1L
30D
CK
R
GN
D
1
GN
D
2
MR
#
5
RE
S
E
T
#
3
VD
D
4
X1
M
A
-5
06
1
0.
0
00
0M
X1
M
A
-5
06
1
0.
0
00
0M
XI
N
1
XO
U
T
4
NC
2
NC
3
C8
3
0.
01
uF
C8
3
0.
01
uF
C77
0.
1u
F
C77
0.
1u
F
R76
0
R76
0
C6
3
18
pF
C6
3
18
pF
C8
9
0
.01u
F
C8
9
0
.01u
F
C7
2
0
.1uF
C7
2
0
.1uF
C95
0.
01
uF
C95
0.
01
uF
R7
8
10
k
R7
8
10
k
C10
5
0.
1u
F
C10
5
0.
1u
F
C65
0.
1u
F
C65
0.
1u
F
C84
0.
01
uF
C84
0.
01
uF
C7
8
0
.1uF
C7
8
0
.1uF
SW
2
SW
T
A
C
T
-S
PS
T
SW
2
SW
T
A
C
T
-S
PS
T
2
4
3
1
C90
0.
01
uF
C90
0.
01
uF
C62
18
pF
C62
18
pF
C7
3
0.
1u
F
C7
3
0.
1u
F
C96
0.
01
uF
C96
0.
01
uF
SH
11
.1
0
0 i
n
. J
u
m
pe
r S
h
un
t
SH
11
.1
0
0 i
n
. J
u
m
pe
r S
h
un
t
JP
1
1
HE
A
D
E
R
3
JP
1
1
HE
A
D
E
R
3
1
2
3
C85
0.
01
uF
C85
0.
01
uF
C7
9
0.
1u
F
C7
9
0.
1u
F
D1
DI
O
D
E
D1
DI
O
D
E
A
K
R7
7
33
1%
R7
7
33
1%
U5
M
IC
371
00
-1
.8
W
S
U5
M
IC
371
00
-1
.8
W
S
IN
1
OU
T
3
GND
2
TAB
4
C66
0.
1u
F
C66
0.
1u
F
L9 Fe
rr
ite
L9 Fe
rr
ite
C91
0.
01
uF
C91
0.
01
uF
SDRAM
2Mb x 16-bit x 4
banks
U3
IS
42
S
168
00
D
-7
T
L
SDRAM
2Mb x 16-bit x 4
banks
U3
IS
42
S
168
00
D
-7
T
L
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A1
0
22
A1
1
35
BA
1
21
BA
0
20
VS
SQ
6
VS
SQ
12
VS
SQ
52
VSS
28
VSS
41
VSS
54
VS
SQ
46
VD
D
1
VD
D
14
VD
D
27
V
DDQ
3
V
DDQ
9
V
DDQ
43
V
DDQ
49
D0
2
D1
4
D2
5
D3
7
D4
8
D5
10
D6
11
D7
13
D8
42
D9
44
D1
0
45
D1
1
47
D1
2
48
D1
3
50
D1
4
51
D1
5
53
DQ
M
L
15
DQ
M
H
39
WE
#
16
CA
S
#
17
RA
S
#
18
CS
#
19
CL
K
38
CK
E
37
NC
40
NC
36
R8
0
0
R8
0
0
C7
4
0.
1u
F
C7
4
0.
1u
F
Y1
14
-P
in
DI
P
Y1
14
-P
in
DI
P
OE
1
OU
T
8
GN
D
7
VD
D
14
C1
04
0.
1
uF
C1
04
0.
1
uF
R7
9
10
k
R7
9
10
k
C6
7
10
uF
C6
7
10
uF
C8
6
0
.01u
F
C8
6
0
.01u
F
C8
0
0.
1u
F
C8
0
0.
1u
F
C6
8
10
uF
C6
8
10
uF
C6
9
0.
1u
F
C6
9
0.
1u
F
C9
2
0
.01u
F
C9
2
0
.01u
F
C7
5
0
.1uF
C7
5
0
.1uF
R7
2
1M
R7
2
1M
X2
M
A
-5
06
27
.0
00
0M
X2
M
A
-5
06
27
.0
00
0M
XI
N
1
XO
U
T
4
NC
2
NC
3
SDRAM
2Mb x 16-bit x 4
banks
U2
IS
42
S
168
00
D
-7
T
L
SDRAM
2Mb x 16-bit x 4
banks
U2
IS
42
S
168
00
D
-7
T
L
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A1
0
22
A1
1
35
BA
1
21
BA
0
20
VS
SQ
6
VS
SQ
12
VS
SQ
52
VSS
28
VSS
41
VSS
54
VS
SQ
46
VD
D
1
VD
D
14
VD
D
27
V
DDQ
3
V
DDQ
9
V
DDQ
43
V
DDQ
49
D0
2
D1
4
D2
5
D3
7
D4
8
D5
10
D6
11
D7
13
D8
42
D9
44
D1
0
45
D1
1
47
D1
2
48
D1
3
50
D1
4
51
D1
5
53
DQ
M
L
15
DQ
M
H
39
WE
#
16
CA
S
#
17
RA
S
#
18
CS
#
19
CL
K
38
CK
E
37
NC
40
NC
36
C8
7
0.
01
uF
C8
7
0.
01
uF
C81
0.
1
uF
C81
0.
1
uF
C7
0
0.
1u
F
C7
0
0.
1u
F
R7
3
1M
R7
3
1M
C9
3
0.
01
uF
C9
3
0.
01
uF
C64
18
pF
C64
18
pF
C6
1
18
pF
C6
1
18
pF
C76
0.
1
uF
C76
0.
1
uF
R7
5
22
0
R7
5
22
0
C8
8
0.
01
uF
C8
8
0.
01
uF