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Epson S1C88650, Technical Manual

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18

EPSON

S1C88650 TECHNICAL MANUAL

5  PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

5 PERIPHERAL CIRCUITS AND

THEIR OPERATION

The peripheral circuits of the S1C88650 is interfaced with the CPU by means of the memory mapped

I/O method. For this reason, just as with other memory access operations, peripheral circuits can be
controlled by manipulating I/O memory. Below is a description of the operation and control method for
each individual peripheral circuit.

5.1 I/O Memory Map

Table 5.1.1(a)  I/O Memory map (00FF00H–00FF03H)

SR

R/W

1

0

Address Bit

Name

Function

Comment

00FF00

(MCU)

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bus mode

CPU mode

R/W register

R/W register

R/W register

CE2 (R32)

CE1 (R31)

CE0 (R30)

Reserved register

In Single chip mode, 

these setting are fixed 

at DC output.

CE signal output

DC (R3x) output

Expansion

Maximum

1

1

1

CE2 enable

CE1 enable

CE0 enable

Single chip

Minimum

0

0

0

CE2 disable

CE1 disable

CE0 disable

BUSMOD

CPUMOD

–

–

–

CE2

CE1

CE0

CE signal output Enable/Disable

Enable:

Disable:

00FF00

(MPU)

D7

D6

D5

D4

D3

D2

D1

D0

1

0

0

0

0

0

0

1

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bus mode

CPU mode

R/W register

R/W register

R/W register

CE2 (R32)

CE1 (R31)

CE0 (R30)

Expansion mode only

Reserved register

Expansion

Maximum

1

1

1

CE2 enable

CE1 enable

CE0 enable

–

Minimum

0

0

0

CE2 disable

CE1 disable

CE0 disable

BUSMOD

CPUMOD

–

–

–

CE2

CE1

CE0

CE signal output Enable/Disable

Enable:

Disable:

00FF01 D7

D6

D5

D4

D3

D2

D1

D0

SPP7

SPP6

SPP5

SPP4

SPP3

SPP2

SPP1

SPP0

0

0

0

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

Stack pointer page address

< SP page allocatable address >

• Single chip mode:

• Expansion mode:

1

1

1

1

1

1

1

1

(MSB)

(LSB)

00FF02 D7

D6

D5

D4

D3

D2

D1

D0

EBR

WT2

WT1

WT0

CLKCHG

SOSC3

–

–

0

0

0

0

1

1

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

BREQ

BACK

OSC3

On

1

1

WT2

1
1
1
1
0
0
0
0

WT1

1
1
0
0
1
1
0
0

WT0

1
0
1
0
1
0
1
0

Number

of state

14
12
10

8
6
4
2

Input port

Output port

OSC1

Off

0

0

Bus release enable register

(K03 and R33 terminal specification)

Wait control register

CPU operating clock switch

OSC3 oscillation On/Off control

R/W register

R/W register

No wait

Reserved register

00FF03 D7

D6

D5

D4

D3

D2

D1

D0

–

–

–

–

–

–

0

0

R/W

R/W

–

–

–

–

–

–

Power source select for LCD voltage regulator

Power voltage booster On/Off control

Constantly "0" when

being read

–

–

–

–

–

–

V

D2

On

–

–

–

–

–

–

V

DD

Off

–

–

–

–

–

–

VDSEL

DBON

K03

R33

only 0 page

0–27H page

CE signal output

DC (R3x) output

Note:

 ____

All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.

Summary of Contents for S1C88650

Page 1: ...Technical Manual CMOS 8 BIT SINGLE CHIP MICROCOMPUTER S1C88650 Technical Hardware S1C88650 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...ation Package D die form F QFP Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 88348 D1 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Ex EVA board Px Peripheral board Wx Flash ROM writer for the microcomputer Xx ROM writer peripheral board Cx C compiler package Ax Assembler package Dx Util...

Page 4: ......

Page 5: ... 3 6 External Bus 11 3 6 1 Data bus 11 3 6 2 Address bus 12 3 6 3 Read RD write WR signals 12 3 6 4 Chip enable CE signal 12 3 6 5 WAIT control 13 3 6 6 Bus authority release state 14 4 INITIAL RESET 15 4 1 Initial Reset Factors 15 4 1 1 RESET terminal 15 4 1 2 Simultaneous LOW level input at input port terminals K00 K03 16 4 1 3 Initial reset sequence 16 4 2 Initial Settings After Initial Reset 1...

Page 6: ... 52 5 7 I O Ports P ports 54 5 7 1 Configuration of I O ports 54 5 7 2 Mask option 54 5 7 3 I O control registers and I O mode 54 5 7 4 Pull up control 55 5 7 5 Special output 55 5 7 6 Control of I O ports 57 5 7 7 Programming notes 60 5 8 Serial Interface 61 5 8 1 Configuration of serial interface 61 5 8 2 Switching of terminal functions 61 5 8 3 Transfer modes 62 5 8 4 Clock source 63 5 8 5 Tran...

Page 7: ... 13 3 Programming note 126 5 14 Interrupt and Standby Status 127 5 14 1 Interrupt generation conditions 127 5 14 2 Interrupt factor flag 129 5 14 3 Interrupt enable register 130 5 14 4 Interrupt priority register and interrupt priority level 131 5 14 5 Exception processing vectors 132 5 14 6 Control of interrupt 133 5 14 7 Programming notes 135 6 SUMMARY OF NOTES 136 6 1 Notes for Low Current Cons...

Page 8: ...ANUAL Peripheral Circuit Board for S1C88650 163 A 1 Names and Functions of Each Part 163 A 2 Precautions 165 A 2 1 Precaution for operation 165 A 2 2 Differences from actual IC 165 A 3 Connecting to the Target System 168 A 4 Product Specifications 171 APPENDIX B USING KANJI FONT 172 ...

Page 9: ...4 bits can be used as the source clock inputs for PWM timers and 1 bit as a bus request signal input 0 3 bits when the external bus is used 26 bits when the external bus is not used 48K bytes program ROM 896K bytes kanji font ROM can be used for a program and data ROM when no font data is stored 8K bytes RAM 768 bytes display memory 8 bits when the external bus is used 16 bits when the external bu...

Page 10: ...grammable Timer Event Counter Clock Timer Power Generator RAM 8K bytes EXCL0 EXCL3 K04 K07 TOUT0 TOUT3 P14 P15 TOUT2 TOUT3 P17 P00 P07 D0 D7 P10 SIN P11 SOUT P12 SCLK P13 SRDY R00 R07 R10 R17 R20 R23 A0 A7 A8 A15 A16 A19 R24 R25 RD WR R30 R32 CE0 CE2 R33 BACK SEG0 SEG125 COM0 COM31 P14 TOUT0 TOUT1 P15 TOUT2 TOUT3 P16 FOUT P17 TOUT2 TOUT3 VDD VSS VD1 VD2 VC1 VC5 CA CG LCD Driver ROM 48K bytes 896K ...

Page 11: ...C1 N C N C N C N C N C VDD OSC3 OSC4 VSS VD1 OSC1 OSC2 TEST RESET MCU MPU K07 EXCL3 K06 EXCL2 K05 EXCL1 K04 EXCL0 K03 BREQ K02 K01 K00 P17 TOUT2 TOUT3 P16 FOUT P15 TOUT2 TOUT3 P14 TOUT0 TOUT1 P13 SRDY P12 SCLK P11 SOUT P10 SIN Pin No Pin name 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 1...

Page 12: ...rminal Input terminals K00 K02 Input terminal K03 or bus request signal input terminal BREQ Input terminal K04 or programmable timer external clock input terminal EXCL0 Input terminal K05 or programmable timer external clock input terminal EXCL1 Input terminal K06 or programmable timer external clock input terminal EXCL2 Input terminal K07 or programmable timer external clock input terminal EXCL3 ...

Page 13: ...option list The following shows the options for configuring the Peripheral Circuit Board S5U1C88000P1 with S5U1C88649P2 installed in the ICE S5U1C88000H5 The selections do not affect the IC s mask option A OSC1 SYSTEM CLOCK 1 Internal Clock 2 User Clock B OSC3 SYSTEM CLOCK 1 Internal Clock 2 User Clock When User Clock is selected input a clock to the OSC1 terminal When Internal Clock is selected t...

Page 14: ...Level 2 CMOS Schmitt 8 ______ WATCHDOG TIMER NMI GENERATION CYCLE 1 32768 fOSC1 0 75 1 sec cycle when fOSC1 32 kHz 2 65536 fOSC1 1 5 2 sec cycle when fOSC1 32 kHz 3 131072 fOSC1 3 4 sec cycle when fOSC1 32 kHz 4 262144 fOSC1 6 8 sec cycle when fOSC1 32 kHz This mask option can select whether the pull up resistor for the I O port terminal it works during input mode is used or not It is possible to ...

Page 15: ...he LCD system voltage regulator Either VDD or VD2 can be selected as the power source for the LCD system voltage regulator according to the VDD power supply voltage level Table 2 2 2 Power source for LCD system voltage regulator Supply voltage VDD 1 8 2 5 V 2 5 3 6 V Power source for LCD system voltage regulator VD2 VDD The VD2 voltage is about double the VDD voltage level Refer to Chapter 8 ELECT...

Page 16: ...n external memory which overlaps the internal RAM area is expanded the RAM area is not released to external memory Access to this area is via internal RAM 3 2 3 I O memory A memory mapped I O method is employed in the S1C88650 for interfacing with internal peripheral circuit Peripheral circuit control bits and data register are arranged in data memory space Control and data exchange are conducted ...

Page 17: ... bus mode settings are made external memory can be accessed 3 3 Exception Processing Vectors 000000H 00004BH in the program area of the S1C88650 is assigned as exception processing vectors Furthermore from 00004EH to 0000FFH software interrupt vectors are assignable to any two bytes which begin with an even address Table 3 3 1 lists the vector addresses and the exception processing factors to whic...

Page 18: ...0H to 00FFFFH is assigned to internal memory and cannot be used to access an external device When accessing internal memory in this mode ____ ____ _____ the chip enable CE and read RD write WR signals are not output to external memory and the data bus D0 D7 goes into high impedance status or pull up status Consequently in cases where addresses overlap in external and internal memory the areas in e...

Page 19: ...ed This mode is suitable for large scale program and data memory systems 3 6 External Bus The S1C88650 has bus terminals that can address a maximum of 1M 3 bytes and memory and other devices can be externally expanded according to the range of each bus mode described in the previous section S1C88650 External device Address bus A0 A19 Data bus D0 D7 RD WR CE0 CE1 CE2 BREQ BACK External device Exter...

Page 20: ...gnal output terminals ____ _____ When set as read RD write WR signal output terminal the data register and high impedance control register for each output port R24 R25 are detached from the output circuit and is usable as a general purpose data register with read write capabilities See Section 3 6 5 WAIT control for the output timing of the signal Output port RD WR signal R24 R25 RD WR Bus mode Bu...

Page 21: ...0 is equipped with a WAIT function which prolongs access time See the S1C88 Core CPU Manual for details of the WAIT function The WAIT state numbers to be inserted can be selected in software from a series of 8 as shown in Table 3 6 5 1 Table 3 6 5 1 Selectable WAIT state numbers Selection No Insert states 1 0 2 2 3 4 4 6 5 8 6 10 7 12 8 14 One state is a 1 2 cycle of the clock in length The WAIT s...

Page 22: ...to a high impedance ________ state outputs a LOW level from the BACK terminal and releases bus authority ________ As soon as a LOW level is output from the BACK terminal the external device can use the external bus When DMA is completed the external device ________ returns the BREQ terminal to HIGH and releases bus authority Figure 3 6 6 2 shows the bus authority release sequence During bus author...

Page 23: ...ram initialization routine which begins at the readout address is executed Internal initial reset fOSC3 1 024 Hz Reset signal fOSC1 256 Hz K00 Input port K00 K01 Input port K01 K02 Input port K01 K03 Input port K03 RESET SLEEP status Oscillation stability waiting signal OSC1 oscillation circuit Divider OSC2 OSC1 OSC3 oscillation circuit Divider Selector OSC4 OSC3 R Q S Operating clock status Reset...

Page 24: ...illation stabilization waiting time 512 fOSC3 sec have elapsed Figure 4 1 3 1 shows the operating sequence following initial reset release The CPU starts operating in synchronization with the OSC3 clock after reset status is released Also when using the initial reset by simultaneous LOW level input into the input port you should be careful of the following points 1 During SLEEP status since the ti...

Page 25: ...B CB EP XP YP Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 1 1 01H Undefined 00H 00H 00H Bit length 8 8 8 8 16 16 16 16 8 1 1 1 1 1 1 1 1 8 8 8 8 8 Reset exception processing loads the preset values stored in 0 bank 0000H 0001H into the PC At the same time 01H of the NB initial value is loaded into CB Initialize the registers which are not i...

Page 26: ...r R W register R W register CE2 R32 CE1 R31 CE0 R30 Expansion mode only Reserved register Expansion Maximum 1 1 1 CE2 enable CE1 enable CE0 enable Minimum 0 0 0 CE2 disable CE1 disable CE0 disable BUSMOD CPUMOD CE2 CE1 CE0 CE signal output Enable Disable Enable Disable 00FF01 D7 D6 D5 D4 D3 D2 D1 D0 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 0 0 0 0 0 0...

Page 27: ...0 LC0 1 0 0 Contrast Dark Light Display area 1 Display area 0 LCD display memory area selection LCD display control 00FF12 D7 D6 D5 D4 D3 D2 D1 D0 00FF14 D7 D6 D5 D4 D3 D2 D1 D0 PRPRT1 PST12 PST11 PST10 PRPRT0 PST02 PST01 PST00 Programmable timer 1 clock control Programmable timer 1 division ratio Programmable timer 0 clock control Programmable timer 0 division ratio 0 0 0 0 0 0 0 0 R W R W R W R ...

Page 28: ...SC1 1 00FF17 D7 D6 D5 D4 D3 D2 D1 D0 PRTF3 PRTF2 PRTF1 PRTF0 R W register Programmable timer 3 source clock selection Programmable timer 2 source clock selection Programmable timer 1 source clock selection Programmable timer 0 source clock selection Constantly 0 when being read Reserved register 0 0 0 0 0 R W R W R W R W R W 1 fOSC1 fOSC1 fOSC1 fOSC1 0 fOSC3 fOSC3 fOSC3 fOSC3 00FF18 D7 D6 D5 D4 D3...

Page 29: ...able timer 6 source clock selection Programmable timer 5 source clock selection Programmable timer 4 source clock selection Constantly 0 when being read 0 0 0 0 R W R W R W R W fOSC1 fOSC1 fOSC1 fOSC1 fOSC3 fOSC3 fOSC3 fOSC3 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 PK01 PK00 PSIF1 PSIF0 PTM1 PTM0 Constantly 0 when being read 0 0 0 R W R W R W K00 K07 interrupt priority register Serial interface interrupt pr...

Page 30: ...lock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer 1 Hz interrupt factor flag Constantly 0 when being read 00FF27 D7 D6 D5 D4 D3 D2 D1 D0 FSERR FSREC FSTRA Serial I F error interrupt factor flag Serial I F receiving interrupt factor flag Serial I F transmitting interrupt factor flag 0 R W R Generated W Reset R Not generated W No operation Constantly 0 when bei...

Page 31: ...flow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable 0 R W Interrupt enable Interrupt disable 00FF2C 00FF2E D7 D6 D5 D4 D3 D2 D1 D0 FTC7 FTU7 FTC6 FTU6 FTC5 FTU5 FTC4 FTU4 PTM7 compare match interrupt factor flag PTM7 underflow interrupt factor flag PTM6 compare match interrupt factor flag PTM6 underflow interrupt factor flag PTM5 compare match interrupt factor...

Page 32: ... D0 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 PTM0 compare data D7 MSB PTM0 compare data D6 PTM0 compare data D5 PTM0 compare data D4 PTM0 compare data D3 PTM0 compare data D2 PTM0 compare data D1 PTM0 compare data D0 LSB 0 R W High Low 00FF34 D7 D6 D5 D4 D3 D2 D1 D0 PTM07 PTM06 PTM05 PTM04 PTM03 PTM02 PTM01 PTM00 PTM0 data D7 MSB PTM0 data D6 PTM0 data D5 PTM0 data D4 PTM0 data D3 PTM0 data...

Page 33: ...No operation Internal clock On On Run Preset External clock D7 D6 D5 D4 D3 D2 D1 D0 RDR27 RDR26 RDR25 RDR24 RDR23 RDR22 RDR21 RDR20 PTM2 reload data D7 MSB PTM2 reload data D6 PTM2 reload data D5 PTM2 reload data D4 PTM2 reload data D3 PTM2 reload data D2 PTM2 reload data D1 PTM2 reload data D0 LSB 1 R W High Low 00FF3A D7 D6 D5 D4 D3 D2 D1 D0 RDR37 RDR36 RDR35 RDR34 RDR33 RDR32 RDR31 RDR30 PTM3 r...

Page 34: ...Low 00FF3F 00FF3E 00FF40 D7 D6 D5 D4 D3 D2 D1 D0 WDEN FOUT2 FOUT1 FOUT0 WDRST TMRST TMRUN Watchdog timer enable FOUT frequency selection Constantly 0 when being read 1 0 0 0 0 0 R W R W R W R W R W W W R W Enable Disable FOUT2 1 1 1 1 0 0 0 0 FOUT1 1 1 0 0 1 1 0 0 FOUT0 1 0 1 0 1 0 1 0 Frequency fOSC3 8 fOSC3 4 fOSC3 2 fOSC3 1 fOSC1 8 fOSC1 4 fOSC1 2 fOSC1 1 FOUT output control Watchdog timer rese...

Page 35: ...chronous mode 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W Serial I F framing error flag Serial I F parity error flag Serial I F overrun error flag Serial I F receive trigger status Serial I F receive enable Serial I F transmit trigger status Serial I F transmit enable Error Reset 0 Error Reset 0 Error Reset 0 Run Trigger Enable Run Trigger Enable No error No operation No error No...

Page 36: ...LK00 1 R W K07 pull up control register K06 pull up control register K05 pull up control register K04 pull up control register K03 pull up control register K02 pull up control register K01 pull up control register K00 pull up control register On Off 00FF58 D7 D6 D5 D4 D3 D2 D1 D0 CTK02H CTK01H CTK00H CTK02L CTK01L CTK00L K04 K07 port chattering eliminate setup Input level check time K00 K03 port c...

Page 37: ...data P13 I O port data P12 I O port data P11 I O port data P10 I O port data 00FF64 D7 D6 D5 D4 D3 D2 D1 D0 PULP07 PULP06 PULP05 PULP04 PULP03 PULP02 PULP01 PULP00 1 R W On Off P07 pull up control register P06 pull up control register P05 pull up control register P04 pull up control register P03 pull up control register P02 pull up control register P01 pull up control register P00 pull up control ...

Page 38: ... D7 D6 D5 D4 D3 D2 D1 D0 R17D R16D R15D R14D R13D R12D R11D R10D 1 R W High Low 00FF75 D7 D6 D5 D4 D3 D2 D1 D0 R25D R24D R23D R22D R21D R20D 00FF73 D7 D6 D5 D4 D3 D2 D1 D0 R07D R06D R05D R04D R03D R02D R01D R00D R07 output port data R06 output port data R05 output port data R04 output port data R03 output port data R02 output port data R01 output port data R00 output port data 1 R W High Low R17 o...

Page 39: ...Preset External clock D7 D6 D5 D4 D3 D2 D1 D0 RDR47 RDR46 RDR45 RDR44 RDR43 RDR42 RDR41 RDR40 PTM4 reload data D7 MSB PTM4 reload data D6 PTM4 reload data D5 PTM4 reload data D4 PTM4 reload data D3 PTM4 reload data D2 PTM4 reload data D1 PTM4 reload data D0 LSB 1 R W High Low 00FFB2 D7 D6 D5 D4 D3 D2 D1 D0 RDR57 RDR56 RDR55 RDR54 RDR53 RDR52 RDR51 RDR50 PTM5 reload data D7 MSB PTM5 reload data D6 ...

Page 40: ...lection R W register R W register PTM6 Run Stop control PTM6 preset PTM6 input clock selection 16 bit x 1 Enable 1 1 Run Preset External clock 8 bit x 2 Disable 0 0 Stop No operation Internal clock 00FFB9 D7 D6 D5 D4 D3 D2 D1 D0 PTRUN7 PSET7 CKSEL7 R W register R W register PTM7 Run Stop control PTM7 preset PTM7 input clock selection Constantly 0 when being read Reserved register 0 when being read...

Page 41: ...D3 D2 D1 D0 CDR77 CDR76 CDR75 CDR74 CDR73 CDR72 CDR71 CDR70 PTM7 compare data D7 MSB PTM7 compare data D6 PTM7 compare data D5 PTM7 compare data D4 PTM7 compare data D3 PTM7 compare data D2 PTM7 compare data D1 PTM7 compare data D0 LSB 0 R W High Low 00FFBD D7 D6 D5 D4 D3 D2 D1 D0 PTM77 PTM76 PTM75 PTM74 PTM73 PTM72 PTM71 PTM70 PTM7 data D7 MSB PTM7 data D6 PTM7 data D5 PTM7 data D4 PTM7 data D3 P...

Page 42: ...P06 P07 Output port R00 Output port R01 Output port R02 Output port R03 Output port R04 Output port R05 Output port R06 Output port R07 Output port R10 Output port R11 Output port R12 Output port R13 Output port R14 Output port R15 Output port R16 Output port R17 Output port R20 Output port R21 Output port R22 Output port R23 Output port R24 Output port R25 I O port P00 I O port P01 I O port P02 I...

Page 43: ... clock cycle WAIT states set in software are inserted between bus cycle states T3 T4 Note however that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC1 oscillation circuit see 5 4 Oscillation Circuits Consequently WAIT state settings in single chip mode are meaningless With regard to WAIT insertion timing see Section 3...

Page 44: ... R30 Expansion mode only Reserved register Expansion Maximum 1 1 1 CE2 enable CE1 enable CE0 enable Minimum 0 0 0 CE2 disable CE1 disable CE0 disable BUSMOD CPUMOD CE2 CE1 CE0 CE signal output Enable Disable Enable Disable 00FF01 D7 D6 D5 D4 D3 D2 D1 D0 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Stack pointer page address SP page allocat...

Page 45: ...ding NMI are masked until you write an optional value into address 00FF00H SPP0 SPP7 00FF01H Sets the page address of stack area In single chip mode set page address to 00H In expansion mode it can be set to any value within the range 00H 27H Since a carry and borrow from to the stack pointer SP is not reflected in register SPP the upper limit on continuous use of the stack area is 64K bytes At in...

Page 46: ...y even if you do not change the content of this address You use the initial value as is you should still be sure to perform the writing operation using the initialization routine 2 When setting stack fields including page addresses as well you should write them in the order of the register SPP 00FF01H and the stack pointer SP Example When setting the 178000H address LD EP 00H LD HL 0FF01H LD HL 17...

Page 47: ...rated at points that are regularly being processed The watchdog timer continues to operate during HALT and when HALT state is continuous for longer than the selected period the CPU starts exception processing During SLEEP the watchdog timer is stopped Note The NMI generation cycles in the watchdog timer mask option list represent maximum values A maximum minus selected optional cycle 4 seconds of ...

Page 48: ...does not count and ______ does not generate the interrupt NMI At initial reset this register is set to 1 WDRST 00FF40H D2 Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading Constantly 0 By writing 1 to WDRST the watchdog timer is reset after which it is immediately restarted Writing 0 will mean no operation Since WDRST is for writing only it ...

Page 49: ...C1 should be used to generate the operating clock and OSC3 circuit placed in a stopped state in order to reduce current consumption 5 4 2 Mask option OSC1 oscillation circuit Crystal oscillation circuit CR oscillation circuit OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit CR oscillation circuit In terms of the oscillation circuit types for OSC1 either crystal osci...

Page 50: ...t is necessary to wait for the OSC1 oscillation to stabilize before the clock can be switched The OSC3 oscillation may take several tens of msec to several seconds until it has completely stabilized The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 8 ELECTRICAL CHARACTERIST...

Page 51: ...and when the clock is switched to OSC1 CLKCHG should be set to 0 At initial reset CLKCHG is set to 1 OSC3 clock 5 4 7 Programming notes 1 When the high speed CPU operation is not necessary you should operate the peripheral circuits according to the setting outline indicate below CPU operating clock OSC1 OSC3 oscillation circuit OFF When the OSC3 clock is not necessary for some peripheral circuits ...

Page 52: ...the input port Input interrupt circuit VDD VSS Data bus Kxx KxxD Address Address Pull up control register Mask option Mask option Fig 5 5 1 1 Structure of input port Each input port terminal is directly connected via a three state buffer to the data bus Furthermore the input signal state at the instant of input port readout is read in that form as data 5 5 2 Mask option Input port pull up resistor...

Page 53: ...pull up control registers 5 5 4 Interrupt function and input comparison register All the input ports K00 K07 provide the interrupt functions The conditions for issuing an interrupt can be set by the software When the interrupt generation condition set for a terminal is met the interrupt factor flag FK00 FK07 corresponding to the terminal is set at 1 and an interrupt is generated Interrupt can be p...

Page 54: ...1x 1 1 0 0 1 1 0 0 CTK00x 1 0 1 0 1 0 1 0 Check time 4 fOSC3 2 µs 2 fOSC3 1 µs 1 fOSC3 0 5 µs 4096 fOSC1 128 ms 2048 fOSC1 64 ms 512 fOSC1 16 ms 128 fOSC1 4 ms None When OSC1 32 kHz OSC3 2 MHz Notes Be sure to disable interrupts before changing the contents of the CTK0x register Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabl...

Page 55: ...rt data K02 input port data K01 input port data K00 input port data High level input Low level input 00FF56 D7 D6 D5 D4 D3 D2 D1 D0 PULK07 PULK06 PULK05 PULK04 PULK03 PULK02 PULK01 PULK00 1 R W K07 pull up control register K06 pull up control register K05 pull up control register K04 pull up control register K03 pull up control register K02 pull up control register K01 pull up control register K00...

Page 56: ...rrupt factor flag K03 interrupt factor flag K02 interrupt factor flag K01 interrupt factor flag K00 interrupt factor flag 0 R Interrupt factor is generated W Reset R No interrupt factor is generated W No operation R W K00D K07D 00FF54H Input data of input port terminal K0x can be read out When 1 is read HIGH level When 0 is read LOW level Writing Invalid The terminal voltage of each of the input p...

Page 57: ...ter EK0x At initial reset this register is set to 0 None PK00 PK01 00FF20H D6 D7 Sets the input interrupt priority level PK00 and PK01 are the interrupt priority registers corresponding to the input interrupts Table 5 5 5 4 shows the interrupt priority level which can be set by this register Table 5 5 5 4 Interrupt priority level settings PK01 PK00 Interrupt priority level 1 1 0 0 1 0 1 0 Level 3 ...

Page 58: ... wait time for introduction of an input port In particular special attention should be paid to key scan for key matrix formation Make this wait time the amount of time or more calculated by the following expression Wait time RIN x CIN load capacitance on the board x 1 6 sec RIN Pull up resistance Max value CIN Terminal capacitance Max value 2 Be sure to disable interrupts before changing the conte...

Page 59: ...ntrol Figure 5 6 1 1 shows the basic structure of the output ports VDD VSS Data bus Rxx Address Data register Address High impedance control register Fig 5 6 1 1 Structure of output ports In expansion mode the data registers and high impedance control registers of the output ports used for bus function can be used as general purpose registers with read write capabilities This will not in any way a...

Page 60: ...omple mentary D7 D6 D5 D4 D3 D2 D1 D0 Reserved register 0 0 0 0 0 R W R W R W R W R W 1 1 1 1 High impedance 0 0 0 0 Comple mentary 00FF72 HZR33 HZR32 HZR31 HZR30 R W register R W register R W register R W register R33 high impedance control R32 high impedance control R31 high impedance control R30 high impedance control 00FF74 D7 D6 D5 D4 D3 D2 D1 D0 R17D R16D R15D R14D R13D R12D R11D R10D 1 R W ...

Page 61: ...r which correspond as shown in Table 5 6 2 1 to the various output port terminals When 1 is set to the HZRxx register the corre sponding output port terminal becomes high impedance state and when 0 is set it becomes complementary output At initial reset this register is set to 0 complementary R00D R07D 00FF73H R10D R17D 00FF74H R20D R25D 00FF75H D0 D5 R30D R33D 00FF76H D0 D3 Sets the data output f...

Page 62: ...usable as general purpose registers with read write capabilities which do not affect I O activities of the terminal The same as above the I O control register of I O port set for serial interface input terminal use is usable as general purpose register In addition to the general purpose DC output special output can be selected for the I O ports P14 P17 with the software 5 7 2 Mask option I O port ...

Page 63: ... load capacitance of the terminal It is necessary to set an appropriate wait time for introduction of an I O port Make this wait time the amount of time or more calculated by the following expression Wait time RIN x CIN load capacitance on the board x 1 6 sec RIN Pull up resistance Max value CIN Terminal capacitance Max value For unused ports select With resistor and enable pull up using the pull ...

Page 64: ...ewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 8 ELECTRICAL CHARACTERISTICS Since the FOUT signal is generated asynchronously from the register FOUTON when the signal is turned ON or OFF by the register settings a hazard of a 1 2 cycle or less is generated Figure 5 7 5 2 shows the output waveform of the FOUT s...

Page 65: ...P04 I O control register P03 I O control register P02 I O control register P01 I O control register P00 I O control register 0 R W Output Input Address Bit Name SR R W Function Comment 1 0 00FF63 D7 D6 D5 D4 D3 D2 D1 D0 P17D P16D P15D P14D P13D P12D P11D P10D P17 I O port data P16 I O port data P15 I O port data P14 I O port data P13 I O port data P12 I O port data P11 I O port data P10 I O port d...

Page 66: ...2 CKSEL2 0 when being read 0 when being read 0 0 0 0 0 0 0 R W R W R W R W R W W R W PTM2 3 8 16 bit mode selection External clock 1 noise rejecter selection PTM2 inverted clock output control PTM2 clock output control PTM2 Run Stop control PTM2 preset PTM2 input clock selection 16 bit x 1 Enable On On Run Preset External clock 8 bit x 2 Disable Off Off Stop No operation Internal clock 00FF39 D7 D...

Page 67: ...s outputs and special outputs can be used as general purpose registers that do not affect the terminal inputs outputs PULP00 PULP07 00FF64H PULP10 PULP17 00FF65H The pull up during the input mode are set with these registers When 1 is written Pull up ON When 0 is written Pull up OFF Reading Valid PULPxx is the pull up control register corresponding to each I O port in bit units When Gate direct is...

Page 68: ... which the pull up resistor is enabled from LOW level to HIGH a delay in the waveform rise time will occur depending on the time constant of the pull up resistor and the load capacitance of the terminal It is necessary to set an appropriate wait time for introduction of an I O port Make this wait time the amount of time or more calculated by the following expression Wait time RIN x CIN load capaci...

Page 69: ...ed data shift register Transmitting data shift register Serial output control circuit SIN P10 Clock control circuit READY output control circuit SCLK P12 Error detection circuit SRDY P13 Start bit detection circuit Programmable timer 1 underflow signal Interrupt request Fig 5 8 1 1 Configuration of serial interface 5 8 2 Switching of terminal functions Serial interface input output terminals SIN S...

Page 70: ... clock from the external master side serial input output device is utilized and clock synchronous 8 bit serial transfers can be performed with this serial interface as the slave _________ The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock _________ Furthermore the SRDY signal indicating the transmit receive ready status is output from the...

Page 71: ...llation start time example indicated in Chapter 8 ELECTRICAL CHARACTERISTICS At initial reset the OSC3 oscillation circuit is set to ON status Transfer rate bps 19 200 9 600 4 800 2 400 1 200 600 300 150 PST1X 00H 00H 00H 00H 00H 00H 02H 02H RDR1X 03H 07H 0FH 1FH 3FH 7FH 1FH 3FH PST1X 00H 00H 00H 00H 00H 00H 03H 03H RDR1X 04H 09H 13H 27H 4FH 9FH 09H 13H PST1X 00H 00H 00H 00H 00H 00H 01H 02H RDR1X ...

Page 72: ...erated when the transmission is completed If there is subsequent data to be transmitted it can be sent using this interrupt In addition TXTRG can be read as the status When set to 1 it indicates transmitting operation and 0 indicates transmitting stop For details on timing see the timing chart which gives the timing for each mode When not transmitting set TXEN to 0 to disable transmitting status R...

Page 73: ... MSB The SDP register should be set before writing data to TRXD0 TRXD7 SCLK LSB first Data D0 D1 D2 D3 D4 D5 D6 D7 LSB MSB SCLK MSB first Data D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Fig 5 8 6 1 Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer transmit receive control procedures and operations With respect to seria...

Page 74: ...onous _________ clock to be input from the SCLK terminal The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal When the final bit MSB when LSB first is selected or LSB when MSB first is selected is output the SOUTx terminal is maintained at that level until the next transmitting begins The transmittin...

Page 75: ... clock to be input from the SCLK terminal The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock At the point where the data of the 8th bit has been incorporated at the final 8th rising edge of the synchronous clock the content of the shift register is sent to the received data buffer and t...

Page 76: ...eceive timing for master mode d Receive timing for slave mode Fig 5 8 6 4 Timing chart clock synchronous system transmission LSB first _________ Transmit receive ready SRDY signal When this serial interface is used in the clock synchronous slave mode external clock input an _________ SRDY signal is output to indicate whether or not this serial interface can transmit receive to the master side exte...

Page 77: ...register ESIF in order to set these terminals for serial interface use _________ _________ SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchro nous mode These terminals function as I O port terminals P12 and P13 3 Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and S...

Page 78: ...ter TXEN to reset the serial interface 2 Write 1 in the transmit enable register TXEN to set into the transmitting enable status 3 Write the transmitting data into TRXD0 TRXD7 Also when 7 bit data is selected the TRXD7 data becomes invalid Data transmitting End TXEN 0 No Yes Transmit complete Set transmitting data to TRXD0 TRXD7 No Yes FSTRA 1 TXEN 0 TXTRG 1 TXEN 1 Fig 5 8 7 2 Transmit procedure i...

Page 79: ...int When an overrun error is generated the interrupt factor flag FSREC is not set to 1 and a receiving complete interrupt is not generated If with parity check has been selected a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected the error inter rupt factor flag is set to 1 When the interrupt has been enabled a...

Page 80: ...with the stop bit set at 0 the serial interface judges the synchronization to be off and a framing error is generated When this error is generated the framing error flag FER and the error interrupt factor flag FSERR are set to 1 When interrupt has been enabled an error interrupt is generated at this point The FER flag is reset to 0 by writing 1 Even when this error has been generated the received ...

Page 81: ...gisters PSIF0 and PSIF1 For details on the above mentioned interrupt control register and the operation following generation of an interrupt see 5 14 Interrupt and Standby Status Figure 5 8 8 1 shows the configuration of the serial interface interrupt circuit Transmitting complete interrupt This interrupt factor is generated at the point where the sending of the data written into the shift registe...

Page 82: ...ag FSREC is set to 1 The interrupt factor flag FSREC is reset to 0 by writing 1 The generation of this interrupt factor permits the received data to be read Also the interrupt factor flag is set to 1 when a parity error or framing error is generated The exception processing vector address is set as follows Receiving complete interrupt 00002AH Error interrupt This interrupt factor is generated at t...

Page 83: ...erial I F parity error flag Serial I F overrun error flag Serial I F receive trigger status Serial I F receive enable Serial I F transmit trigger status Serial I F transmit enable 0 when being read Only for asynchronous mode 0 0 0 0 0 0 0 R W R W R W R W R W R W R W No error No operation No error No operation No error No operation Stop No operation Disable Stop No operation Disable R W R W R W R W...

Page 84: ...o the transfer modes At initial reset ESIF is set to 0 I O port Table 5 8 9 1 b Serial interface control bits Address Bit Name SR R W Function Comment 1 0 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 PK01 PK00 PSIF1 PSIF0 PTM1 PTM0 Constantly 0 when being read 0 0 0 R W R W R W K00 K07 interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register PK01 PSIF1 1 1...

Page 85: ...omes invalid in the clock synchro nous mode At initial reset EPR is set to 0 non parity PMD 00FF48H D5 Selects odd parity even parity When 1 is written Odd parity When 0 is written Even parity Reading Valid When 1 is written to PMD odd parity is selected and even parity is selected when 0 is written The parity check and addition of a parity bit is only valid when 1 has been written to EPR When 0 h...

Page 86: ...ase of continuous transmitting wait for the transmitting complete interrupt then write the data The TRXD7 becomes invalid for the asynchronous 7 bit mode Converted serial data for which the bits set at 1 as HIGH VDD level and for which the bits set at 0 as LOW VSS level are output from the SOUT terminal During receiving Read the received data When 1 is read HIGH level When 0 is read LOW level The ...

Page 87: ...t this register is set to 0 interrupt disabled FSTRA FSREC FSERR 00FF27H D0 D1 D2 Indicates the serial interface interrupt generation status When 1 is read Interrupt factor present When 0 is read Interrupt factor not present When 1 is written Resets factor flag When 0 is written Invalid FSTRA FSREC and FSERR are interrupt factor flags that respectively correspond to the interrupts for transmitting...

Page 88: ...et the receiving complete interrupt factor flag FSREC to 0 by providing a wait time in error processing routines and similar routines When an overrun error is generated the receiving complete interrupt factor flag FSREC is not set to 1 and a receiving complete interrupt is not generated Table 5 8 10 1 Time difference between FSERR and FSREC on error generation Clock source Time difference fOSC3 n ...

Page 89: ...FTM2 and FTM1 at the falling edge of the 32 Hz 8 Hz 2 Hz and 1 Hz signals to 1 Interrupt can be prohibited by the setting the interrupt enable registers ETM32 ETM8 ETM2 and ETM1 corre sponding to each interrupt factor flag In addition a priority level of the clock timer interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority registers PTM0 and PTM1 For details on the...

Page 90: ...ctor flag FTM32 Address Interrupt enable register ETM32 Address 8 Hz falling edge Interrupt factor flag FTM8 Address Interrupt enable register ETM8 Address 2 Hz falling edge Interrupt factor flag FTM2 Address Interrupt enable register ETM2 Interrupt priority level judgement circuit Address Interrupt priority register PTM0 PTM1 Address 1 Hz falling edge Interrupt factor flag FTM1 Address Interrupt ...

Page 91: ...r data Clock timer data Clock timer data Clock timer data 0 R High Low 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 PK01 PK00 PSIF1 PSIF0 PTM1 PTM0 Constantly 0 when being read 0 0 0 R W R W R W K00 K07 interrupt priority register Serial interface interrupt priority register Clock timer interrupt priority register PK01 PSIF1 1 1 0 0 Priority level PK00 PSIF0 1 0 1 0 ...

Page 92: ...l settings At initial reset this register is set to 0 level 0 PTM1 PTM0 Interrupt priority level 1 1 0 0 1 0 1 0 Level 3 IRQ3 Level 2 IRQ2 Level 1 IRQ1 Level 0 None ETM1 ETM2 ETM8 ETM32 00FF22H D0 D3 Enables or disables the generation of an interrupt for the CPU When 1 is written Interrupt enabled When 0 is written Interrupt disabled Reading Valid The ETM1 ETM2 ETM8 and ETM32 are interrupt enable ...

Page 93: ...ter is incremented 1 The TMRUN maintains 1 for reading until the timer actually shifts to STOP status Figure 5 9 4 1 shows the timing chart of the RUN STOP control Fig 5 9 4 1 Timing chart of RUN STOP control 2 The SLP instruction is executed when the clock timer is in the RUN status TMRUN 1 The clock timer operation will become unstable when returning from SLEEP status Therefore when shifting to ...

Page 94: ... circuit Clock selection circuit Prescaler clock control circuit Clock output circuit Comparator Underflow Underflow signal INCL0 fOSC3 fOSC1 Input port K04 Clock output EXCL0 TOUT0 Underflow interrupt Compare match interrupt Compare match Timer 0 Interrupt circuit 8 bit reload data register RDR1 8 bit down counter PTM1 8 bit compare data register CDR1 Timer 1 control registers Control circuit Clo...

Page 95: ...atch Timer 6 Interrupt circuit 8 bit reload data register RDR7 8 bit down counter PTM7 8 bit compare data register CDR7 Timer 7 control registers Control circuit Clock selection circuit Prescaler clock control circuit Comparator Underflow INCL7 fOSC3 fOSC1 Input port K07 EXCL3 Underflow interrupt Compare match interrupt Compare match Timer 7 Interrupt circuit 5 10 2 Operation mode Timers 0 and 1 T...

Page 96: ...eing read 0 0 0 0 0 R W R W R W W R W 0 Off Stop No operation Internal clock 1 On Run Preset External clock Table 5 10 2 1 b Control registers in 16 bit mode example of Timers 0 and 1 SR R W Address Bit Name Function Comment 1 0 D7 D6 D5 D4 D3 D2 D1 D0 00FF30 MODE16_A PTNREN_A PTOUT0 PTRUN0 PSET0 CKSEL0 0 when being read Reserved register 0 when being read 0 0 0 0 0 0 0 R W R W R W R W R W W R W P...

Page 97: ...n be selected from either the internal clock or external clock by the input clock selection register CKSEL pro vided for each timer The internal clock is an output of the prescaler The external clock is used for the event counter function A signal from the input port is used as the count clock Table 5 10 3 1 shows the input clock selection register and input clock of each timer Table 5 10 3 1 Inpu...

Page 98: ...controlled individually by the PTRUNx register In the 16 bit mode the PTRUN L register controls a pair of timers as a 16 bit timer In this case control of the PTRUN H register is invalid The buffers PTMx is attached to the counter and reading is possible in optional timing When the counter agrees with the data set in the compare data register during down counting the timer generates a compare matc...

Page 99: ...er 1 underflow interrupt 00001AH Timer 1 compare match interrupt 00001CH Timer 2 underflow interrupt 00001EH Timer 2 compare match interrupt 000020H Timer 3 underflow interrupt 000022H Timer 3 compare match interrupt 000024H Timer 4 underflow interrupt 00003CH Timer 4 compare match interrupt 00003EH Timer 5 underflow interrupt 000040H Timer 5 compare match interrupt 000042H Timer 6 underflow inter...

Page 100: ...enable register ETC6 Interrupt priority level judgment circuit Address Interrupt priority register PPT6 PPT7 Timer 6 Timer 1 Timer 0 interrupt request Address Underflow Interrupt factor flag FTU0 Address Interrupt enable register ETU0 Timer 1 interrupt request Address Compare match Interrupt factor flag FTC0 Address Interrupt enable register ETC0 Interrupt priority level judgment circuit Address I...

Page 101: ...trol register PTOUTx of _________ each timer and the TOUT output can be controlled using the inverted clock output control register RPTOUTx of Timer 2 or Timer 3 When PTOUTx RPTOUTx is set to 1 the TOUTx ___________ TOUTx signal is output from the corresponding port terminal when 0 is set the port is set for DC output When PTOUTx RPTOUTx is 1 settings of the I O control register IOC14 IOC15 IOC17 ...

Page 102: ...FH 1FH 3FH 7FH 1FH 3FH PST1X 00H 00H 00H 00H 00H 00H 03H 03H RDR1X 04H 09H 13H 27H 4FH 9FH 09H 13H PST1X 00H 00H 00H 00H 00H 00H 01H 02H RDR1X 05H 0BH 17H 2FH 5FH BFH BFH 5FH fOSC3 2 4756 MHz fOSC3 3 0720 MHz fOSC3 3 6864 MHz OSC3 oscillation frequency Programmable timer settings Since the underflow signal only is used as the clock source the CDR1X register value does not affect the transfer rates...

Page 103: ...ogrammable timer 3 division ratio Programmable timer 2 clock control Programmable timer 2 division ratio 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W On On Off Off PST32 1 1 1 1 0 0 0 0 PST31 1 1 0 0 1 1 0 0 PST30 1 0 1 0 1 0 1 0 OSC3 fOSC3 4096 fOSC3 1024 fOSC3 256 fOSC3 64 fOSC3 32 fOSC3 8 fOSC3 2 fOSC3 1 OSC1 fOSC1 128 fOSC1 64 fOSC1 32 fOSC1 16 fOSC1 8 fOSC1 4 fOSC1 2 fOSC1 1 PST22 1 1 1 1 ...

Page 104: ... 3 source clock selection Programmable timer 2 source clock selection Programmable timer 1 source clock selection Programmable timer 0 source clock selection Constantly 0 when being read Reserved register 0 0 0 0 0 R W R W R W R W R W 1 fOSC1 fOSC1 fOSC1 fOSC1 0 fOSC3 fOSC3 fOSC3 fOSC3 00FF1B D7 D6 D5 D4 D3 D2 D1 D0 PRTF7 PRTF6 PRTF5 PRTF4 Programmable timer 7 source clock selection Programmable t...

Page 105: ...enable PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable 0 R W Interrupt enable Interrupt disable 00FF2C 00FF2E D7 D6 D5 D4 D3 D2 D1 D0 FTC7 FTU7 FTC6 FTU6 FTC5 FTU5 FTC4 FTU4 PTM7 compare match interrupt factor flag PTM7 underflow interrupt factor flag PTM6 compare match interrupt factor flag PTM6 underflow interrupt factor flag PTM5 compare match...

Page 106: ...2 D1 D0 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 PTM0 compare data D7 MSB PTM0 compare data D6 PTM0 compare data D5 PTM0 compare data D4 PTM0 compare data D3 PTM0 compare data D2 PTM0 compare data D1 PTM0 compare data D0 LSB 0 R W High Low 00FF34 D7 D6 D5 D4 D3 D2 D1 D0 PTM07 PTM06 PTM05 PTM04 PTM03 PTM02 PTM01 PTM00 PTM0 data D7 MSB PTM0 data D6 PTM0 data D5 PTM0 data D4 PTM0 data D3 PTM0 ...

Page 107: ...top No operation Internal clock On On Run Preset External clock D7 D6 D5 D4 D3 D2 D1 D0 RDR27 RDR26 RDR25 RDR24 RDR23 RDR22 RDR21 RDR20 PTM2 reload data D7 MSB PTM2 reload data D6 PTM2 reload data D5 PTM2 reload data D4 PTM2 reload data D3 PTM2 reload data D2 PTM2 reload data D1 PTM2 reload data D0 LSB 1 R W High Low 00FF3A D7 D6 D5 D4 D3 D2 D1 D0 RDR37 RDR36 RDR35 RDR34 RDR33 RDR32 RDR31 RDR30 PT...

Page 108: ...er selection R W register R W register PTM4 Run Stop control PTM4 preset PTM4 input clock selection 16 bit x 1 Enable 1 1 Run Preset External clock 8 bit x 2 Disable 0 0 Stop No operation Internal clock 00FFB1 D7 D6 D5 D4 D3 D2 D1 D0 PTRUN5 PSET5 CKSEL5 R W register R W register PTM5 Run Stop control PTM5 preset PTM5 input clock selection Constantly 0 when being read Reserved register 0 when being...

Page 109: ...D6 PTM5 data D5 PTM5 data D4 PTM5 data D3 PTM5 data D2 PTM5 data D1 PTM5 data D0 LSB 1 R High Low 00FFB7 D7 D6 D5 D4 D3 D2 D1 D0 PTM47 PTM46 PTM45 PTM44 PTM43 PTM42 PTM41 PTM40 PTM4 data D7 MSB PTM4 data D6 PTM4 data D5 PTM4 data D4 PTM4 data D3 PTM4 data D2 PTM4 data D1 PTM4 data D0 LSB 1 R High Low 00FFB6 D7 D6 D5 D4 D3 D2 D1 D0 00FFB8 MODE16_D PTNREN_D PTRUN6 PSET6 CKSEL6 0 when being read Rese...

Page 110: ...D2 D1 D0 CDR67 CDR66 CDR65 CDR64 CDR63 CDR62 CDR61 CDR60 PTM6 compare data D7 MSB PTM6 compare data D6 PTM6 compare data D5 PTM6 compare data D4 PTM6 compare data D3 PTM6 compare data D2 PTM6 compare data D1 PTM6 compare data D0 LSB 0 R W High Low 00FFBC D7 D6 D5 D4 D3 D2 D1 D0 CDR77 CDR76 CDR75 CDR74 CDR73 CDR72 CDR71 CDR70 PTM7 compare data D7 MSB PTM7 compare data D6 PTM7 compare data D5 PTM7 c...

Page 111: ...Selects the input clock for each timer When 1 is written External clock When 0 is written Internal clock Reading Valid The clock to be input to each timer is selected from either the external clock input signal of input port or the internal clock prescaler output clock When 0 is written to the CKSELx register the internal clock prescaler output INCLx is selected as the input clock for Timer x When...

Page 112: ...ta set in this register with the corresponding counter data and outputs the compare match signals when they are the same The compare match signal controls the interrupt and the TOUT output waveform This register can also be read At initial reset this register is set to 00H PTM00 PTM07 00FF36H PTM10 PTM17 00FF37H PTM20 PTM27 00FF3EH PTM30 PTM37 00FF3FH PTM40 PTM47 00FFB6H PTM50 PTM57 00FFB7H PTM60 ...

Page 113: ...At initial reset this register is set to 0 DC output Note If PTOUT0 and PTOUT1 are set to 1 at the same time PTOUT1 is effective Similarly if PTOUT2 and PTOUT3 are set to 1 PTOUT3 is effective Furthermore if the programmable timer is set in 16 bit mode the TOUT0 and TOUT2 signals cannot be output RPTOUT2 00FF38H D4 RPTOUT3 00FF39H D4 _________ Controls the output of the TOUT signal When 1 is writt...

Page 114: ...F2EH D2 FTU6 00FF2EH D4 FTU7 00FF2EH D6 Indicates the generation of underflow interrupt factor When 1 is read Int factor has generated When 0 is read Int factor has not generated When 1 is written Factor flag is reset When 0 is written Invalid FTUx is the interrupt factor flag corresponding to interrupt of Timer x and is set to 1 due to the counter underflow At this point if the corresponding inte...

Page 115: ...PTRUNx RD Input clock Fig 5 10 10 1 Timing chart at RUN STOP control 2 When the SLP instruction is executed while the programmable timer is running PTRUNx 1 the timer stops counting during SLEEP status When SLEEP status is canceled the timer starts counting However the operation becomes unstable immediately after SLEEP status is canceled Therefore when shifting to SLEEP status stop the 16 bit prog...

Page 116: ...ystem voltage regulator power select register VDSEL for this switching When VDSEL is set to 0 VDD is selected and when VDSEL is set to 1 VD2 is selected The VD2 voltage is generated by approximately doubling the VDD voltage in the power voltage booster circuit When using VD2 write 1 to the power voltage booster circuit ON OFF control register DBON to turn the power voltage booster circuit on This ...

Page 117: ...number of displaying dots When 1 32 duty is selected an LCD panel with 126 segments 32 commons maximum 4 032 dots can be driven When 1 16 duty is selected an LCD panel with 126 segments 16 commons maximum 2 016 dots can be driven The COM16 COM31 terminals become invalid in that they always output an OFF signal When 1 8 duty is selected an LCD panel with 126 segments 8 commons maximum 1 008 dots ca...

Page 118: ...2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEG0 1 2 3 4 VC5 VC4 VC3 VC2 VC1 V GND SS VC5 VC4 VC3 VC2 VC1 V GND SS VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS 32 Hz when fOSC1 32 768 kHz is selected as the source clock FRMCS 0 Fig 5 11 4 1 Drive waveform for 1 32 duty ...

Page 119: ...COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 VDD VSS VC5 VC4 VC3 VC2 VC1 V GND SS VC5 VC4 VC3 VC2 VC1 V GND SS VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS 32 Hz when fOSC1 32 768 kHz is selected as the source clock FRMCS 0 Fig 5 11 4 2 Drive waveform for 1 16 duty ...

Page 120: ...2 1 0 FR COM0 COM1 COM2 SEG0 SEG1 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 V GND SS VC5 VC4 VC3 VC2 VC1 V GND SS COM0 SEG0 COM0 SEG1 when fOSC1 32 768 kHz is selected as the source clock FRMCS 0 4 6 4 6 5 5 VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 64 Hz Fig 5 11 4 3 Drive waveform for 1 8 duty ...

Page 121: ...one by the dot font selection register DTFNT when 0 is written to DTFNT 16 16 5 8 dots is selected and when 1 is written 12 12 dots is selected The memory allocation for the SEG terminals can be reversed using the SEG assignment reverse register SEGREV Table 5 11 5 1 Selecting SEG assignment SEGREV 1 0 Assignment Reverse Normal Fx00H SEG125 SEG0 Fx70H SEG0 SEG125 The correspondence between the dis...

Page 122: ...3 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Display area Display area Display area 0 15 125 112 SEG normal 1 SEG reverse 2 16 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2 SEGREV 1 Address ...

Page 123: ... 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2 SEGREV 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Display area Display area SEG normal 1 SEG reverse 2 Addres...

Page 124: ...6 7 8 9 10 11 12 13 14 15 Display area 0 when DSPAR is set to 0 Display area 1 when DSPAR is set to 1 Display area 1 when DSPAR is set to 1 0 15 125 112 16 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2...

Page 125: ...12 16 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2 SEGREV 1 Display area 0 when DSPAR is set to 0 Display area 1 when DSPAR is set to 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 ...

Page 126: ...3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Display area 1 when DSPAR is set to 1 0 15 125 112 16 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2 SEGREV 1 SEG normal 1 SEG reverse 2 Address Data bit Fi...

Page 127: ... D4 D5 D6 D7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Display area 1 when DSPAR is set to 1 0 15 125 112 16 31 111 96 32 47 95 80 48 63 79 64 64 79 63 48 80 95 47 32 96 111 31 16 112 125 15 0 0 0 F COM 1 0 F 2 0 F 3 0 F 4 0 F 5 0 F 6 0 F 7 0 D 00F800H 00F87DH 00F900H 00F97DH 00FA00H 00FA7DH 00FB00H 00FB7DH 00FC00H 00FC7DH 00FD00H 00FD7DH 1 SEGREV 0 2 SEGREV 1 SEG normal 1 SEG reverse 2 Address Data bit Fig...

Page 128: ...hen all the dots are on and is set to dynamic drive when they are off this function can be used as follows 1 Since all dots on is binary output VC5 and VSS with static drive the common segment termi nal can be used as a monitor terminal for the OSC1 oscillation frequency adjustment 2 Since all dots off is dynamic drive you can brink the entire LCD display without changing display memory data Selec...

Page 129: ...ormal 0 0 0 16 16 5 8 00FF11 D7 D6 D5 D4 D3 D2 D1 D0 FRMCS DSPAR LCDC1 LCDC0 LC3 LC2 LC1 LC0 LCD frame signal source clock selection LCD contrast adjustment These bits are reset to 0 0 when SLP instruction is executed 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W PTM fOSC1 LCDC1 1 1 0 0 LCDC0 1 0 1 0 LCD display All LCDs lit All LCDs out Normal display Drive off LDUTY1 1 1 0 0 LDUTY0 1 0 1 0 Dut...

Page 130: ... is selected The correspondence between the display memory bits set according to the display area and the common segment terminals are shown in Figures 5 11 5 1 5 11 5 5 At initial reset DSPAR is set to 0 display area 0 LCDC0 LCDC1 00FF11H D4 D5 Controls the LCD display Table 5 11 7 4 LCD display control LCDC1 LCDC0 LCD display 1 1 0 0 1 0 1 0 All LCDs lit Static All LCDs out Dynamic Normal displa...

Page 131: ... 1 is written VD2 When 0 is written VDD Reading Valid When 1 is written to VDSEL the LCD system voltage regulator is driven with VD2 generated by the power voltage booster Before this setting is made it is necessary to write 1 to DBON to turn on the power voltage booster Furthermore do not switch the power voltage to VD2 for at least 1 msec after the power voltage booster is turned on to allow VD2...

Page 132: ...Table 5 12 2 1 by the SVDS3 SVDS0 registers Table 5 12 2 1 Criteria voltage setting SVDS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Criteria voltage V 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 05 2 0 1 95 1 9 1 85 1 8 SVDS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SVDS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SVDS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 When the SVDON register is set to 1 source voltage detection by the SVD circuit is execute...

Page 133: ...OFF Reading Valid When the SVDON register is set to 1 a supply voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the result is loaded to the SVDDT latch To obtain a stable detection result the SVD circuit must be ON for at least 500 µsec At initial reset this register is set to 0 SVDDT 00FF12H D5 This is the result of supply voltage detection When 0 is read Supply vol...

Page 134: ... R W R W R W R W On Reverse 1 1 1 12 12 Off Normal 0 0 0 16 16 5 8 LDUTY1 1 1 0 0 LDUTY0 1 0 1 0 Duty Not allowed 1 16 1 32 1 8 HLMOD 00FF10H D7 Controls the heavy load protection mode When 1 is written Heavy load protection ON When 0 is written Heavy load protection OFF Reading Valid The device enters the heavy load protection mode by writing 1 to HLMOD and returns to the normal mode by writing 0...

Page 135: ...from the input port The CPU reactivates after waiting 128 fOSC1 or 512 fOSC3 seconds of oscillation stabilization time the oscillation stabilization time varies depending on the operating clock being used when the SLP instruction is executed At this time the CPU restarts program execution from an exception processing routine input interrupt routine Note The oscillation becomes unstable for a while...

Page 136: ... K05 FK06 EK06 K06 FK07 EK07 K07 Input port PTM0 PTM1 PSIF0 PSIF1 PK00 PK01 PPT0 PPT1 Interrupt vector address generation circuit NMI IRQ3 IRQ2 IRQ1 Data bus Vector address FTU2 ETU2 Underflow FTC2 ETC2 Compare match Program mable timer 2 FTU3 ETU3 Underflow FTC3 ETC3 Compare match Program mable timer 3 PPT2 PPT3 FTU4 ETU4 Underflow FTC4 ETC4 Compare match Program mable timer 4 FTU5 ETU5 Underflow...

Page 137: ...falling edge or rising edge instruction at KCP01 K00 input of falling edge or rising edge instruction at KCP00 Programmable timer 0 underflow Programmable timer 0 compare match Programmable timer 1 underflow Programmable timer 1 compare match Programmable timer 2 underflow Programmable timer 2 compare match Programmable timer 3 underflow Programmable timer 3 compare match Programmable timer 4 unde...

Page 138: ...h Timer 6 underflow Timer 6 compare match Timer 7 underflow Timer 7 compare match Serial interface receiving error Serial interface receiving completion Serial interface transmitting completion Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz Clock timer 1 Hz Interrupt enable register FK07 FK06 FK05 FK04 FK03 FK02 FK01 FK00 FTU0 FTC0 FTU1 FTC1 FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 F...

Page 139: ...o level 0 Furthermore the priority levels in each system have been previously decided and they cannot be changed The CPU can mask each interrupt by setting the interrupt flags I0 and I1 The relation between the interrupt priority level of each system and interrupt flags is shown in Table 5 14 4 3 and the CPU accepts only interrupts above the level indicated by the interrupt flags The NMI watchdog ...

Page 140: ...pondence Vector address 000000H 000002H 000004H 000006H 000008H 00000AH 00000CH 00000EH 000010H 000012H 000014H 000016H 000018H 00001AH 00001CH 00001EH 000020H 000022H 000024H 000026H 000028H 00002AH 00002CH 00002EH 000030H 000032H 000034H 000036H 000038H 00003AH 00003CH 00003EH 000040H 000042H 000044H 000046H 000048H 00004AH 00004CH 00004EH 0000FEH Priority High Low No priority rating Exception p...

Page 141: ...K00 PSIF0 1 0 1 0 Level 3 Level 2 Level 1 Level 0 Level 3 Level 2 Level 1 Level 0 0 0 R W R W PTM1 1 1 0 0 Priority level PTM0 1 0 1 0 Level 3 Level 2 Level 1 Level 0 00FF2A D7 D6 D5 D4 D3 D2 D1 D0 PPT7 PPT6 PPT5 PPT4 Constantly 0 when being read 0 0 R W R W PPT7 PPT5 1 1 0 0 PPT6 PPT4 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 ETM32 ETM8 ETM2 ETM1 Clock ...

Page 142: ...le PTM6 compare match interrupt enable PTM6 underflow interrupt enable PTM5 compare match interrupt enable PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable 0 R W Interrupt enable Interrupt disable 00FF2C 00FF26 D7 D6 D5 D4 D3 D2 D1 D0 FTM32 FTM8 FTM2 FTM1 Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 ...

Page 143: ...e described within the common area 000000H 007FFFH 4 Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred when fOSC1 is 32 768 kHz Table 5 14 6 1 c Interrupt control bits SR R W Address Bit Name Function Comment 1 0 00FF29 D7 D6 D5 D4 D3 D2 D1 D0 FTC3 FTU3 FTC2 FTU2 FTC1 FTU1 FTC0 FTU0 PTM3 compare match interrupt factor flag PTM3 underflow interrupt factor flag PTM2 co...

Page 144: ...ned You should refer to these when programming See Chapter 8 ELECTRICAL CHARACTERIS TICS for the current consumption Refer to Programming notes in each peripheral section for precautions of each peripheral circuit Table 6 1 1 Circuit systems and control registers Circuit type CPU Oscillation circuit Power voltage booster LCD controller SVD circuit Heavy lord protection Status at time of initial re...

Page 145: ...en the built in pull up resistor of the RESET terminal is used take into consideration dispersion of the resistance for setting the constant In order to prevent any occurrences of unneces sary resetting caused by noise during operating components such as capacitors and resistors should be connected to the RESET terminal in the shortest line Power Supply Circuit Sudden power supply variation due to...

Page 146: ...to malfunction When developing products which use this IC consider the following precautions to prevent malfunctions caused by visible radiations 1 Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use 2 The inspection process of the product needs an environment that shields the IC from visible radiation 3 As well as the face of the IC shi...

Page 147: ...32 768 kHz CI Max 35 kΩ 0 25 pF 1 5 MΩ 4 MHz 4 MHz 1 MΩ 15 pF Crystal oscillation 30 pF Ceramic oscillation 15 pF Crystal oscillation 30 pF Ceramic oscillation 40 kΩ Recommended values for external parts Symbol C1 C2 C3 C4 C5 C6 C7 C9 C10 C11 CP Cres Name Capacitor between VSS and VD1 Capacitor between VSS and VC1 Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between VSS an...

Page 148: ...tic package VSS 0 V 8 2 Recommended Operating Conditions Item Symbol Min Typ Max Unit Condition Operating power voltage Operating frequency Capacitor between VD1 and VSS Capacitor between VC1 and VSS Capacitor between VC2 and VSS Capacitor between VC3 and VSS Capacitor between VC4 and VSS Capacitor between VC5 and VSS Capacitor between CA and CB Capacitor between CA and CC Capacitor between CD and...

Page 149: ...utput current VIH VIL VT1 VT1 VT2 VT2 IOH IOL ILI ILO RIN CIN ISEGH ISEGL 0 8VDD 0 0 5VDD 0 1VDD 0 5VDD 0 1VDD 0 5 1 1 100 5 VDD 0 2VDD 0 9VDD 0 5VDD 0 9VDD 0 5VDD 0 5 1 1 500 15 5 V V V V V V mA mA µA µA kΩ pF µA µA Kxx Pxx Kxx Pxx RESET MCU MPU RESET MCU MPU Kxx Kxx Pxx Rxx VOH 0 9 VDD Pxx Rxx VOL 0 1 VDD Kxx Pxx RESET MCU MPU Pxx Rxx Kxx Pxx RESET MCU MPU Kxx Pxx VIN 0 V f 1 MHz Ta 25 C SEGxx C...

Page 150: ... 7H LCX 8H LCX 9H LCX AH LCX BH LCX CH LCX DH LCX EH LCX FH Item Symbol Min Typ Max Unit Condition Note 1 2 3 4 5 Unless otherwise specified VDD 1 8 to 3 6 V VSS 0 V Ta 25 C C1 C11 0 1 µF When a checker pattern is displayed No panel load Connects 1 MΩ load resistor between VSS and VC1 Connects 1 MΩ load resistor between VSS and VC2 Connects 1 MΩ load resistor between VSS and VC3 Connects 1 MΩ load...

Page 151: ...l on LCx FH fOSC1 32 768kHz VDD 2 5 to 3 6V LCDCx All on LCx FH fOSC1 32 768kHz HLMOD H LCDCx All on LCx FH fOSC1 32 768kHz DBON H VDD 1 8 to 2 5V LCDCx All on LCx FH fOSC1 32 768kHz DBON H VDD 1 8 to 2 5V HLMOD H SVDON ON Note 1 2 3 4 5 VDD 1 8 to 3 6 V VSS 0 V Ta 25 C C1 C11 0 1 µF No panel load Unless otherwise specified Note 1 2 3 4 5 This value is added to the current consumption during execu...

Page 152: ...g operation with OSC3 clock fOSC1 fOSC3 tcy tcy 30 0 03 10 20 30 40 50 60 0 24 0 49 0 73 0 98 1 22 1 46 32 768 61 122 183 244 305 366 200 8 2 67 133 200 267 333 400 66 7 133 3 200 0 266 7 333 3 400 0 kHz MHz µs µs µs µs µs µs µs µs µs µs µs µs VDD 1 8 to 3 6 V 1 cycle instruction 2 cycle instruction 3 cycle instruction 4 cycle instruction 5 cycle instruction 6 cycle instruction 1 cycle instruction...

Page 153: ... Address set up time in write cycle Address hold time in write cycle Write signal pulse width Data output set up time in write cycle Data output hold time in write cycle twas twah twp twds twdh ns ns ns ns ns Note 1 1 Note 1 Condition VDD 1 8 to 3 6 V VSS 0 V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VIH2 1 6 V VIL2 0 6 V VOH 0 8VDD VOL 0 2VDD CL 100 pF load capacitance Substitute the number of states for w...

Page 154: ...1 tsa2 s s 1 2 Note 1 2 Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating Time as far as AC is excluded Erroneous start bit detection range time is a logical range to detect whether a LOW level start bit has been input again after a start bit has been detected and the internal sampling clock has started When a HIGH level is...

Page 155: ...vh tevl tckr tckf µs µs µs s s s µs µs µs ns ns Note 2 1 1 64 fOSC1 32 fOSC1 32 fOSC1 2 1 1 25 25 Cycle time H pulse width L pulse width Cycle time H pulse width L pulse width Cycle time H pulse width L pulse width Condition VDD 1 8 to 3 6 V VSS 0 V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD SCLK EXCL VIH1 tsccy tsch VIL1 tckf tckr tscl VIH1 tevcy tevh VIL1 tckf tckr tevl ___________ RESET input clock Symbol...

Page 156: ...xternal capacitor Symbol Min Typ Max Unit Operating power voltage RESET input time Vsr tpsr V ms Note 1 8 10 Item Condition VDD 1 8 to 3 6 V VSS 0 V Ta 25 C VDD RESET tpsr Vsr 0 5VDD 0 1VDD Power ON 1 Because the potential of the RESET terminal not reached VDD level or higher VDD RESET VSS 1 ...

Page 157: ...8 to 3 6 V VSS 0 V Ta 25 C Crystal oscillator Q12C2000 Ri 30 kΩ Typ CG1 25 pF CD1 Built in Q12C2000 Made by Seiko Epson corporation OSC1 CR Min Typ Max tsta f IC 25 100 25 µs RCR constant Oscillation start time Frequency IC deviation Item Symbol Unit Condition Note Unless otherwise specified VDD 1 8 to 3 6 V VSS 0 V Ta 25 C OSC3 Crystal Min Typ Max Oscillation start time tsta 10 ms 1 Item Symbol U...

Page 158: ...ue High level output current voltage characteristic Ta 70 C Max value 0 0 0 3 6 9 12 15 0 2 0 4 0 6 0 8 1 0 VDD VOH V VDD 1 8 V VDD 2 4 V VDD 3 6 V I OH mA Low level output current voltage characteristic Ta 70 C Min value 0 0 15 12 9 6 3 0 0 1 0 2 0 3 0 4 0 5 0 6 VOL V VDD 1 8 V VDD 3 6 V I OL mA VDD 2 4 V ...

Page 159: ...resistor between VSS and VC5 no panel load Ta 25 C Typ value 1 5 2 0 2 5 3 0 3 5 4 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx FH LCx 0H V C5 V LCD drive voltage supply voltage characteristic when the power voltage booster is used Connects 1 MΩ load resistor between VSS and VC5 no panel load Ta 25 C Typ value 1 5 1 8 2 1 2 4 2 7 3 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx FH LCx 0H V C5 V ...

Page 160: ...emperature characteristic Typ value 50 1 05VC5 1 04VC5 1 03VC5 1 02VC5 1 01VC5 1 00VC5 0 99VC5 0 98VC5 0 97VC5 0 96VC5 0 95VC5 25 0 25 50 75 100 Ta C V C5 V LCD drive voltage load characteristic Ta 25 C Typ value LCx 8H 0 5 30 5 25 5 20 5 15 5 10 5 05 5 00 4 95 4 90 4 8 12 16 20 IVC5 µA V C5 V ...

Page 161: ... 153 8 ELECTRICAL CHARACTERISTICS SVD voltage ambient temperature characteristic Typ value SVDSx FH 50 1 05VSVD 1 04VSVD 1 03VSVD 1 02VSVD 1 01VSVD 1 00VSVD 0 99VSVD 0 98VSVD 0 97VSVD 0 96VSVD 0 95VSVD 25 0 25 50 75 100 Ta C V SVD V ...

Page 162: ...ure characteristic During operation with OSC1 Crystal oscillation fOSC1 32 768 kHz Typ value 50 8 6 4 2 0 25 0 25 50 75 100 Ta C I HALT1 µA In HALT status current consumption resistor characteristic During operation with OSC1 CR oscillation Ta 25 C 100 60 50 40 30 20 10 0 1000 10000 RCR1 kΩ I HALT2 µA Max Typ ...

Page 163: ...haracteristic During operation with OSC1 Crystal oscillation fOSC1 32 768 kHz Typ value 50 16 12 8 4 0 25 0 25 50 75 100 Ta C I EXE1 µA In executed status current consumption resistor characteristic During operation with OSC1 CR oscillation Ta 25 C 100 160 140 120 100 80 60 40 20 0 1000 10000 RCR1 kΩ I EXE2 µA Max Typ ...

Page 164: ... with OSC3 Crystal oscillation Ceramic oscillation Ta 25 C 0 0 4000 3500 3000 2500 2000 1500 1000 500 0 2 0 4 0 6 0 8 0 10 0 fOSC3 MHz Max Typ I EXE3 µA In executed status current consumption resistor characteristic During operation with OSC3 CR oscillation Ta 25 C 10 1800 1600 1400 1200 1000 800 600 400 200 0 100 1000 RCR3 kΩ I EXE4 µA Max Typ ...

Page 165: ...cillation frequency resistor characteristic OSC1 CR oscillation Ta 25 C Typ value 100 1000 100 10 1000 10000 RCR1 kΩ f OSC1 kHz Oscillation frequency temperature characteristic OSC1 CR oscillation Typ value RCR1 1500 kΩ 50 1000 100 10 25 25 50 0 75 100 Ta C f OSC1 kHz ...

Page 166: ...llation frequency resistor characteristic OSC3 CR oscillation Ta 25 C Typ value 10 10000 1000 100 10 100 1000 RCR3 kΩ f OSC3 kHz Oscillation frequency temperature characteristic OSC3 CR oscillation Typ value RCR3 40 kΩ 50 10000 1000 100 25 25 50 0 75 100 Ta C f OSC3 kHz ...

Page 167: ...ICAL MANUAL EPSON 159 9 PACKAGE 9 PACKAGE 9 1 Plastic Package QFP22 256pin Unit mm 129 192 65 128 INDEX 64 1 256 193 28 0 1 30 0 4 28 0 1 30 0 4 0 16 0 4 0 05 0 03 1 4 0 1 0 1 1 7 max 0 5 0 2 0 10 0 125 1 0 05 0 025 ...

Page 168: ...EG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 N C N C N C N C N C VSS SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 Pin No Pin name 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239...

Page 169: ... Y X 0 0 6 7 mm 120 125 130 135 140 145 150 155 160 165 170 175 Die No 180 185 190 195 200 205 210 215 220 225 230 235 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 115 110 105 100 95 90 80 85 Chip thickness 400 µm Pad opening 90 µm Pad 119 is used for the IC shipment test so you should not bond it ...

Page 170: ...0 231 232 233 234 235 236 Name VSS SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 VD2 CG CF CE CD CC CB CA VC5 VC4 VC3 VC2 VC1 X 3 232 3 232 3 232 3 23...

Page 171: ...1C88000P1 Refer to the S5U1C88000P Manual for how to download circuit data into the S1C88 Family Peripheral Circuit Board S5U1C88000P1 and common specifications of the board For details on ICE functions and how to operate the debugger refer to the separately prepared manuals A 1 Names and Functions of Each Part The following explains the names and functions of each part of the S5U1C88000P1 S5U1C88...

Page 172: ...cillation frequency 9 RESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE 10 LED 1 MPU MCU Indicates the MPU or MCU mode Lit MPU mode Not lit MCU mode 11 LED 2 BUSMOD LED 3 CPUMOD Indicates the bus and CPU modes BUSMOD CPUMOD register settings Table A 1 2 Bus and CPU modes Lit Lit Not lit Not lit Expansion Single chip Bus mode BUSMOD Maximum...

Page 173: ...llation when adjusting the oscillation frequency 26 I O 1 I O 2 I O 3 I O 4 connectors These are the connectors for connecting the I O and LCD The I O cables 80 pin 40 pin 2 flat type 100 pin 50 pin 2 flat type 40 pin 20 pin 2 flat type are used to connect to the target system A 2 Precautions Take the following precautions when using the S5U1C88000P1 S5U1C88649P2 A 2 1 Precaution for operation 1 T...

Page 174: ... Pay attention to the output drive capability and output voltage of the LCD terminals SEG COM since they are different from those of the actual IC The system and the software should be designed in order to adjust the LCD contrast The S5U1C88000P1 board allows switching of the LCD drive voltage with its switch on the back side Refer to Section A 1 Names and Functions of Each Part When the LCDC0 and...

Page 175: ...s board can operate with the OSC3 circuit Because the logic level of the oscillation circuit is high the timing at which the oscillation starts on this board differs from that of theactual IC Access to undefined address space If any undefined space in the S1C88650 s internal ROM RAM or I O is accessed for data read or write operations the read written value is indeterminate Additionally it is impo...

Page 176: ...n circuit 4 9152 MHz When CR oscillation is selected the oscillation frequency can be adjusted using the controls on the front panel OSC1H and OSC1L for adjusting OSC1 OSC3H and OSC3L for adjusting OSC3 Use a frequency counter or other equipment to be connected to the OSC1 CR oscillation frequency monitor pin pin 18 on the monitor connector or OSC3 CR oscillation frequency monitor pin pin 19 for m...

Page 177: ... N C N C N C N C N C COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 40 pin CN1 1 40 pin CN1 2 Table A 3 2 I O 2 connector No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin name VDD 3 3 V VDD 3 3 V VSS VSS RESET MCU MPU OSC1EX OSC3EX N C N C N C N C N C SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 ...

Page 178: ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG11...

Page 179: ...100 170L 1 Cable connector 50 pin Connector 3M 7950 B500SC 2 Strain relief 3M 3448 7950 2 Cable 50 pin flat cable 1 Interface CMOS interface 3 3 V Length Approx 40 cm I O cable 40 pin 20 pin x 2 S5U1C88649P2 connector 40 pin KEL 8830E 040 170L Cable connector 40 pin KEL 8822E 040 170L 1 Cable connector 20 pin Connector 3M 7920 B500SC 2 Strain relief 3M 3448 7920 2 Cable 20 pin flat cable 1 Interfa...

Page 180: ...ge also contains a sample program that runs on the S1C88 Family microcomputer to display this font data on an LCD an application note for the sample program and a bitmap utility that can be used to create custom font data The kanji font data is supplied in an object file format assembler output file identified by the extension obj to enable it to be embedded in the S1C88 Family microcomputer progr...

Page 181: ...ils num 64 68 E 08190 Sant Cugat del Vallès SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 Fax 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 7F High Tech Bldg 900 Y...

Page 182: ...EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http www epsondevice com Technical Manual S1C88650 Issue January 2004 Printed in Japan A L Document code 404824700 ...

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