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EPSON

S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

The ESIF is the serial interface (1), the ESIFS is the serial interface (2) enable registers and P10–P13, P30–
P33 terminals become serial input/output terminals (SIN, SOUT, SCLK, SRDY) when "1" is written, and
they become I/O port terminals when "0" is written.
Also, see Table 4.11.3.2 for the terminal settings according to the transfer modes.
At initial reset, this register is set to "0".

Note: After setting ESIF to "1", wait at least 10 µsec before starting actual data transfer since a hazard

may be generated from the P12 (SCLK) terminal when ESIF is set to "1".
Also, setting ESIFS to "1" may cause a hazard to be generated from the P32 (SCLK) terminal, so a
10 µsec or more interval is also needed here.

PUL10: Serial interface (1) SIN pull-up control register (FF45H•D0)
PUL12: Serial interface (1) SCLK pull-up control register (FF45H•D2)
PUL30: Serial interface (2) SIN pull-up control register (FF4DH•D0)
PUL32: Serial interface (2) SCLK pull-up control register (FF4DH•D2)

Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).

When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF

Reading: Valid

Sets the pull-up resistor built into the SIN (P10/P30) and SCLK (P12/P32) terminals to ON or OFF. (Pull-
up resistor is only built in the port selected by mask option.)
SCLK pull-up is effective only in the slave mode. In the master mode, the PUL12/PUL32 register can be
used as a general purpose register.
At initial reset, these registers are set to "1" and the lines are pulled up.

SMD0, SMD1: Serial interface (1) mode selection register (FF70H•D1, D2)
SMD0S, SMD1S: Serial interface (2) mode selection register (FF58H•D1, D2)

Set the transfer modes as shown in Table 4.11.9.2.

Table 4.11.9.2 Transfer mode settings

SMD1/SMD1S SMD0/SMD0S

Mode

1

1

0

0

1

0

1

0

8-bit asynchronous

7-bit asynchronous

Clock synchronous slave

Clock synchronous master

This register can also read out.
At initial reset, this register is set to "0".

SCS0, SCS1: Serial interface (1) clock source selection register (FF71H•D0, D1)
SCS0S, SCS1S: Serial interface (2) clock source selection register (FF59H•D0, D1)

Select the clock source as shown in Table 4.11.9.3.

Table 4.11.9.3 Clock source selection

SCS1

1

1

0

0

SCS0

1

0

1

0

Clock source

Programmable timer

f

OSC3

/ 93 (2400 bps)

f

OSC3

/ 372 (600 bps)

f

OSC3

/ 186 (1200 bps)

This register can also be read out.
In the clock synchronous slave mode, setting of this register is invalid.
At initial reset, this register is set to "0".

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Summary of Contents for S1C63558

Page 1: ...MF1153 03 Technical Manual CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63558 Technical Hardware S1C63558 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...Section 2 1 2 4 7 3 Page 8 49 Item Table 2 1 2 1 LCD drive voltage when generated internally Table 4 7 3 1 LCD drive voltage when generated internally Contents The table was revised The table was revised Chapter 2 4 S1C63557 Technical Manual ...

Page 4: ......

Page 5: ...al versions are not written in the manuals Previous No E0C63158 E0C63256 E0C63358 E0C63P366 E0C63404 E0C63406 E0C63408 E0C63F408 E0C63454 E0C63455 E0C63458 E0C63466 E0C63P466 New No S1C63158 S1C63256 S1C63358 S1C6P366 S1C63404 S1C63406 S1C63408 S1C6F408 S1C63454 S1C63455 S1C63458 S1C63466 S1C6P466 S1C63 Family peripheral products Previous No E0C63467 E0C63557 E0C63558 E0C63567 E0C63F567 E0C63658 E...

Page 6: ......

Page 7: ... 3 1 CPU 12 3 2 Code ROM 12 3 3 RAM 12 3 4 Data ROM 13 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 14 4 1 Memory Map 14 4 2 Watchdog Timer 23 4 2 1 Configuration of watchdog timer 23 4 2 2 Interrupt function 23 4 2 3 I O memory of watchdog timer 24 4 2 4 Programming notes 24 4 3 Oscillation Circuit 25 4 3 1 Configuration of oscillation circuit 25 4 3 2 OSC1 oscillation c...

Page 8: ...4 I O memory of clock timer 59 4 8 5 Programming notes 60 4 9 Stopwatch Timer 61 4 9 1 Configuration of stopwatch timer 61 4 9 2 Count up pattern 61 4 9 3 Interrupt function 62 4 9 4 I O memory of stopwatch timer 63 4 9 5 Programming notes 64 4 10 Programmable Timer 65 4 10 1 Configuration of programmable timer 65 4 10 2 Setting of initial value and counting down 66 4 10 3 Counter mode 67 4 10 4 S...

Page 9: ...FSK Demodulator 136 4 15 1 Configuration of FSK demodulator 136 4 15 2 Mask option 138 4 15 3 Ring carrier detection and interrupt 139 4 15 4 Inputting FSK data 140 4 15 5 I O memory of FSK demodulator 142 4 15 6 Programming notes 144 4 16 Interrupt and HALT 145 4 16 1 Interrupt factor 147 4 16 2 Interrupt mask 148 4 16 3 Interrupt vector 148 4 16 4 I O memory of interrupt 149 4 16 5 Programming n...

Page 10: ...6 7 10 Characteristic Curves reference value 167 CHAPTER 8 PACKAGE _______________________________________________ 169 8 1 Plastic Package 169 8 2 Ceramic Package for Test Samples 170 CHAPTER 9 PAD LAYOUT ____________________________________________ 171 9 1 Diagram of Pad Layout 171 9 2 Pad Coordinates 172 ...

Page 11: ...s It is possible to switch the 8 bits to special output 2 I O port 16 bits It is possible to switch the 2 bits to special output and the 4 bits to serial I F input output 2 Serial interface 2 ch 8 bit clock synchronous or asynchronous system is selectable LCD driver 40 segments 8 16 or 17 commons 2 48 segments 8 commons 1 Time base counter 2 systems Clock timer stopwatch timer Programmable timer B...

Page 12: ...R10 R13 R20 R23 1 Mask option Core CPU S1C63000 ROM 8 192 words 13 bits System Reset Control Interrupt Generator OSC RAM 5 120 words 4 bits Data ROM 2 048 words 4 bits LCD Driver 40 SEG 17 COM TONE DP Telephone Function AVDD AVSS TIP RING FB BPOUT CDIN RDIN RDRC VREF FSK Demodulator Power Controller SVD Stopwatch Timer Clock Timer Programmable Timer Counter Input Port Serial Interface 1 Sound Gene...

Page 13: ...127 128 Pin name N C SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 N C Pin name SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD RESET TEST TONE DP R23 R22 R21 R20 R13 R12 R11 N C Pin name N C R10 R03 R02 R01 R00 CDIN BPOUT...

Page 14: ...ignal output is possible by software I O port switching to serial I F 2 input output is possible by software Output port switching to XBZ signal output is possible by software Output port switching to BZ signal output is possible by software Output port switching to TOUT signal output is possible by software Output port switching to FOUT signal output is possible by software Output port switching ...

Page 15: ...2 2 2 Simultaneous low input to terminals K00 K03 for details 3 Input port pull up resistor The mask option is used to select whether the pull up resistor is supplemented to the input ports or not It is possible to select for each bit of the input ports Refer to Section 4 4 3 Mask option for details 4 Output specification of the output port Either complementary output or N channel open drain outpu...

Page 16: ...able in each option item as indicated in the option list Refer to Chapter 4 Peripheral Circuits and Operation to select the specifica tions that meet the application system Be sure to select the specifications for unused functions too according to the instruction provided Use fog63558 in the S5U1C63000A package for this selection Refer to the S5U1C63558D Manual for details 1 MULTIPLE KEY ENTRY RES...

Page 17: ...enDrain P23 1 Complementary 2 Nch OpenDrain P30 1 Complementary 2 Nch OpenDrain P31 1 Complementary 2 Nch OpenDrain P32 1 Complementary 2 Nch OpenDrain P33 1 Complementary 2 Nch OpenDrain 6 I O PORT PULL UP RESISTOR P0x 1 With Resistor 2 Gate Direct P1x 1 With Resistor 2 Gate Direct P20 1 With Resistor 2 Gate Direct P21 1 With Resistor 2 Gate Direct P22 1 With Resistor 2 Gate Direct P23 1 With Res...

Page 18: ...ircuit Oscillation system voltage regulator LCD driver Fig 2 1 1 Configuration of power supply 2 1 1 Voltage VD1 for oscillation circuit and internal circuits VD1 is a voltage for the oscillation circuit and the internal logic circuits and is generated by the oscillation system voltage regulator for stabilizing the oscillation The VD1 voltage is fixed at 2 1 V so it is not necessary to control by ...

Page 19: ...ET Initial reset can be executed externally by setting the reset terminal to a low level VSS After that the initial reset is released by setting the reset terminal to a high level VDD and the CPU starts operating The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 2 Hz signal high that is divided by the OSC...

Page 20: ...nitial reset if that time is the defined time 1 to 2 sec or more If using this function make sure that the specified ports do not go low at the same time during ordinary operation 2 2 3 Internal register at initial resetting Initial reset initializes the CPU as shown in Table 2 2 3 1 The registers and flags which are not initialized by initial reset should be initialized in the program if necessar...

Page 21: ...t FOUT FOUT XRMUTE XRMUTE XTMUTE XTMUTE TOUT TOUT BZ BZ XBZ XBZ HFO HFO HDO HDO Table 2 2 4 1 b List of shared terminal settings Pxx Terminal name P00 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 Special output Serial I F 2 Terminal status at initial reset P00 P03 Input Pull up 1 P10 Input Pull up 1 P11 Input Pull up 1 P12 Input Pull up 1 P13 Input Pull up 1 P20 Input Pull up 1 P21 Input Pu...

Page 22: ...s 0000H to 13FFH on the data memory map Addresses 0100H to 01FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When programming keep the following points in mind 1 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 2 The S1C63000 core CPU handles t...

Page 23: ...bit data 0000H 00FFH 0100H 01FFH 0200H 13FFH 4 bits 4 bit access area SP2 stack area 4 bit access area Data area 4 16 bit access area SP1 stack area Fig 3 3 1 Configuration of data RAM 3 4 Data ROM The data ROM is a mask ROM for loading various static data such as a character generator and has a capacity of 2 048 words 4 bits The data ROM is assigned to addresses 8000H to 87FFH on the data memory ...

Page 24: ...d peripheral I O memory Figure 4 1 1 shows the overall memory map of the S1C63558 and Tables 4 1 1 a h the peripheral circuits I O space memory maps 0000H 1400H 8000H 8800H F000H FF00H FFFFH RAM area Unused area Unused area Data ROM area I O memory area Display memory area Unused area Peripheral I O area F000H F25EH FF00H FFFFH Fig 4 1 1 Memory map Note Memory is not implemented in unused areas wi...

Page 25: ...F row frequency output enable DTMF column frequency output enable 0 8 8 1 1 9 9 2 2 10 10 3 3 11 11 4 4 12 12 5 5 13 13 6 6 14 14 7 7 15 15 PTS3 0 Time sec PTS3 0 Time sec FF12H FTS3 FTS2 FTS1 FTS0 R W FTS3 FTS2 FTS1 FTS0 0 1 1 0 Flash time selection initial value 563 ms 0 8 750 1 94 9 844 2 188 10 938 3 281 11 1031 4 375 12 1125 5 469 13 1219 6 563 14 1313 7 656 15 1406 FTS3 0 Time ms FTS3 0 Time...

Page 26: ...h Low Low Low Low R03 output port data FOUTE 0 Fix at 1 when FOUT is used R02 output port data PTOUT 0 Fix at 1 when TOUT is used R01 output port data BZOUT 0 Fix at 1 when BZ is used R00 output port data XBZOUT 0 Fix at 1 when XBZ is used FF32H R13HIZ R12HIZ R11HIZ R10HIZ R W R13HIZ R12HIZ R11HIZ R10HIZ 0 0 0 0 Hi Z Hi Z Hi Z Hi Z Output Output Output Output R13 CHFO 0 HFO CHFO 1 Hi z control R12...

Page 27: ...t Output Input Input Input Input P33 I O control register General purpose register when SIF clock sync slave is selected P32 I O control register General purpose register when SIF clock sync is selected P31 I O control register ESIFS 0 General purpose register when SIF is selected P30 I O control register ESIFS 0 General purpose register when SIF is selected FF4DH PUL33 PUL32 PUL31 PUL30 R W PUL33...

Page 28: ...overrun error flag status reading Serial I F 2 overrun error flag reset writing R W FF5CH 2 2 2 2 High High High High Low Low Low Low Serial I F 2 transmit receive data low order 4 bits LSB R W FF5DH 2 2 2 2 High High High High Low Low Low Low MSB Serial I F 2 transmit receive data high order 4 bits FF60H LDUTY1 LDUTY0 Dummy LPWR R W LDUTY1 LDUTY0 Dummy LPWR 0 0 0 0 On Off LCD drive duty switch Ge...

Page 29: ...trigger writing Serial I F 1 receive enable Serial I F 1 transmit status reading Serial I F 1 transmit trigger writing Serial I F 1 transmit enable R R W FF73H 0 FER PER OER 0 3 FER PER OER 2 0 0 0 Error Reset Error Reset Error Reset No error No error No error Unused Serial I F 1 framing error flag status reading Serial I F 1 framing error flag reset writing Serial I F 1 parity error flag status r...

Page 30: ...d Timer 0 Run Stop W R W R W FFC2H PTPS01 PTPS00 PTRST0 PTRUN0 0 1 1 1 1 4 2 1 32 3 1 256 PTPS01 00 Division ratio PTPS11 PTPS10 PTRST1 3 PTRUN1 0 0 2 0 Reset Run Invalid Stop Prescaler 1 division ratio selection Timer 1 reset reload Timer 1 Run Stop W R W R W FFC3H PTPS11 PTPS10 PTRST1 PTRUN1 RLD03 RLD02 RLD01 RLD00 0 0 0 0 MSB Programmable timer 0 reload data low order 4 bits LSB R W FFC4H RLD03...

Page 31: ...rupt mask register Dialer FFEAH 0 0 EIRDET EICDET R R W 0 3 0 3 EIRDET EICDET 2 2 0 0 Enable Enable Mask Mask Unused Unused Interrupt mask register FSK demodulator ring detection Interrupt mask register FSK demodulator carrier detection FFF2H 0 0 IPT1 IPT0 R R W 0 3 0 3 IPT1 IPT0 2 2 0 0 R Yes W Reset R No W Invalid Unused Unused Interrupt factor flag Programmable timer 1 Interrupt factor flag Pro...

Page 32: ...terrupt factor flag Dialer FFFAH 0 0 IRDET ICDET R R W 0 3 0 3 IRDET ICDET 2 2 0 0 R Yes W Reset R No W Invalid Unused Unused Interrupt factor flag FSK demodulator ring detection Interrupt factor flag FSK demodulator carrier detection FFF8H 0 ISERS ISTRS ISRCS R R W 0 3 ISERS ISTRS ISRCS 2 0 0 0 R Yes W Reset R No W Invalid Unused Interrupt factor flag Serial I F 2 error Interrupt factor flag Seri...

Page 33: ... bit binary counter and generates the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine...

Page 34: ...hen 0 is written Disabled Reading Valid When 1 is written to the WDEN register the watchdog timer starts count operation When 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 WDRST Watchdog timer reset FF07H D0 Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading A...

Page 35: ...lock selection signal To CPU To peripheral circuits Clock switch Oscillation system voltage regulator OSC3 oscillation circuit OSC1 oscillation circuit VD1 Divider Fig 4 3 1 1 Oscillation system block diagram 4 3 2 OSC1 oscillation circuit The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits The oscillation frequency is 32 768 kHz Typ Figure 4 3 2 1...

Page 36: ... of the OSC3 oscillation circuit oscillation can be stopped by the software OSCC register 4 3 4 Switching the CPU operating clock The CPU system clock is switched to OSC1 or OSC3 by the software CLKCHG register When OSC3 is to be used as the CPU system clock first turn the OSC3 oscillation ON and switch the clock after waiting 5 msec or more for oscillation stabilization When switching from OSC3 t...

Page 37: ...tion clock is selected with this register When 1 is written OSC3 clock is selected When 0 is written OSC1 clock is selected Reading Valid When the CPU clock is to be OSC3 set CLKCHG to 1 for OSC1 set CLKCHG to 0 After turning the OSC3 oscillation ON OSCC 1 switching of the clock should be done after waiting 5 msec or more At initial reset this register is set to 0 4 3 7 Programming notes 1 It take...

Page 38: ...ption suits input from the push switch key matrix and so forth When Gate direct is selected the port can be used for slide switch input and interfacing with other LSIs 4 4 2 Interrupt function All eight bits of the input ports K00 K03 K10 K13 provide the interrupt function The conditions for issuing an interrupt can be set by the software Further whether to mask the interrupt function can be selec...

Page 39: ...e of an interrupt for K00 K03 Interrupt selection register SIK03 1 SIK02 1 SIK01 1 SIK00 0 Input port 1 Initial value Interrupt generation K03 1 K02 0 K01 1 K00 0 Input comparison register KCP03 1 KCP02 0 KCP01 1 KCP00 0 With the above setting the interrupt of K00 K03 is generated under the following condition 2 K03 1 K02 0 K01 1 K00 1 3 K03 0 K02 0 K01 1 K00 1 4 K03 0 K02 1 K01 1 K00 1 Because K0...

Page 40: ... K10 K13 input port data FF26H KCP13 KCP12 KCP11 KCP10 R W KCP13 KCP12 KCP11 KCP10 1 1 1 1 K10 K13 input comparison register FFE4H 0 0 0 EIK0 R R W 0 3 0 3 0 3 EIK0 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K00 K03 FFE5H 0 0 0 EIK1 R R W 0 3 0 3 0 3 EIK1 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K10 K13 FFF4H 0 0 0 IK0 R R W 0 3 0 3 0 3 IK0 2 2 2 0 R Y...

Page 41: ...gisters At initial reset these registers are set to 0 EIK0 K0 input interrupt mask register FFE4H D0 EIK1 K1 input interrupt mask register FFE5H D0 Masking the interrupt of the input port can be selected with these registers When 1 is written Enable When 0 is written Mask Reading Valid With these registers masking of the input port interrupt can be selected for each of the two systems K00 K03 K10 ...

Page 42: ...ng expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kΩ 2 The K13 terminal functions as the clock input terminal for the programmable timer and the input signal is shared with the input port and the programmable timer Therefore when the K13 terminal is set to the clock input terminal for the programmable timer take care of the interrupt setting 3 After...

Page 43: ...unction selection Table 4 5 1 1 Function setting of output terminals Terminal name R00 R01 R02 R03 R10 R11 R12 R13 R20 R23 Special output Terminal status at initial reset R00 HIGH output R01 HIGH output R02 HIGH output R03 HIGH output R10 HIGH output R11 HIGH output R12 HIGH output R13 HIGH output R20 R23 HIGH output FOUT R00 R01 R02 FOUT R10 R11 R12 R13 R20 R23 XRMUTE R00 R01 R02 R03 R10 XRMUTE R...

Page 44: ...utput control register CHFO CHDO CRMO CTMO FOUTE PTOUT BZOUT XBZOUT Data bus Register FOUTE Register R03 Register R03HIZ FOUT R03 FOUT Register PTOUT Register R02 Register R02HIZ TOUT R02 TOUT Register BZOUT Register R01 Register R01HIZ BZ R01 BZ Register XBZOUT Register R00 Register R00HIZ XBZ R00 XBZ Data bus Register CHFO Register R13 Register R13HIZ HFO R13 HFO Register CHDO Register R12 Regis...

Page 45: ...ection 4 12 Sound Generator for details of the buzzer signal and controlling method TOUT R02 The R02 terminal can output a TOUT signal The TOUT signal is the clock that is output from the programmable timer and can be used to provide a clock signal to an external device To output the TOUT signal fix the R02 register at 1 and the R02HIZ register at 0 and turn the signal ON and OFF using the PTOUT r...

Page 46: ... to the CRMO register and fix the R11 register at 1 and the R11HIZ register at 0 Use the CRMUTE register for controlling the XRMUTE signal output Refer to Section 4 14 Telephone Function for details of the signal and controlling method HDO R12 The R12 terminal can output a HDO signal The HDO signal is the hold line signal used for the telephone function To output the HDO signal set the R12 port as...

Page 47: ... used R01 output port data BZOUT 0 Fix at 1 when BZ is used R00 output port data XBZOUT 0 Fix at 1 when XBZ is used FF32H R13HIZ R12HIZ R11HIZ R10HIZ R W R13HIZ R12HIZ R11HIZ R10HIZ 0 0 0 0 Hi Z Hi Z Hi Z Hi Z Output Output Output Output R13 CHFO 0 HFO CHFO 1 Hi z control R12 CHDO 0 HDO CHDO 1 Hi z control R11 CRMO 0 XRMUTE CRMO 1 Hi z control R10 CTMO 0 XTMUTE CTMO 1 Hi z control FF33H R13 HFO R1...

Page 48: ...without changing it When 1 is written to the register the output port terminal goes high VDD and when 0 is written the output port terminal goes low VSS When an output port R00 R03 R10 R13 is used for special output fix the corresponding data register at 1 At initial reset these registers are all set to 1 XBZOUT R00 output selection register FF65H D0 Selects the R00 terminal function When 1 is wri...

Page 49: ...R03HIZ register has been set to 0 an FOUT signal is output from the R03 terminal When 0 is written the R03 terminal goes high VDD When using the R03 output port for general purpose output fix this register at 0 At initial reset this register is set to 0 FOFQ0 FOFQ1 FOUT frequency selection register FF06H D0 D1 Selects a frequency of the FOUT signal Table 4 5 5 2 FOUT clock frequency FOFQ1 1 1 0 0 ...

Page 50: ...t to 0 CHFO R13 output selection register FF13H D3 Selects the R13 terminal function When 1 is written HFO output When 0 is written General purpose DC output Reading Valid When using the R13 terminal for the HFO output write 1 to this register Furthermore fix the R13 register at 1 and the R13HIZ register at 0 Refer to Section 4 14 Telephone Function for controlling the HFO output When using the R1...

Page 51: ... name P00 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 Special output Serial I F 1 2 Terminal status at initial reset P00 P03 Input Pull up P10 Input Pull up P11 Input Pull up P12 Input Pull up P13 Input Pull up P20 Input Pull up P21 Input Pull up P22 Input Pull up P23 Input Pull up P30 Input Pull up P31 Input Pull up P32 Input Pull up P33 Input Pull up CL P00 P03 P10 P11 P12 P13 P20 P21 CL...

Page 52: ...rite 1 is to the I O control register When an I O port is set to output mode it works as an output port it outputs a high level VDD when the port output data is 1 and a low level VSS when the port output data is 0 If perform the read out in each mode when output mode the register value is read out and when input mode the port value is read out At initial reset the I O control registers are set to ...

Page 53: ...tput from the P22 terminal and P23 terminal when the functions are switched by the EXLCDC register The following tables show the frequencies of the CL and FR signals Table 4 6 5 1 CL signal frequency OSC1 oscillation frequency 32 768 kHz When 1 8 duty is selected 512 Hz When 1 16 duty is selected 1 024 Hz When 1 17 duty is selected 1 024 Hz Table 4 6 5 2 FR signal frequency OSC1 oscillation freque...

Page 54: ...lock sync slave is selected P11 pull up control register ESIF 0 General purpose register when SIF is selected P10 pull up control register ESIF 0 SIN pull up control register when SIF is selected FF46H P13 XSRDY P12 XSCLK P11 SOUT P10 SIN R W P13 P12 P11 P10 2 2 2 2 High High High High Low Low Low Low P13 I O port data General purpose register when SIF clock sync slave is selected P12 I O port dat...

Page 55: ...31 PUL30 1 1 1 1 On On On On Off Off Off Off P33 pull up control register General purpose register when SIF clock sync slave is selected P32 pull up control register General purpose register when SIF clock sync master is selected SCLK I pull up control register when SIF clock sync slave is selected P31 pull up control register ESIFS 0 General purpose register when SIF is selected P30 pull up contr...

Page 56: ... configuration within P30 P33 that are used for the serial interface 2 is decided by the transfer mode 7 bit asynchronous 8 bit asynchronous clock synclonous slave clock synchronous master selected with the SMD1S and SMD0S registers In the clock synchronous slave mode all the P30 P33 ports are set to the serial interface 2 input output port In the clock synchronous master mode P30 P32 are set to t...

Page 57: ...lid The input and output modes of the I O ports are set in 1 bit unit Writing 1 to the I O control register makes the corresponding I O port enter the output mode and writing 0 induces the input mode At initial reset these registers are all set to 0 so the I O ports are in the input mode The I O control registers of the port which are set for the special output P22 P23 or input output of the seria...

Page 58: ...the pull up resistor and input gate capaci tance Hence when fetching input ports set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kΩ 2 When special output CL FR has...

Page 59: ...ed by the LCD system voltage circuit These four output voltages can only be supplied to the externally expanded LCD driver Turning the LCD system voltage circuit ON or OFF is controlled with the LPWR register When LPWR is set to 1 the LCD system voltage circuit outputs the LCD drive voltages VC1 VC23 VC4 and VC5 to the LCD driver The LCD system voltage circuit generates VC23 with the voltage regul...

Page 60: ...ged to SEG47 SEG40 Therefore COM8 COM16 cannot be used In this case be sure to set the drive duty to 1 8 by the software Table 4 7 4 2 shows the frame frequencies corresponding to the OSC1 oscillation frequency and drive duty Table 4 7 4 2 Frame frequency OSC1 oscillation frequency 32 768 kHz When 1 8 duty is selected 32 Hz When 1 16 duty is selected 32 Hz When 1 17 duty is selected 30 12 Hz Figur...

Page 61: ...005H F104H F105H F204H SEG3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 F006H F007H F106H F107H F206H SEG39 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 F04EH F04FH F14EH F14FH F24EH 1 16 duty 1 17 duty Data bit a When 1 17 or 1 16 duty is selected COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Unused SEG0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D...

Page 62: ...en it is set to 0 the dot goes OFF At 1 17 1 16 duty drive all data of COM0 COM16 15 is output At 1 8 duty drive data only corresponding to COM0 COM7 is output However since the display memory has capacity for two screens it is designed so that the memory for COM8 COM15 shown in Figure 4 7 5 1 a can also be used as COM0 COM15 Select either F000H F05FH or F100H F15FH for the area to be displayed to...

Page 63: ...6 7 8 9 10 11 12 13 14 15 LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Contrast light dark Setting the LC3 LC0 register affects the VC23 voltage and other voltages change according to the VC23 As a result the LCD contrast is adjusted The supply voltage VDD within the range from 2 2 to 2 5 V affects t...

Page 64: ...OM1 COM5 COM1 COM5 COM1 COM5 D0 COM0 COM4 COM0 COM4 COM0 COM4 COM0 COM4 SEG0 SEG0 SEG1 SEG1 SEG2 SEG38 SEG39 SEG39 Not implemented COM0 COM7 F100H F101H F102H F103H F104H F14DH F14EH F14FH F160H F1FFH D3 COM11 COM15 COM11 COM15 COM11 COM15 COM11 COM15 D2 COM10 COM14 COM10 COM14 COM10 COM14 COM10 COM14 0 D1 COM09 COM13 COM09 COM13 COM9 COM13 COM9 COM13 D0 COM8 COM12 COM8 COM12 COM8 COM12 COM8 COM12...

Page 65: ...0 8 640 40 16 680 40 17 When 48 8 mask option is selected 384 48 8 Invalid Invalid At initial reset this register is set to 0 When 48 8 is selected by mask option reset to 1 8 duty ALON LCD all ON control register FF61H D1 Displays the all LCD dots ON When 1 is written All LCD dots displayed When 0 is written Normal display Reading Valid By writing 1 to the ALON register all the LCD dots goes ON a...

Page 66: ...3 LC0 1111B dark At room temperature use setting number 7 or 8 as standard At initial reset LC3 LC0 are undefined 4 7 8 Programming notes 1 When a program that access no memory mounted area F060H F0FFH F160H F1FFH F201H F203H F25FH is made the operation is not guaranteed 2 Because at initial reset the contents of display memory and LC3 LC0 LCD contrast are undefined there is need to initialize by ...

Page 67: ...0 TM0 128 Hz D1 TM1 64 Hz D2 TM2 32 Hz D3 TM3 16 Hz FF7AH D0 TM4 8 Hz D1 TM5 4 Hz D2 TM6 2 Hz D3 TM7 1 Hz Since the clock timer data has been allocated to two addresses a carry is generated from the low order data within the count TM0 TM3 128 16 Hz to the high order data TM4 TM7 8 1 Hz When this carry is generated between the reading of the low order data and the high order data a content combinin...

Page 68: ...nterrupt request Bit D0 D1 D2 D3 D0 D1 D2 D3 Frequency Clock timer timing chart 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Fig 4 8 3 1 Timing chart of clock timer As shown in Figure 4 8 3 1 interrupt is generated at the falling edge of the frequencies 32 Hz 8 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 is set to 1 Selection of whether to mask the separate in...

Page 69: ...lock timer 32 Hz 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read TM0 TM7 Timer data FF79H FF7AH The 128 1 Hz timer data of the clock timer can be read out with these registers These eight bits are read only and writing operations are invalid By reading the low order data FF79H the high order data FF7AH is held until reading or for 0 48 1 5 msec one of short...

Page 70: ... factor flags IT0 IT1 IT2 IT3 correspond to the clock timer interrupts of the respective frequencies 32 Hz 8 Hz 2 Hz 1 Hz The software can judge from these flags whether there is a clock timer interrupt However even if the interrupt is masked the flags are set to 1 at the falling edge of the signal These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will oc...

Page 71: ...n The stopwatch timer is configured of 4 bit BCD counters SWD0 SWD3 and SWD4 SWD7 The counter SWD0 SWD3 at the stage preceding the stopwatch timer has an approximated 100 Hz signal for the input clock It counts up every 1 100 sec and generates an approximated 10 Hz signal The counter SWD4 SWD7 has an approximated 10 Hz signal generated by the counter SWD0 SWD3 for the input clock In count up every...

Page 72: ...0 SWD3 and SWD4 SWD7 through their respective overflows can generate 10 Hz approximate 10 Hz and 1 Hz interrupts Figure 4 9 3 1 shows the timing chart for the stopwatch timer Address FF7DH 1 100sec BCD 10 Hz Interrupt request Bit D0 D1 D2 D3 Stopwatch timer SWD0 3 timing chart Address FF7EH 1 10sec BCD 1 Hz Interrupt request Bit D0 D1 D2 D3 Stopwatch timer SWD4 7 timing chart Fig 4 9 3 1 Timing ch...

Page 73: ... reset 2 Not set in the circuit 3 Constantly 0 when being read SWD0 SWD7 Stopwatch timer data FF7DH FF7EH The 1 100 sec and the 1 10 sec data BCD can be read from SWD0 SWD3 and SWD4 SWD7 respec tively These eight bits are read only and writing operations are invalid At initial reset the timer data is initialized to 00H SWRST Stopwatch timer reset FF7CH D1 When 1 is written Stopwatch timer reset Wh...

Page 74: ... Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags ISW10 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts respectively The software can judge from these flags whether there is a stopwatch timer interrupt However even if the interrupt is masked the flags are set to 1 by the overflow of the corresponding counters These fla...

Page 75: ...pt Generating a TOUT signal output from the R02 output port terminal Generating the synchronous clock source for the serial interface timer 1 underflow is used and it is possible to set the transfer rate Reload data register RLD00 RLD07 Data buffer PTD00 PTD07 Input port K13 PTRUN0 FCSEL PLPOL Programmable timer 0 PTPS00 PTPS01 8 bit down counter Prescaler Selector CKSEL0 Timer 0 Run Stop Clock co...

Page 76: ...N STOP does not affect the counter data The counter maintains its data while stopped and can restart counting continuing from that data The counter data can be read via the data buffers PTD00 PTD07 timer 0 and PTD10 PTD17 timer 1 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data when the low order data is read in order to p...

Page 77: ...T The timer 1 operates only in the timer mode and cannot be used as an event counter In the event counter mode the clock is supplied to timer 0 from outside of the IC therefore the settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings of the timer 0 source clock selection register CKSEL0 become invalid Count down timing can be selected from either ...

Page 78: ...tion registers CKSEL0 timer 0 and CKSEL1 timer 1 when 0 is written to the register OSC1 is selected and when 1 is written OSC3 is selected When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the osc...

Page 79: ...d when 1 is written timer 1 is selected Figure 4 10 6 1 shows the TOUT signal waveform when the channel is changed Timer 0 underflow Timer 1 underflow CHSEL 0 1 TOUT output R02 Fig 4 10 6 1 TOUT signal waveform at channel change The TOUT signal can be output from the R02 output port terminal Programmable clocks can be supplied to external devices Figure 4 10 6 2 shows the configuration of the outp...

Page 80: ... timer 1 into RUN state PTRUN 1 It is not necessary to control with the PTOUT register PTRUN1 Timer 1 underflow Source clock for serial I F Fig 4 10 7 1 Synchronous clock of serial interface A setting value for the RLD1X register according to a transfer rate is calculated by the following expres sion RLD1X fosc 32 bps division ratio of the prescaler 1 fosc Oscillation frequency OSC1 OSC3 bps Trans...

Page 81: ... 0 MSB Programmable timer 0 reload data low order 4 bits LSB R W FFC4H RLD03 RLD02 RLD01 RLD00 RLD07 RLD06 RLD05 RLD04 0 0 0 0 MSB Programmable timer 0 reload data high order 4 bits LSB R W FFC5H RLD07 RLD06 RLD05 RLD04 RLD13 RLD12 RLD11 RLD10 0 0 0 0 MSB Programmable timer 1 reload data low order 4 bits LSB R W FFC6H RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 0 0 0 0 MSB Programmable timer 1...

Page 82: ...rescaler division ratio selection register FFC3H D2 D3 Selects the division ratio of the prescaler Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0 and two bits of PTPS10 and PTPS11 are for timer 1 The prescaler division ratios that can be set by these registers are shown in Table 4 10 8 2 Table 4 10 8 2 Selection of prescaler division ratio PTPS11 PTPS...

Page 83: ... 0 is selected from either the falling edge of the external clock input to the K13 input port terminal or the rising edge When 0 is written to the PLPOL register the falling edge is selected and when 1 is written the rising edge is selected Setting of this register is effective only when timer 0 is used in the event counter mode At initial reset this register is set to 0 RLD00 RLD07 Timer 0 reload...

Page 84: ...ps by writing 0 In STOP status the counter data is maintained until the counter is reset or is set in the next RUN status When STOP status changes to RUN status the data that has been maintained can be used for resuming the count Same as above the timer 1 counter is controlled by the PTRUN1 register At initial reset these registers are set to 0 CHSEL TOUT output channel selection register FFC1H D3...

Page 85: ...nterrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags IPT0 and IPT1 correspond to timer 0 and timer 1 interrupts respectively The software can judge from these flags whether there is a programmable timer interrupt However even if the interrupt is masked the flags are set to 1 by ...

Page 86: ...nter mode Therefore be aware that the counter does not enter RUN STOP status if a clock is not input after setting the RUN STOP control register PTRUN0 3 Since the TOUT signal is generated asynchronously from the PTOUT register a hazard within 1 2 cycle is generated when the signal is turned ON and OFF by setting the register 4 When the OSC3 oscillation clock is selected for the clock source it is...

Page 87: ...ng the FSK demodulator SIF 2 is used for data input SIF 1 cannot be used for this purpose Note Explanation made in this section is only for SIF 1 Be aware that S for the SIF 2 control bits is omitted Further the serial I O terminal names are explained using P10 P13 Figure 4 11 1 1 shows the configuration of the serial interface 1 The serial interface 2 has the same configuration except for the ter...

Page 88: ...ock synchronous master mode and SRDY for clock synchronous slave mode that are used as output in the input output port of the serial interface is respectively selected by the mask options of P11 P12 and P13 Either complementary output or N channel open drain output can be selected as the output specification However when N channel open drain output is selected do not apply a voltage exceeding the ...

Page 89: ...ynchronous slave mode 7 bit asynchronous mode In this mode 7 bit asynchronous transfer can be performed Parity check during data reception and addition of parity bit odd even none during transmitting can be specified and data processed in 7 bits with or without parity Since this mode employs the internal clock the SCLK terminal is not used Furthermore since the SRDY terminal is not utilized either...

Page 90: ...al SCLK Clock synchronous slave mode Divider Selector Selector 1 2 OSC3 oscillation circuit Fig 4 11 4 1 Division of the synchronous clock Table 4 11 4 2 shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer Table 4 11 4 2 OSC3 oscillation frequencies and transfer rates Transfer rate bps 9 600 4 800 2 400 1 200 600 300 150 fOSC3 3 5...

Page 91: ...ta In the clock synchronous mode synchronous clock input output from the SCLK terminal is also enabled The transmit control bit TXTRG is used as the trigger to start transmitting data Data to be transmitted is written to the transmit data shift register and when transmitting prepara tions a recomplete 1 is written to TXTRG whereupon data transmitting begins When interrupt has been enabled an inter...

Page 92: ...om the master side external serial input output device is used as the synchronous clock In the clock synchronous mode since one clock line SCLK is shared for both transmitting and receiving transmitting and receiving cannot be performed simultaneously Half duplex only is possible in clock synchronous mode Transfer data is fixed at 8 bits and both transmitting and receiving are conducted with the L...

Page 93: ...smitting data into TRXD0 TRXD7 4 In case of the master mode confirm the receive ready status on the slave side external serial input output device if necessary Wait until it reaches the receive ready status 5 Write 1 in the transmit control bit TXTRG and start transmitting In the master mode this control causes the synchro nous clock to change to enable and to be provided to the shift register for...

Page 94: ...sively incorpo rated into the shift register in synchronization with the rising edge of the synchronous clock At the point where the data of the 8th bit has been incorporated at the final 8th rising edge of the synchronous clock the content of the shift register is sent to the receive data buffer and the receiving complete interrupt factor flag ISRC is set to 1 When interrupt has been enabled a re...

Page 95: ... to 1 at the point where the first synchronous clock has been input falling edge When you have set in the master mode control the transfer by inputting the same signal from the slave side using the input port or I O port At this time since the SRDY terminal is not set and instead P13 functions as the I O port you can apply this port for said control Timing chart The timing chart for the clock sync...

Page 96: ...mpling clock 8bit data D0 D1 D2 D3 D4 D5 D6 p s1 s2 7bit data parity D0 D1 D2 D3 D4 D5 D6 D7 s1 s2 8bit data parity D0 D1 D2 D3 D4 D5 D6 D7 s1 p s2 s1 s2 p Start bit Low level 1 bit Stop bit High level 1 bit Parity bit 7bit data D0 D1 D2 D3 D4 D5 D6 s1 s2 Fig 4 11 7 1 Transfer data configuration for asynchronous system Here following we will explain the control sequence and operation for initializ...

Page 97: ...llation circuit is turned ON prior to commencing data transfer See 4 3 Oscillation Circuit Data transmit procedure The control procedure and operation during transmitting is as follows 1 Write 0 in the transmit enable register TXEN to reset the serial interface 2 Write 1 in the transmit enable register TXEN to set into the transmitting enable status 3 Write the transmitting data into TRXD0 TRXD7 A...

Page 98: ...oint When an overrun error is generated the interrupt factor flag ISRC is not set to 1 and a receiv ing complete interrupt is not gener ated End RXEN 1 No Yes Receiving interrupt Yes Receiving complete Received data reading from TRXD0 TRXD7 RXEN 0 RXTRG 1 No Yes Error generated Error processing Data receiving RXEN 0 Resets error flags PER OER and FER No If with parity check has been selected a par...

Page 99: ...p bit 1 When receiving has been done with the stop bit set at 0 the serial interface judges the synchronization to be off and a framing error is generated When this error is gener ated the framing error flag FER and the error interrupt factor flag ISER are set to 1 When interrupt has been enabled an error interrupt is generated at this point The FER flag is reset to 0 by writing 1 Even when this e...

Page 100: ... D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D2 D3 D4 D5 1st data 2st data Sumpling clock b Receive timing Fig 4 11 7 4 Timing chart asynchronous transfer 4 11 8 Interrupt function This serial interface includes a function that generates the below indicated three types of interrupts Transmitting complete interrupt Receiving complete interrupt Error interrupt The interrupt factor flag ISxx and the interrupt mask...

Page 101: ... incorporated into the shift register has been transferred into the receive data buffer and it sets the interrupt factor flag ISRC to 1 When set in this manner if the corresponding interrupt mask register EISRC is set to 1 and the CPU is set to interrupt enabled status I flag 1 an interrupt will be generated to the CPU When the interrupt mask register EISRC has been set to 0 and interrupt has been...

Page 102: ...slave 3 Async 8 bit SMD1S 0S Mode SMD1S 0S Mode FF58H 0 SMD1S SMD0S ESIFS R R W 0 3 SMD1S SMD0S ESIFS 2 0 0 0 SIF I O Unused Serial I F 2 mode selection Serial I F 2 enable P3x port function selection 0 1200bps 1 600bps 2 2400bps 3 PT SCS1S 0S Mode FF59H R W 0 0 0 0 Enable Odd Disable Even Serial I F 2 parity enable register Serial I F 2 parity mode selection SIF 2 clock source selection R W FF5AH...

Page 103: ...High High High High Low Low Low Low Serial I F 1 transmit receive data low order 4 bits LSB R W FF75H TRXD7 TRXD6 TRXD5 TRXD4 TRXD7 TRXD6 TRXD5 TRXD4 2 2 2 2 High High High High Low Low Low Low MSB Serial I F 1 transmit receive data high order 4 bits FFE3H 0 EISER EISTR EISRC R R W 0 3 EISER EISTR EISRC 2 0 0 0 Enable Enable Enable Mask Mask Mask Unused Interrupt mask register Serial I F 1 error I...

Page 104: ...en 0 is written Pull up OFF Reading Valid Sets the pull up resistor built into the SIN P10 P30 and SCLK P12 P32 terminals to ON or OFF Pull up resistor is only built in the port selected by mask option SCLK pull up is effective only in the slave mode In the master mode the PUL12 PUL32 register can be used as a general purpose register At initial reset these registers are set to 1 and the lines are...

Page 105: ...arity check and addition of a parity bit is only valid when 1 has been written to EPR EPRS When 0 has been written to EPR EPRS the parity setting by PMD PMDS becomes invalid At initial reset this register is set to 0 TXEN Serial interface 1 transmit enable register FF72H D0 TXENS Serial interface 2 transmit enable register FF5AH D0 Sets the serial interface to the transmit enabled status When 1 is...

Page 106: ...and the following receive preparation has been done In the slave mode SRDY becomes 0 at the point where 1 has been written into into the RXTRG RXTRGS In the asynchronous system RXTRG RXTRGS is used for preparation of the following data receiving Read the received data located in the receive data buffer and write 1 into RXTRG RXTRGS to inform that the receive data buffer has shifted to empty When 1...

Page 107: ...n error flag FF5BH D0 Indicates the generation of an overrun error When 1 is read Error When 0 is read No error When 1 is written Reset to 0 When 0 is written Invalid OER OERS is an error flag that indicates the generation of an overrun error and becomes 1 when an error has been generated An overrun error is generated when a receiving of data has completed prior to writing 1 to RXTRG RXTRGS in the...

Page 108: ...r flags FFF8H D0 D1 D2 Indicates the serial interface interrupt generation status When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid ISRC ISRCS ISTR ISTRS and ISER ISERS are interrupt factor flags that respectively correspond to the interrupts for receivie completion transmit completion and receive error and are...

Page 109: ...mplete interrupt is not generated Table 4 11 10 1 Time difference between ISER and ISRC on error generation Clock source Time difference fOSC3 n Programmable timer 1 2 cycles of fOSC3 n 1 cycle of timer 1 underflow 5 When the demultiplied signal of the OSC3 oscillation circuit is made the clock source it is necessary to turn the OSC3 oscillation ON prior to using the serial interface A time interv...

Page 110: ...cuit Envelope addition circuit ENON BZE R00 R01 output circuit BZOUT XBZOUT ENRTM ENRST BZSTP BZSHT SHTPW R01 BZ Fig 4 12 1 1 Configuration of sound generator 4 12 2 Buzzer output circuit The S1C63558 uses the R01 BZ and R00 XBZ terminals for outputting buzzer signals To drive a piezoelectric buzzer with one terminal use the BZ signal output from the R01 BZ terminal The piezo electric buzzer shoul...

Page 111: ...Write 1 to the XBZOUT register to set the XBZ output Also in this case the data register R00 for the R00 output port should be fixed at 1 and the high impedance register R00HIZ at 0 The buzzer signals generated by the sound generator are output from the BZ R01 and XBZ R00 terminals by writing 1 to the buzzer output enable register BZE When 0 is written to the BZE register the BZ R01 terminal goes ...

Page 112: ...evel 8 Min 4096 0 2048 0 8 16 7 16 6 16 5 16 4 16 3 16 2 16 1 16 3276 8 1638 4 8 20 7 20 6 20 5 20 4 20 3 20 2 20 1 20 2730 7 1365 3 12 24 11 24 10 24 9 24 8 24 7 24 6 24 5 24 2340 6 1170 3 12 28 11 28 10 28 9 28 8 28 7 28 6 28 5 28 Duty ratio by buzzer frequency Hz When the HIGH level output time has been made TH and when the LOW level output time has been made TL due to the ratio of the pulse wi...

Page 113: ...uated down to level 8 minimum it is retained at that level The duty ratio can be returned to maximum by writing 1 into register ENRST during output of a envelope attached buzzer signal The envelope attenuation time time for changing of the duty ratio can be selected by the register ENRTM The time for a 1 stage level change is 62 5 msec 16 Hz when 0 has been written into ENRTM and 125 msec 8 Hz whe...

Page 114: ...in operation during one shot output and when it is 0 it shows that the circuit is in the ready outputtable status In addition it can also terminate one shot output prior to the elapsing of the set time This is done by writing a 1 into the one shot buzzer stop BZSTP In this case as well the buzzer signal goes OFF in synchronization with the 256 Hz signal When 1 is written to BZSHT again during a on...

Page 115: ...ENRST 3 ENON BZE 0 Reset 0 0 1sec Reset On Enable 0 5sec Invalid Off Disable Envelope releasing time selection Envelope reset writing Envelope On Off Buzzer output enable FF6DH 0 BZSTP BZSHT SHTPW R W R W 0 3 BZSTP 3 BZSHT SHTPW 2 0 0 0 Stop Trigger Busy 125msec Invalid Invalid Ready 31 25msec Unused 1 shot buzzer stop writing 1 shot buzzer trigger writing 1 shot buzzer status reading 1 shot buzze...

Page 116: ...ix the R01 register at 1 and the R01HIZ register at 0 At initial reset this register is set to 0 BZE BZ output control register FF6CH D0 Controls the buzzer signal output When 1 is written Buzzer output ON When 0 is written Buzzer output OFF Reading Valid When 1 is written to BZE the BZ signal is output from the BZ R01 terminal and the XBZ signal is output from the XBZ R00 terminal When 0 is writt...

Page 117: ... No operation Reading Always 0 Writing 1 into ENRST resets envelope and the duty ratio becomes maximum If an envelope has not been added ENON 0 and if no buzzer signal is being output the reset becomes invalid Writing 0 is also invalid This bit is dedicated for writing and is always 0 for reading ENON Envelope ON OFF control register FF6CH D1 Controls the addition of an envelope onto the buzzer si...

Page 118: ...time extension When reading When 1 is read BUSY When 0 is read READY During reading BZSHT shows the operation status of the one shot output circuit During one shot output BZSHT becomes 1 and the output goes OFF it shifts to 0 At initial reset this bit is set to 0 BZSTP One shot buzzer stop FF6DH D2 Stops the one shot buzzer output When 1 is written Stop When 0 is written No operation Reading Alway...

Page 119: ... to use with the mask option 4 13 3 SVD operation The SVD circuit compares the criteria voltage set by software and the supply voltage VDD terminal VSS terminal or the external voltage SVD terminal VSS terminal and sets its results into the SVDDT latch By reading the data of this SVDDT latch it can be determined by means of software whether the supply voltage is normal or has dropped The criteria ...

Page 120: ...S2 SVDS1 SVDS0 0 0 0 0 SVD criteria voltage setting 0 2 20 1 05 8 2 60 1 2 20 9 2 70 2 2 20 10 2 80 3 2 20 11 2 90 4 2 20 12 3 00 5 2 30 13 3 10 6 2 40 14 3 20 7 2 50 15 3 30 SVDS3 0 Voltage V SVDS3 0 Voltage V 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read SVDS3 SVDS0 SVD criteria voltage setting register FF04H Criteria voltage for SVD is set as shown in ...

Page 121: ... a stable detection result the SVD circuit must be ON for at least l00 µsec So to obtain the SVD detection result follow the programming sequence below 1 Set SVDON to 1 2 Maintain for 100 µsec minimum 3 Set SVDON to 0 4 Read SVDDT 2 The SVD circuit should normally be turned OFF because SVD operation increase current consump tion ...

Page 122: ... pulses Either DTMF mode or DP mode can be selected by software In the DTMF mode the DTMF generator uses the OSC3 3 58 MHz clock to generate the tone signal set by software signal tone or dual tone and outputs it to the TONE terminal In the DP mode the DP generator uses the OSC1 32 kHz clock to generate the dial pulses for the number set by software to the DP terminal The push button matrix is con...

Page 123: ...for details of each control register Operating mode This dialer has built in a DTMF generator for generating tones and a DP generator for generating dial pulses Two basic operating modes are provided tone mode and pulse mode The mode can be switched by software TPS register This setting must be performed prior to the dial processing At initial reset tone mode is set The following operating conditi...

Page 124: ...e Section 4 14 10 I O memory of telephone function for details of each control register The hook switch HSON continuous tone output CTO hold line HOLD and handfree HF functions and their timings are controlled by software These functions do not generate interrupts The HSON that controls the hook switch must be turned ON off hook before executing the tele phone function Actual handset operations ar...

Page 125: ...Write 1000 to FF10H Write 0110 to IDP Write 0111 to FTS Write 0010 to PTS Set HSON 1 Set 5 to TCD Interrupt Reset ID No Yes Fig 4 14 3 2 Flow chart of dialing pulse transmission In the setting step 1000B is written to address FF10H to set pulse DP mode the make ratio 40 60 and the dialing rate 10 pps Then data is written to IDP FF15H PTS FF11H and FTS FF12H to set an inter digit pause time pause t...

Page 126: ...us Control registers TONE Row group programmable divider Column group programmable divider SINR SINC Sine wave pattern ROM Sine wave pattern ROM D A converter D A converter Vref 3 58 MHz oscillator Frequency divider Fig 4 14 4 1 DTMF generator block diagram As shown in Figure 4 14 4 1 the DTMF generator generates each frequency by dividing the OSC3 3 58 MHz clock Therefore the OSC3 oscillation cir...

Page 127: ...ime varies de pending on the external oscillator s characteristic and operating conditions allow ample margin for the interval Further the OSC3 oscillation circuit increases current consumption so it should be turned OFF when the DTMF generator is not used or the CPU does not need high speed processing The following explains how to output the tone signal and the circuit operation First write 1 to ...

Page 128: ...TO register However the tone signal will be output for 94 msec even if the CTO register is set to 0 before 94 msec duration time has passed The tone duration time when the CTO register is set to 0 is 94 msec When the tone signal has been output completely the TONE terminal returns to Low level then a 94 msec of inter digit pause will be inserted An interrupt occurs when the inter digit pause time ...

Page 129: ...a bus 32 kHz Oscillator Frequency Divider Control Registers Timing Control Programmable Down Counter DP Data bus 32 kHz oscillator Frequency divider Control registers Timing control circuit Programmable down counter DP Fig 4 14 5 1 DP generator block diagram The DP generator uses the OSC1 32 kHz clock for generating dial pulses In this mode it is not necessary to control the OSC3 oscillation circu...

Page 130: ...ate 10 pps or 20 pps using DRS 3 Select a make ratio 40 60 or 33 3 66 6 using MB 4 Select an inter digit pause time 94 msec to 1 406 msec using IDP The following explains how to output dial pulses and the circuit operation First write 1 to the HSON register FF18H D3 so the dialer is in off hook status As a result the DP terminal goes High VDD level Next write a digit of the dial number to be trans...

Page 131: ...ransmission of the next dial pulses The XRMUTE R11 and XTMUTE R10 terminals keep on Low level for 4 msec of mute hold time tMH after the inter digit pause is released If the next pulse output does not start in this period the XRMUTE R11 and XTMUTE R10 terminals return to High level When the next pulse output starts in the mute hold period the XRMUTE R11 and XTMUTE R10 terminals will stay in Low le...

Page 132: ...D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 PTS Pause time sec 8 9 10 11 12 13 14 15 Do not write 0 0000B to the PTS register because it may cause a malfunction At initial reset the pause time is set to 4 seconds Writing data to the PTS register just defines the pause time The actual pause operation will be activated when the PAUSE bit FF14H D1 is set to 1 Figure 4 14 6 1 shows the ti...

Page 133: ...0 0 1 1 Fig 4 14 6 1 b Pause execution timing chart in tone mode PAUSE is a write only bit and is used as the trigger for a pause insertion When the pause time that is set to the PTS register has passed from the writing of the PAUSE bit an interrupt occurs At the same time the PAUSE bit is automatically cleared to 0 by the interrupt Thus the pause function requires start control only The pause fun...

Page 134: ... 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 FTS Flash time msec 750 844 938 1031 1125 1219 1313 1406 Do not write 0 0000B to the FTS register because it may cause a malfunction At initial reset the flash time is set to 563 msec Writing data to the FTS register just defines the flash time The actual flash operation will be activated when the FLASH bit FF14H D0 is set to 1 Figure 4 14 7 1 shows a tim...

Page 135: ...the XTMUTE signal while holding the current communication line open This function can be controlled using the HOLD register When 1 is written to the HOLD register the communication line is held open and the XTMUTE signal goes Low level When 0 is written the XTMUTE signal returns to High level The R12 terminal can be used to output the HDO signal that indicates hold status To use the HDO signal set...

Page 136: ...terrupt occurs when the pause time 1 to 15 sec set by the PTS register has passed after writing 1 to the PAUSE bit See the timing chart in Figure 4 14 6 1 3 Flash interrupt When the flash function is executed 938 msec of a flash pause is made when the flash time 94 to 1 406 msec set by the FTS register has passed after writing 1 to the FLASH bit A flash interrupt occurs immediately following the f...

Page 137: ... value 750 ms 0 8 750 1 94 9 844 2 188 10 938 3 281 11 1031 4 375 12 1125 5 469 13 1219 6 563 14 1313 7 656 15 1406 IDP3 0 Time ms IDP3 0 Time ms FF17H TCD3 TCD2 TCD1 TCD0 R W TCD3 TCD2 TCD1 TCD0 0 0 0 0 Telephone code for dialing 0 R1C4 8 R3C2 8 1 R1C1 1 9 R3C3 9 2 R1C2 2 10 R4C2 10 3 R1C3 3 11 R4C3 11 4 R2C1 4 12 R4C1 12 5 R2C2 5 13 R2C4 13 6 R2C3 6 14 R4C4 14 7 R3C1 7 15 R3C4 15 TCD3 0 DTMF DP ...

Page 138: ... When 1 is written XTMUTE output When 0 is written General purpose DC output Reading Valid When using the R10 terminal for the XTMUTE output write 1 to this register Furthermore fix the R10 register at 1 and the R10HIZ register at 0 The XTMUTE output is controlled by the CTMUT register FF18H D0 At initial reset this register is set to 0 CRMO R11 output selection register FF13H D1 Selects the R11 t...

Page 139: ...ode Reading Valid When 1 is witten to the TPS register pulse mode outputs dial pulses is selected When 0 is written tone mode outputs tone signals is selected At initial reset this register is set to 0 MB Make Break ratio selection FF10H D1 Selects a make ratio for pulse mode When 1 is written 33 3 66 6 When 0 is written 40 0 60 0 Reading Valid The make ratio make break of the dialing pulses that ...

Page 140: ...me msec Unavailable 94 188 281 375 469 563 656 D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 FTS Flash time msec 750 844 938 1031 1125 1219 1313 1406 Do not write 0 0000B to the FTS register because it may cause a malfunction The specified flash time will be inserted when 1 is written to the FLASH bit FF14H D0 At initial reset this register is set to 0110B 563 msec HO...

Page 141: ...igh level output on R13 terminal When 0 is written OFF Low level output on R13 terminal Reading Valid This register controls the HFO signal output to the R13 terminal when the HFO function has been se lected The HFO output function is set by writing 1 to the CHFO register FF13H D3 In this case the R13 register must be fixed at 1 and the R13HIZ register at 0 When 1 is written to the HF register the...

Page 142: ...one output SINR 0 0 1 1 Control register SINC 0 1 0 1 Tone output DC level 1 2 VDD VSS COL frequency ROW frequency Dual tone output Tables 4 14 10 6 a and b list the frequencies set by the TCD register FF17H when single tone output is selected Table 4 14 10 6 a Single tone COL frequencies SINR 0 SINC 1 D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 TCD code COL frequen...

Page 143: ...is register Table 4 14 10 8 lists the relationship of writing codes and tone frequencies Table 4 14 10 8 Relationship of codes and tone frequencies D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 TCD code Tone frequency ROW1 COL4 ROW1 COL1 ROW1 COL2 ROW1 COL3 ROW2 COL1 ROW2 COL2 ROW2 COL3 ROW3 COL1 Key symbol A 1 2 3 4 5 6 7 D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 ...

Page 144: ...t this register is set to 0 CTO Continuous output tone selection FF16H D3 Selects the tone duration time to continuous output or not When 1 is written Continuous When 0 is written 94 msec Reading Valid This register is used to decide the tone duration time The minimum value of tone duration time is 94 msec When the CTO register is set to 1 a tone signal will be output until the CTO register is cha...

Page 145: ... interrupt enabled state At initial reset this flag is set to 0 4 14 11 Programming notes 1 It is necessary to turn the OSC3 oscillation on prior to a dialing operation in tone mode because the tone mode uses the OSC3 3 58 MHz clock However it increases current consumption Therefore turn the OSC3 oscillation off after finishing the dialling operation in tone mode 2 Do not write 0 0000B to the IDP ...

Page 146: ...SK core block respectively RDETCP RDET comparison register EIRDET Interrupt mask register Data bus CDETCP CDET comparison register EIRDET Interrupt mask register IRDET Interrupt factor flag ICDET Interrupt factor flag RDET Ring detection bit CDET Carrier detection bit FSKON FSK control register TRXD7S TRXD0S Transmit receive data register ESIFS SIF 2 enable register OSC3 oscillation circuit FSK co...

Page 147: ...VSS TIP Inverted input terminal of the input amplifier RING Non inverted input terminal of the input amplifier FB Feedback output terminal of the input amplifier BPOUT Output terminal of the band pass filter CDIN Input terminal for carrier signal detection RDIN Input terminal for ring signal detection RDRC I O terminal for connecting an RC network VRFF Reference voltage 1 2VDD output terminal The ...

Page 148: ...5 R3 R6 R4 R1 R2 VREF VREF 500pF 500pF Fig 4 15 2 2 Circuit configuration when the internal feedback resistor is not used example of differential input The gain of the amplifier can be changed with external resistors A 500 kΩ resistor is recommended for R1 R2 R5 and R6 and approximately 200 kΩ for R3 and R4 The gain can be found with the following formula GAmp R5 R6 In case of R1 R2 R3 R4 R5 R6 R1...

Page 149: ...t mask register is set to 0 the interrupt will be masked However even in this case the interrupt factor flag is set to 1 when the interrupt condition is met Figure 4 15 3 1 shows the relationship between the detection bit and the comparison register Comparison register RDETCP 0 CDETCP 0 RDETCP 1 CDETCP 0 RDET CDET bit 1 Initial value Ring detection interrupt generation RDET 0 CDET 0 With the above...

Page 150: ...generation example for Bellcore 4 15 4 Inputting FSK data The FSK demodulator starts operating when 1 is written to FSKON FF66H D3 Normally it should be set to 0 to decrease current consumption if not necessary The following settings are necessary before starting the FSK demodulator operation 1 Setting the serial interface 2 The demodulated data is loaded to the data register of the serial interfa...

Page 151: ...ng 1 to OSCC 3 After waiting 5 msec or more switch the CPU operating clock from OSC1 to OSC3 by writing 1 to CLKCHG 4 Turn the FSK demodulator ON by writing 1 to FSKON 5 Enable the serial interface 2 to receive data by writing 1 to RXENS 6 Read data from TRXD0S TRXD7S after waiting for the receiving interrupt of the serial interface 2 After reading data reset the overrun error check by writing 1 t...

Page 152: ...hen being read 4 Depends on the input status of the RDIN terminal FSKON FSK demodulator control register FF66H D3 Turns the FSK demodulator ON and OFF When 1 is written ON When 0 is written OFF Reading Valid The FSK demodulator goes ON by writing 1 to FSKON At the same time the data input line of the serial interface 2 is switched from the P30 terminal to the FSK demodulator output The P3x termina...

Page 153: ...alling edge of the CDET signal When CDETCP is 0 the interrupt is generated at the rising edge At initial reset this register is set to 0 EIRDET EICDET Interrupt mask registers FFEAH D1 D0 Enables or disables the generation of an interrupt for the CPU When 1 is written Enabled When 0 is written Disabled Reading Valid EIRDET and EICDET are interrupt mask registers that respectively correspond to the...

Page 154: ...ently allow an adequate waiting time after turning ON the OSC3 oscillation before starting the FSK operation Note that the oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts 2 In order to decrease current consumption the FSK demodulator and the OSC3 oscillation circuit should be turned OFF when their operations are not necessary 3 When detect...

Page 155: ...s of the interrupt flag setting Also the interrupt mask register is not provided However it is possible to not generate NMI since software can stop the watchdog timer operation Figure 4 16 1 shows the configuration of the interrupt circuit Note After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the S...

Page 156: ... ISW1 EISW1 ISW10 EISW10 IPT0 EIPT0 IPT1 EIPT1 ISERS EISERS ISRCS EISRCS ISTRS EISTRS ISER EISER ISRC EISRC ISTR EISTR Interrupt vector generation circuit Program counter low order 4 bits INT Interrupt request NMI request Watchdog timer Interrupt factor flag Interrupt mask register Input comparison register Interrupt selection register Interrupt flag ID EID ICDET EICDET IRDET EIRDET K00 KCP00 SIK0...

Page 157: ...r 0 Programmable timer 0 counter 0 Serial interface 1 receive error Serial interface 1 receive completion Serial interface 1 transmit completion Serial interface 2 receive error Serial interface 2 receive completion Serial interface 2 transmit completion K00 K03 input falling edge or rising edge K10 K13 input falling edge or rising edge Clock timer 1 Hz falling edge Clock timer 2 Hz falling edge C...

Page 158: ...H D1 FFE2H D0 FFE3H D2 FFE3H D0 FFE3H D1 FFE8H D2 FFE8H D0 FFE8H D1 FFE4H D0 FFE5H D0 FFE 6H D3 FFE6H D2 FFE6H D1 FFE6H D0 FFE7H D1 FFE7H D0 Interrupt mask register 4 16 3 Interrupt vector When an interrupt request is input to the CPU the CPU begins interrupt processing After the program being executed is terminated the interrupt processing is executed in the following order 1 The content of the f...

Page 159: ...ammable timer 0 FFE7H 0 0 EISW1 EISW10 R R W 0 3 0 3 EISW1 EISW10 2 2 0 0 Enable Enable Mask Mask Unused Unused Interrupt mask register Stopwatch timer 1 Hz Interrupt mask register Stopwatch timer 10 Hz FFE3H 0 EISER EISTR EISRC R R W 0 3 EISER EISTR EISRC 2 0 0 0 Enable Enable Enable Mask Mask Mask Unused Interrupt mask register Serial I F 1 error Interrupt mask register Serial I F 1 transmit com...

Page 160: ...pletion Interrupt factor flag Serial I F 1 receive completion FFF4H 0 0 0 IK0 R R W 0 3 0 3 0 3 IK0 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unused Interrupt factor flag K00 K03 FFF8H 0 ISERS ISTRS ISRCS R R W 0 3 ISERS ISTRS ISRCS 2 0 0 0 R Yes W Reset R No W Invalid Unused Interrupt factor flag Serial I F 2 error Interrupt factor flag Serial I F 2 transmit completion Interrupt factor f...

Page 161: ...factor flags are set when the interrupt condition is established even if the interrupt mask registers are set to 0 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine...

Page 162: ...ircuits and control registers Circuit and item CPU CPU operating frequency LCD system voltage circuit SVD circuit FSK demodulator Control register HALT instruction CLKCHG OSCC LPWR SVDON FSKON Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation cir...

Page 163: ...ngs of SP1 and SP2 must be done as a pair Watchdog timer 1 When the watchdog timer is being used the software must reset it within 3 second cycles 2 Because the watchdog timer is set in operation state by initial reset set the watchdog timer to disabled state not used before generating an interrupt NMI if it is not used Oscillation circuit 1 It takes at least 5 msec from the time the OSC3 oscillat...

Page 164: ...occur when the signal is turned ON or OFF LCD driver 1 When a program that access no memory mounted area F050H F0FFH F150H F1FFH F201H F203H F24FH is made the operation is not guaranteed 2 Because at initial reset the contents of display memory and LC3 LC0 LCD contrast are undefined there is need to initialize by the software Furthermore take care of the registers LPWR and ALOFF because these are ...

Page 165: ...al interface mode in the transmit receive disabled status TXEN RXEN 0 2 Do not perform double trigger writing 1 to TXTRG RXTRG when the serial interface is in the transmitting receiving operation 3 In the clock synchronous mode since one clock line SCLK is shared for both transmitting and receiving transmitting and receiving cannot be performed simultaneously Half duplex only is possible in clock ...

Page 166: ... is written to the PAUSE bit FF14H D1 or the FLASH bit FF14H D0 FSK demodulator 1 When starting the FSK demodulator operation the OSC3 oscillation circuit must be turned ON and the CPU operating clock must be switched to the OSC3 clock The OSC3 oscillation circuit takes a maximum 5 msec for oscillation stabilization after turning the circuit ON Consequently allow an adequate waiting time after tur...

Page 167: ...the board pattern Reset Circuit The power on reset signal which is input to the RESET terminal changes depending on conditions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product When the built in pull up resistor is added to the RESET terminal by mask option take into consider ...

Page 168: ...ly near circuits that are sensitive to noise such as the oscillation unit OSC4 OSC3 VSS Large current signal line High speed signal line Prohibited pattern Precautions for Visible Radiation when bare chip is mounted Visible radiation causes semiconductor devices to change the electrical characteristics It may cause this IC to malfunction When developing products which use this IC consider the foll...

Page 169: ...k 1000p 1000p 10k 0 2µ 0 2µ 470k 33k 0 2µ 0 1µ 0 1µ LCD panel 40 17 CGC TEST V C1 V C23 V C4 V C5 DP TONE TIP RING FB RDIN RDRC V REF CDIN BPOUT Piezo Coil I O Input C1 C2 X tal CGX CR CGC CDC C1 C7 CP CRES Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Capacitor Capacitor RESET terminal capacitor 32 768 kHz CI Max 34 kΩ 5 25 pF 3 58 MHz 30 pF 30 pF 0 2 µF 1...

Page 170: ...to 70 65 to 150 260 C 10sec lead section 250 Unit V V V mA C C mW The permissible total output current is the sum total of the current average current that simultaneously flows from the output pin or is drawn in In case of plastic package QFP15 128pin 7 2 Recommended Operating Conditions Item Supply voltage Oscillation frequency SVD terminal input voltage Ta 20 to 70 C Symbol VDD fOSC1 fOSC3 SVD U...

Page 171: ...0 33 VOL1 0 1 VDD R00 03 R10 13 R20 23 RDRC P00 03 P10 13 P20 23 P30 33 VOH2 VC5 0 05V COM0 16 VOL2 VSS 0 05V VOH3 VC5 0 05V SEG0 39 VOL3 VSS 0 05V Item High level input voltage 1 High level input voltage 2 High level input voltage 3 Low level input voltage 1 Low level input voltage 2 Low level input voltage 3 Low level input voltage 4 High level input current Low level input current 1 Low level i...

Page 172: ...1 2 3 4 VSVD1 VSVD2 tSVD IOP V V µs µA µA µA µA µA µA µA mA mA mA mA Typ 1 07 1 05 100 3 8 19 300 800 15 6 2 5 2 0 2 5 1 5 2 20 2 20 2 20 2 20 2 20 2 30 2 40 2 50 2 60 2 70 2 80 2 90 3 00 3 10 3 20 3 30 0 95 1 5 4 10 150 600 1 4 1 2 1 8 1 0 Typ 0 93 0 85 1 0 5 Without panel load The SVD circuit is OFF OSCC 0 Please input the voltage which is within the range between VSS and VDD into the SVD termin...

Page 173: ...rmitted leak resistance Symbol Vsta Vstp CD f V f IC f CG Vhho Rleak Unit V V pF ppm ppm ppm V MΩ Max 10 10 Typ 14 20 Min 2 2 2 2 10 10 5 5 200 Condition tsta 3sec VDD tstp 10sec VDD Including the parasitic capacitance inside the IC in chip VDD 2 2 to 5 5V CG 5 to 25pF CG 5pF VDD Between OSC1 and VSS Unless otherwise specified VDD 3 0V VSS 0V fOSC1 32 768kHz CG 25pF CD built in Ta 20 to 70 C OSC3 ...

Page 174: ...C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Master mode SCLK OUT SOUT SIN VOH VOH VOL tsms tsmh tsmd VIH1 VIL1 VOL Slave mode SCLK IN SOUT SIN VIH1 VOH VOL tsss tssh tssd VIH1 VIL1 VIL1 3 Asynchronous system Item Start bit detection error time 1 Erroneous start bit detection range time 2 1 2 Symbol tsa1 tsa2 Unit s s Max t 16 10t 16 Typ Min 0 9t 16 Start bit detection error time is a logical d...

Page 175: ...579545 100 6 25 7 5 Min 1188 1188 2178 1280 2068 20 57 0 1 70 20 3 5 Value measured between TIP RING pin and BPOUT pin The following expressions can be used to calculate the typical values dBm of CDON and CDOFF when an external resistor RTR 10kΩ Typ is connected in series with the TIP pin and the RING pin In addition the following expressions can be used to calculate the sensitivity of CDON and CD...

Page 176: ...s ms ms ms ms ms ms ms ms V mVrms mVrms mVrms mVrms dB dB kΩ Hz Hz Hz Hz Hz Hz Hz Hz ms ms ms Max 6 Typ 938 4 1 2 2 3 10 20 33 2 16 6 39 1 19 5 66 4 33 2 58 6 29 3 0 5 VDD VSS 92 168 122 224 2 5 2 5 701 32 771 45 857 17 935 10 1215 88 1331 68 1471 85 1645 01 94 Min 7 94 188 Condition Selected by software Selected by software 10pps M B 1 2 20pps M B 1 2 10pps M B 2 3 20pps M B 2 3 10pps M B 1 2 20p...

Page 177: ...ic Curves reference value High level output current Pxx Rxx BZ Ta 70 C Max value 0 0 0 1 2 3 4 5 6 7 8 0 2 0 4 0 6 VDD VOH V VDD 3 0 V VDD 5 0 V I OH mA 0 8 1 0 Low level output current Pxx Rxx BZ Ta 70 C Min value 1 0 0 2 4 6 8 10 12 14 0 8 0 6 0 4 VOL V VDD 3 0 V VDD 5 0 V I OL mA 0 2 0 0 ...

Page 178: ...t current SEGxx Ta 70 C Max value 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 0 2 0 4 0 6 VDD VOH V VDD 3 0 V VDD 5 0 V I OH mA 0 8 1 0 Low level output current SEGxx Ta 70 C Min value 1 0 2 0 1 8 1 6 1 4 1 2 1 0 0 8 0 6 0 4 0 2 0 0 0 8 0 6 0 4 VOL V VDD 3 0 V VDD 5 0 V I OL mA 0 2 0 0 ...

Page 179: ... PACKAGE CHAPTER 8 PACKAGE The dimensions are subject to change without notice 8 1 Plastic Package QFP15 128pin Unit mm 14 0 1 16 0 4 65 96 14 0 1 16 0 4 33 64 INDEX 0 16 32 1 128 97 1 4 0 1 0 1 1 7 max 1 0 5 0 2 0 10 0 125 0 4 0 1 0 05 0 05 0 025 ...

Page 180: ...170 EPSON S1C63558 TECHNICAL MANUAL CHAPTER 8 PACKAGE 8 2 Ceramic Package for Test Samples Unit mm 28 0 28 32 0 4 28 0 28 32 0 4 0 8 0 35 0 2 3 05max 0 8 0 2 0 15 65 96 33 64 32 1 128 97 INDEX ...

Page 181: ...SON 171 CHAPTER 9 PAD LAYOUT CHAPTER 9 PAD LAYOUT 9 1 Diagram of Pad Layout Chip thickness 400 µm Pad opening 100 µm X Y 0 0 4 01 mm 4 50 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 90 85 95 100 105 110 115 120 122 Die No ...

Page 182: ... 1557 1419 1280 1164 1049 933 818 702 587 471 356 240 125 9 106 222 337 453 568 684 799 915 1030 1146 1261 1400 1538 1677 1815 No 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pad name SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 S...

Page 183: ...llès SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 4F Bldg 27 No 69 Gui Jing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 43...

Page 184: ...ursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 185: ...http www epsondevice com Technical Manual S1C63558 EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue November 1998 Printed October 2001 in Japan A L M ...

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