Epson S1C63000 Core Cpu Manual Download Page 51

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S1C63000 CORE CPU MANUAL

EPSON

CHAPTER 4: INSTRUCTION SET

XOR

%A,%A

%A,%B

%A,imm4

%A,[%X]

%A,[%X]+

%A,[%Y]

%A,[%Y]+

XOR

%B,%A

%B,%B

%B,imm4

%B,[%X]

%B,[%X]+

%B,[%Y]

%B,[%Y]+

XOR

%F,imm4

XOR

[%X],%A

[%X],%B

[%X],imm4

[%X]+,%A

[%X]+,%B

[%X]+,imm4

XOR

[%Y],%A

[%Y],%B

[%Y],imm4

[%Y]+,%A

[%Y]+,%B

[%Y]+,imm4

BIT

%A,%A

%A,%B

%A,imm4

%A,[%X]

%A,[%X]+

%A,[%Y]

%A,[%Y]+

BIT

%B,%A

%B,%B

%B,imm4

%B,[%X]

%B,[%X]+

%B,[%Y]

%B,[%Y]+

BIT

[%X],%A

[%X],%B

[%X],imm4

[%X]+,%A

[%X]+,%B

[%X]+,imm4

BIT

[%Y],%A

[%Y],%B

[%Y],imm4

[%Y]+,%A

[%Y]+,%B

[%Y]+,imm4

CLR

[00addr6],imm2

[FFaddr6],imm2

SET

[00addr6],imm2

[FFaddr6],imm2

TST

[00addr6],imm2

[FFaddr6],imm2

1 1 0 1 1 1 1 1 1 0 0 0 X

1 1 0 1 1 1 1 1 1 0 0 1 X

1 1 0 1 1 1 1 0 0 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 0 0 0 0

1 1 0 1 1 1 1 1 0 0 0 0 1

1 1 0 1 1 1 1 1 0 0 0 1 0

1 1 0 1 1 1 1 1 0 0 0 1 1

1 1 0 1 1 1 1 1 1 0 1 0 X

1 1 0 1 1 1 1 1 1 0 1 1 X

1 1 0 1 1 1 1 0 1 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 0 1 0 0

1 1 0 1 1 1 1 1 0 0 1 0 1

1 1 0 1 1 1 1 1 0 0 1 1 0

1 1 0 1 1 1 1 1 0 0 1 1 1

1 0 0 0 0 1 0 1 0 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 1 0 0 0

1 1 0 1 1 1 1 1 0 1 1 0 0

1 1 0 1 1 1 0 0 0 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 1 0 0 1

1 1 0 1 1 1 1 1 0 1 1 0 1

1 1 0 1 1 1 0 0 1 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 1 0 1 0

1 1 0 1 1 1 1 1 0 1 1 1 0

1 1 0 1 1 1 0 1 0 i3 i2 i1 i0

1 1 0 1 1 1 1 1 0 1 0 1 1

1 1 0 1 1 1 1 1 0 1 1 1 1

1 1 0 1 1 1 0 1 1 i3 i2 i1 i0

1 1 0 1 0 1 1 1 1 0 0 0 X

1 1 0 1 0 1 1 1 1 0 0 1 X

1 1 0 1 0 1 1 0 0 i3 i2 i1 i0

1 1 0 1 0 1 1 1 0 0 0 0 0

1 1 0 1 0 1 1 1 0 0 0 0 1

1 1 0 1 0 1 1 1 0 0 0 1 0

1 1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 1 0 1 1 1 1 0 1 0 X

1 1 0 1 0 1 1 1 1 0 1 1 X

1 1 0 1 0 1 1 0 1 i3 i2 i1 i0

1 1 0 1 0 1 1 1 0 0 1 0 0

1 1 0 1 0 1 1 1 0 0 1 0 1

1 1 0 1 0 1 1 1 0 0 1 1 0

1 1 0 1 0 1 1 1 0 0 1 1 1

1 1 0 1 0 1 1 1 0 1 0 0 0

1 1 0 1 0 1 1 1 0 1 1 0 0

1 1 0 1 0 1 0 0 0 i3 i2 i1 i0

1 1 0 1 0 1 1 1 0 1 0 0 1

1 1 0 1 0 1 1 1 0 1 1 0 1

1 1 0 1 0 1 0 0 1 i3 i2 i1 i0

1 1 0 1 0 1 1 1 0 1 0 1 0

1 1 0 1 0 1 1 1 0 1 1 1 0

1 1 0 1 0 1 0 1 0 i3 i2 i1 i0

1 1 0 1 0 1 1 1 0 1 0 1 1

1 1 0 1 0 1 1 1 0 1 1 1 1

1 1 0 1 0 1 0 1 1 i3 i2 i1 i0

1 0 1 0 0 i1 i0 a5 a4 a3 a2 a1 a0

1 0 1 0 1 i1 i0 a5 a4 a3 a2 a1 a0

1 0 1 1 0 i1 i0 a5 a4 a3 a2 a1 a0

1 0 1 1 1 i1 i0 a5 a4 a3 a2 a1 a0

1 0 0 1 0 i1 i0 a5 a4 a3 a2 a1 a0

1 0 0 1 1 i1 i0 a5 a4 a3 a2 a1 a0

↓

– –

↑

↓

– –

↓

– –

↓

– –

●

↓

– –

↓

– –

●

↓

– –

↓

– –

↓

– –

↑

↓

– –

↓

– –

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↓

– –

↓

– –

●

↓

– –

↓

– –

●

↓

– –

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↓

– –

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↓

– –

↓

– –

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– –

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– –

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↓

– –

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↓

– –

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↓

– –

↓

– –

↓

– –

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– –

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– –

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– –

↓

– –

↓

– –

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↓

– –

●

↓

– –

●

↓

– –

↓

– –

↓

– –

↓

– –

↓

– –

↓

– –

↓

– –

↓

– –

↓

– –

←

∀

←

∀

←

∀

imm4

←

∀

[X]

←

∀

[X], X

←

X+1

←

∀

[Y]

←

∀

[Y], Y

←

Y+1

←

∀

←

∀

←

∀

imm4

←

∀

[X]

←

∀

[X], X

←

X+1

←

∀

[Y]

←

∀

[Y], Y

←

Y+1

←

∀

imm4

[X]

←

[X]

∀

[X]

←

[X]

∀

[X]

←

[X]

∀

imm4

[X]

←

[X]

∀

A, X

←

X+1

[X]

←

[X]

∀

B, X

←

X+1

[X]

←

[X]

∀

imm4, X

←

X+1

[Y]

←

[Y]

∀

[Y]

←

[Y]

∀

[Y]

←

[Y]

∀

imm4

[Y]

←

[Y]

∀

A, Y

←

Y+1

[Y]

←

[Y]

∀

B, Y

←

Y+1

[Y]

←

[Y]

∀

imm4, Y

←

Y+1

∧

imm4

∧

[X]

∧

[X], X

←

X+1

∧

[Y]

∧

[Y], Y

←

Y+1

∧

imm4

∧

[X]

∧

[X], X

←

X+1

∧

[Y]

∧

[Y], Y

←

Y+1

[X]

∧

[X]

∧

[X]

∧

imm4

[X]

∧

A, X

←

X+1

[X]

∧

B, X

←

X+1

[X]

∧

imm4, X

←

X+1

[Y]

∧

[Y]

∧

[Y]

∧

imm4

[Y]

∧

A, Y

←

Y+1

[Y]

∧

B, Y

←

Y+1

[Y]

∧

imm4, Y

←

Y+1

[00addr6]

←

[00addr6]

∧

not (2

imm2

)

[FFaddr6]

←

[FFaddr6]

∧

not (2

imm2

)

[00addr6]

←

[00addr6]

∧

imm2

)

[FFaddr6]

←

[FFaddr6]

∧

imm2

)

[00addr6]

∧

imm2

)

[FFaddr6]

∧

imm2

)

Mnemonic

Machine code

Operation

Cycle

Page

Flag

EXT.

mode

E I C Z

11 10 9 8 7 6 5 4 3 2 1 0

ALU logic operation (2/2)

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↔ ↔ ↔ ↔

↔
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139

140

141

139

140

141

140

142

143

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142

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131

139

Summary of Contents for S1C63000

Page 1: ...MF855 03 Core CPU Manual CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63000 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...ual versions are not written in the manuals Previous No E0C63158 E0C63256 E0C63358 E0C63P366 E0C63404 E0C63406 E0C63408 E0C63F408 E0C63454 E0C63455 E0C63458 E0C63466 E0C63P466 New No S1C63158 S1C63256 S1C63358 S1C6P366 S1C63404 S1C63406 S1C63408 S1C6F408 S1C63454 S1C63455 S1C63458 S1C63466 S1C6P466 S1C63 Family peripheral products Previous No E0C63467 E0C63557 E0C63558 E0C63567 E0C63F567 E0C63658 ...

Page 4: ......

Page 5: ...U 4 2 1 2 Register configuration 4 2 1 3 Flags 5 2 1 4 Arithmetic operations with numbering system 7 2 1 5 EXT register and data extension 8 2 2 Program Memory 11 2 2 1 Configuration of program memory 11 2 2 2 PC program counter 11 2 2 3 Branch instructions 12 2 2 4 Table look up instruction 16 2 3 Data Memory 17 2 3 1 Configuration of data memory 17 2 3 2 Addressing for data memory 18 2 3 3 Stack...

Page 6: ...EEP status 31 CHAPTER 4 INSTRUCTION SET 33 4 1 Addressing Mode 33 4 1 1 Basic addressing modes 33 4 1 2 Extended addressing mode 35 4 2 Instruction List 37 4 2 1 Function classification 37 4 2 2 Symbol meanings 38 4 2 3 Instruction list by function 40 4 2 4 List in alphabetical order 48 4 2 5 List of extended addressing instructions 55 4 3 Instruction Formats 59 4 4 Detailed Explanation of Instruc...

Page 7: ...er 2 16 bits Address extension register 8 bits Program counter 16 bits Stack pointer 2 8 bits Condition flag 4 bits Queue register 16 bits Interrupt function NMI Non Maskable Interrupt vector 1 Hardware interrupt vector Maximum 15 vectors Software interrupt vector Maximum 63 vectors Standby function HALT SLEEP Peripheral circuit interface Memory mapped I O method Pipeline processing 2 stages fetch...

Page 8: ...age Clock input Inputs the system clock from the peripheral circuit 2 phase divided clock output Outputs the 2 phase divided signals to be generated from the system clock input to the CLK terminal as following phase Instruction address output Outputs an instruction code ROM address Data address output Outputs a data RAM I O address CLK PK PL 1 cycle PC 16 QUEUE 16 X 16 Y 16 SP2 8 SP1 8 DATA ADDRES...

Page 9: ...Non maskable interrupt request An interrupt request terminal for an interrupt that cannot be masked by software It is accepted at the falling edge of an input signal to this terminal Interrupt request An interrupt request terminal for interrupts that can be masked by software It is accepted by a low level signal input to this terminal Interrupt acknowledge Goes to a low level while executing an NM...

Page 10: ...ding to the operation result 2 1 2 Register configuration Figure 2 1 2 1 shows the register configuration of the S1C63000 Function classification Arithmetic Logic Rotate shift Mnemonic Operation Addition Addition with carry Subtraction Subtraction with carry Comparison Increment adds 1 Decrement subtracts 1 Logical product Logical sum Exclusive OR Bit test Bit clear Bit set Bit test Rotate to left...

Page 11: ...t data accessing and it is used to operate stack in 1 word 4 bit unit See Section 2 3 3 Stack and stack pointer for details of the stack operation EXT register The EXT register is an 8 bit data register that is used when an address or data is extended into 16 bits See Section 2 1 5 EXT register and data extension for details F register The F register includes 4 bits of flags Z and C flags that are...

Page 12: ... except for NMI are disabled Furthermore when a hardware interrupt including the NMI is generated the I flag is reset to 0 and interrupts after that point are disabled The multiple interrupts can be accepted by setting the I flag to 1 in the interrupt processing routine The NMI non maskable interrupt is accepted regardless of the I flag setting The software interrupts are accepted regardless of th...

Page 13: ...ster B register A register B register E I C Z 0010B 2 0111B 7 0001B 1 0 1 0 0101B 5 0011B 3 0000B 0 0 1 1 Example 2 Decimal subtractio SBC B A 10 C flag is 0 before operation Setting value Result F register B register A register B register E I C Z 1001B 9 0111B 7 0010B 2 0 0 0 0001B 1 0010B 2 1001B 9 0 1 0 Example 3 3 digit BCD down counter LDB EXT 0 Counter base address 0010H LD XL 0x10 LDB X 0 I...

Page 14: ...nstruction which permits the extended addressing to extend the data using the EXT register These instructions are specified in Instruction List and Detailed Explanation of Instructions Make sure of the instructions when programming Note Do not use instructions see Instruction List which are invalid for the extended addressing when the E flag is set to 1 Do not use them following instructions that ...

Page 15: ...necessary to pay the same attention when returning the F register using the POP F instruction 2 Extension with E flag The following explains the instructions that can be executed when the E flag is set to 1 and its operation Modifying the indirect addressing with the X and Y registers for 4 bit data access The indirect addressing instructions which contain X or Y as an operand and accesses 4 bit d...

Page 16: ...hen the Y register is used Note The CMP instruction performs a subtraction with a complement therefore it is necessary to set the complement 1 s complement of the high order 8 bit data in the EXT register EXT register FFH High order 8 bit data Extending branch addresses The following PC relative branch instructions which have a signed 8 bit relative address as the operand permit extended addressin...

Page 17: ...ection 3 5 Interrupts for details of the interrupts The address 0111H to 013FH is the software interrupt vector s area Up to 63 software interrupts can be set up together with the hardware interrupt vector area Set branch instructions to the interrupt service routines in this area similarly to the hardware interrupts Addresses from 0000H to 00FFH and from 0140H to FFFFH are program area A call ins...

Page 18: ...gn8 specified in the operand as a signed 8 bit relative address The range that can be branched is from the next instruction address 128 to 127 A value within the range from 128 to 127 should be used if specifying a value for jumping in the assembler Generally branch destination labels such as JR LABEL are used and they are expanded into the actual address by the assembler These instructions permit...

Page 19: ...ddress within 0000H to 003FH in which the content specifies a 4 bit relative address JR addr6 This instruction branches the program sequence with the content of the data memory specified by the addr6 as an unsigned 4 bit relative address The operand addr6 can specify a data memory address within 0000H to 003FH The range that can be branched is from the next instruction address 0 to 15 absolute val...

Page 20: ...anches to the specified address Generally common subroutines that are called from two or more modules are placed in this area when the program is developed as multiple modules Example CALZ 0x50 Calls the subroutine located at the address 0050H See Section 2 3 3 Stack and stack pointer for stack PC relative call instructions CALR The PC relative call instruction adds the relative address specified ...

Page 21: ... specify a data memory address within 0000H to 003FH The range that can be branched is from the next instruction address 0 to 15 Same with the JR addr6 this call instruction can be used as a conditional call according to the flags that are set in the memory specified with addr6 Example When the content of the address 0010H is 4 0100B SET 0x0010 0 Sets the bit 0 in the address 0010H to 1 0010H 5 CA...

Page 22: ...The software interrupt instruction INT imm6 specifies a vector address within the addresses from 0111H to 013FH to execute its interrupt service routine It can also call a hardware interrupt service routine because it can specify an address from 0100H It performs the same operation with the call instruction but the F register is also saved into the stack before branching Consequently the RETI inst...

Page 23: ...ry map of the S1C63000 Fig 2 3 1 1 S1C63000 data memory map The S1C63000 can access 64K word space linearly without any of the page management commonly used in current 4 bit microcomputers The S1C63000 has a built in 16 bit data bus for the address stack SP1 and a RAM that permits 16 bit data accessing can be connected to the addresses 0000H to 03FFH The 16 bit accessible area is different dependi...

Page 24: ...addressing in this area the EXT register and an indirect instruction with the X register X are used To access this area first write an 8 bit low order address 00H to FFH in the EXT register then execute an indirect addressing instruction with an operand X only the instruction that permits the extended addressing In this case the content of the X register does not affect the address to be accessed ...

Page 25: ...bit data accessing Fig 2 3 3 1 SP1 configuration As shown in the figure the D0 D1 and D10 D15 within the 16 bits are fixed at 0 8 bits of the D2 D9 can be set by software Furthermore the hardware also operates for this 8 bit field Therefore ad dressing by the SP1 is done in 4 word units and a 16 bit address data can be transferred in one accessing Since the SP1 performs 16 bit data accessing this ...

Page 26: ...r POP Y instructions are executed the data retained in the queue register is returned to the PC X register or Y register Since the SP1 is incremented the content of the queue register is renewed it generates a bus cycle to load the content of the memory SP1 1 to the queue register 3 When the LDB SP1 BA INC SP1 or DEC SP1 instructions are executed When these instructions are executed the content of...

Page 27: ...am so that the stacks do not cross over the upper lower limits of the mounted memory The SP1 must be set in the RAM area that permits 16 bit accessing depending on the model The SP1 address stack cannot be allocated to other than the 16 bit accessible area even if the address is less than 03FFH The area management for the SP1 stack SP2 stack and data RAM should be done by the user Pay attention to...

Page 28: ...cycle The number of cycles which is stated in the instruction list indicates the number of bus cycles 3 2 Instruction Fetch and Execution The S1C63000 executes the instructions indicated with the PC program counter one by one That operation for an instruction is divided into two stages one is a fetch cycle to read an instruction and another is an execution cycle to execute the instruction that has...

Page 29: ... write Memory read 3 3 2 High impedance control The data bus goes to a high impedance during an execution cycle that accesses only the internal registers in the CPU During the bus cycle period both the read signal RD and write signal WR are fixed at a high level and a dummy address is output on the address bus CLK PK PL DA00 DA15 WR RD D0 D3 DBS1 DBS0 T1 T2 T3 T4 Bus cycle Dummy address Fig 3 3 2 ...

Page 30: ...upt is generated CLK PK PL DA00 DA15 RDIV WR RD D0 D3 DBS1 DBS0 T1 T2 T3 T4 Bus cycle Dummy address Interrupt vector CLaK PK PL DA00 DA15 WR RD D0 D3 BS16 DBS1 DBS0 T1 T2 T3 T4 Bus cycle Address Write data a During 4 bit data access b During 16 bit data access Fig 3 3 4 1 Bus cycle during memory write Fig 3 3 3 1 Bus cycle during reading interrupt vector 3 3 4 Memory write In an execution cycle th...

Page 31: ... 4 bit data access b During 16 bit data access Fig 3 3 5 1 Bus cycle during memory read 3 4 Initial Reset The S1C63000 has a reset SR terminal in order to start the program after initializing the circuit when the power is turned on or other situations The following explains the operation at an initial reset and the initial setting of the internal registers 3 4 1 Initial reset sequence The S1C63000...

Page 32: ... of a peripheral circuit operation When the CPU accepts an interrupt request that is sent by the hardware the CPU stops executing the current sequence of the program and shifts into the interrupt processing When all the interrupt processing has finished the interrupted program is resumed The S1C63000 has the hardware interrupt function for the peripheral circuits including an NMI non maskable inte...

Page 33: ...ster into the stack indicated by the SP2 then resets the I flag to 0 to prohibit following interrupts excluding NMI Bus cycle 3 Sets the data bus status DBS1 DBS0 to 01B Then turns the vector read signal RDIV low and reads the interrupt vector 4 bits output from the peripheral circuit to the data bus When NMI is generated this cycle becomes a dummy cycle because the interrupt vector is fixed at 01...

Page 34: ... 5 DUMMY 0100H ANY pc 3 pc 1 0100H ANY 2 1 2 ANY pc SP2 1 DUMMY SP1 1 F reg ANY pc Interrupt processing by the hardware Interrupt sampling ANY LD A X 0 3 ANY 00xxH pc 2 LDB EXT imm8 ANY 00xxH DUMMY Interrupt sampling Executing the interrupt service routine Fig 3 5 2 1 NMI sequence normal acceptance Fig 3 5 2 2 NMI sequence interrupt acceptance after 1 instruction CLK PK PL PC FETCH BS16 DBS1 0 WR ...

Page 35: ...t vector CLK PK PL PC FETCH BS16 DBS1 0 WR RD RDIV DA00 DA15 D0 D3 M00 M15 IRQ IACK NACK IF 0 1 2 3 4 5 ANY ANY DUMMY 010xH ANY pc 2 pc 1 010xH ANY ANY 2 1 2 ANY pc SP2 1 DUMMY SP1 1 ANY F reg xH pc Interrupt processing by the hardware Executing the interrupt service routine 4 6 cycle Interrupt sampling Inte rrupt vector Fig 3 5 2 3 Hardware interrupt IRQ sequence normal acceptance Fig 3 5 2 4 Har...

Page 36: ...SP1 and SP2 in the initialize routine Further when re setting the stack pointer the SP1 and SP2 must be set as a pair When one of them is set all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set 2 The interrupt processing is the same as a subroutine call that branches to the interrupt vector address At that time the F register is evacuated into t...

Page 37: ... Th2 states are continuously inserted During this period interrupt sampling is done at the falling edge of the Th2 state and the generation of an interrupt factor causes it to shift to the interrupt processing Fig 3 6 1 1 Sequence of shifting to HALT status and restarting 3 6 2 SLEEP status The SLEEP status is the status in which the CPU and the peripheral circuits within the MCU stop operat ing a...

Page 38: ... oscillation circuit begins to oscillate When the oscillation starts the CLK input to the CPU is masked by the peripheral circuit and the input to the CPU begins after stabilization waiting time several 10 msec several msec has elapsed The CPU samples the interrupt at the falling edge of the initially input CLK and starts the interrupt processing OSC CLK PK PL PC FETCH DBS1 0 STOP IRQ T1 SLP pc 0 ...

Page 39: ...he instruction Immediate data addressing The immediate data addressing is the addressing mode in which the immediate data is used for operations and is used as transfer data Values that are specified in the operand are directly used as data or addresses In the instruction list the following symbols are used to write immediate data Table 4 1 1 1 Symbol and size of immediate data Symbol imm2 imm4 im...

Page 40: ...er after executing the transfer or operation This function is useful to access a continuous addresses in the data memory Examples SUB A X Subtracts the content of a memory specified with the X register from the A register LD X Y Transfers the content of a memory specified with the Y register to a memory specified with the X register Then increments the contents of the X register and Y register 6 b...

Page 41: ...ions JR sign8 JRC sign8 JRNC sign8 JRZ sign8 JRNZ sign8 Call instruction CALR sign8 4 1 2 Extended addressing mode In the S1C63000 when data is written to the EXT register the E flag is set and a specific instruction follows the data specified by that instruction is extended with the EXT register data see Section 2 1 5 When the E flag is set instructions are extended in an addressing mode differen...

Page 42: ...which has X or Y as the source operand or the destination operand When X is used the memory from 0000H to 00FFH can be accessed and when Y is used FF00H to FFFFH can be accessed Instructions that operate in the 8 bit absolute addressing mode with the E flag Instruction Operand LD r X r Y X r Y r X imm4 Y imm4 EX r X r Y ADD r X r Y X r Y r X imm4 Y imm4 ADC r X r Y X r Y r X imm4 Y imm4 B X n4 B Y...

Page 43: ...n classification Table 4 2 1 1 lists the function classifications of the instructions Table 4 2 1 1 Instruction function classifications Function classification Arithmetic Logic Transfer Mnemonic Operation Addition Addition with carry Subtraction Subtraction with carry Comparison Increment adds 1 Decrement subtracts 1 Logical product Logical sum Exclusive OR Bit test Bit clear Bit set Bit test Loa...

Page 44: ...er the setting data is 8 bits of D0 to D7 PC Program counter PC 16 bits In the notation with mnemonics the register names should be written with a placed in front of them according to the S1C63 Family assembler source format A A register B B register BA BA register X X register XH XH register XL XL register Y Y register YH YH register YL YL register F F register EXT EXT register SP1 Stack pointer ...

Page 45: ...FFFFH where the addr6 specifies SP1 SP1 16 bit address stack where the SP1 specifies SP2 SP2 4 bit data stack where the SP2 specifies Flags Z Zero flag C Carry flag I Interrupt flag E Extension flag Flag is set Flag is reset Flag is set or reset Flag is not changed Operations and others Addition Subtraction Logical product Logical sum Exclusive OR Data load Data exchange Extended addressing mode E...

Page 46: ... 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 1 0 i3 i2 i1 i0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 i3 i2 i1 i0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1...

Page 47: ... 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 i3 i2 i1 i0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 1 i3 i2 i1 i0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 i3 i2 i1 i0 1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 i3 i2 i1 i0 1 1 0 0...

Page 48: ...1 1 0 1 1 1 0 0 0 1 0 0 1 i3 i2 i1 i0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 i3 i2 i1 i0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 1 0 1 1 i3 i2 i1 i0 1 1 1 1 0 0 1 1 1 X 0 0 0 1 1 1 1 0 0 1 1 1 X 0 1 0 1 1 1 1 0 0 1 0 0 i3 i2 i1 i0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 ...

Page 49: ...1 1 0 1 1 10H n4 1 1 1 0 0 1 0 0 0 n3n2n1n0 1 1 1 0 0 1 0 0 1 n3n2n1n0 1 1 1 0 0 1 0 1 0 n3n2n1n0 1 1 1 0 0 1 0 1 1 n3n2n1n0 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 X A X B X imm4 X A X X 1 X B X X 1 X imm4 X X 1 Y A Y B Y imm4 Y A Y Y 1 Y B Y Y 1 Y imm4 Y Y 1 00addr6 00addr6 1 00addr6 00addr6 1 B N s adjust B A C B N s adjust B X C B N s adj...

Page 50: ... 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 X 1 1 0 1 1 0 1 1 1 0 1 1 X 1 1 0 1 1 0 1 0 1 i3 i2 i1 i0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 0 0 1 i3 i2 i1 i0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 i3 i2 i1 i0 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 i3 i2 i1 i0 1 1 0 1...

Page 51: ... 1 0 1 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 0 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 0 1 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 1 0 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0...

Page 52: ...A imm8 BA X BA Y LDB XL BA XL imm8 XH BA LDB YL BA YL imm8 YH BA LDB EXT BA EXT imm8 LDB SP1 BA SP2 BA LDB X BA X imm8 LDB Y BA ADD X BA X sign8 Y BA Y sign8 CMP X imm8 Y imm8 INC SP1 SP2 DEC SP1 SP2 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 X 1 1 1 1 1 1 1 0 0 1 1 0 X 1 1 1 1 1 1 1 0 0 1 1 1 X 0 1 0 0 1 i7 i6 i5...

Page 53: ...TI 0 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 a5a4a3a2a1a0 0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 0 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 0 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 0 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 1 1 1 1 1 1 1 1 1 0 0 1 X 0 0 0 1 1 i7 i6 i5 i4 i3 i2 i1 i0 0 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 1 1 1 1 1 0 0 a5a4a3a2a1a0 1 1 1 1 1 1 0 i5 i4 i3 i2 i...

Page 54: ...1 1 0 0 1 0 1 1 1 0 0 1 X 1 1 0 0 1 0 1 0 0 i3 i2 i1 i0 1 1 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 0 X 1 1 0 0 1 0 1 1 1 0 1 1 X 1 1 0 0 1 0 1 0 1 i3 i2 i1 i0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 X 0 1 1 0 0 s7 s6 s5 s4 s3 s2 ...

Page 55: ...0 1 1 0 1 1 1 1 1 1 0 1 0 0 0 1 1 i3 i2 i1 i0 1 1 0 1 0 1 1 1 1 0 0 0 X 1 1 0 1 0 1 1 1 1 0 0 1 X 1 1 0 1 0 1 1 0 0 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 X 1 1 0 1 0 1 1 1 1 0 1 1 X 1 1 0 1 0 1 1 0 1 i3 i2 i1 i0 1 1 0 1 0 1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 ...

Page 56: ... 1 1 0 0 0 1 1 i3 i2 i1 i0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 n3n2n1n0 1 1 1 0 0 1 0 0 1 n3n2n1n0 1 1 1 0 0 1 0 1 0 n3n2n1n0 1 1 1 0 0 1 0 1 1 n3n2n1n0 1 0 0 0 0 0 0 a5a4a3a2a1a0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 1 0 ...

Page 57: ... 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 i3 i2 i1 i0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 1 0 i3 i2 i1 i0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 i3 i2 i1 i0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 X 1...

Page 58: ...i0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 0 1 0 i3 i2 i1 i0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 i3 i2 i1 i0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 X 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1...

Page 59: ...0 1 1 1 0 1 1 1 0 0 0 1 1 0 n3n2n1n0 1 1 0 0 0 1 0 1 0 i3 i2 i1 i0 1 1 1 0 0 0 0 1 0 n3n2n1n0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 n3n2n1n0 1 1 0 0 0 1 0 1 1 i3 i2 i1 i0 1 1 1 0 0 0 0 1 1 n3n2n1n0 1 0 1 1 0 i1 i0 a5a4a3a2a1a0 1 0 1 1 1 i1 i0 a5a4a3a2a1a0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 2 2 1 1 2 2 2 2 1 1 2 2 2 2 1 1 1 1 1 1 1 1 2 1 1 1 2 1 2 1 ...

Page 60: ...0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 0 X 1 1 0 1 1 1 1 1 1 0 1 1 X 1 1 0 1 1 1 1 0 1 i3 i2 i1 i0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 i3 i2 i1 i0 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 0 0 i3 i2 i1 i0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 ...

Page 61: ...mm8 imm4 C Mnemonic Operation Flag E I C Z 8 bit absolute addressing 1 4 LDB EXT imm8 LD A X LDB EXT imm8 LD A Y LDB EXT imm8 LD B X LDB EXT imm8 LD B Y LDB EXT imm8 LD X A LDB EXT imm8 LD X B LDB EXT imm8 LD X imm4 LDB EXT imm8 LD Y A LDB EXT imm8 LD Y B LDB EXT imm8 LD Y imm4 LDB EXT imm8 EX A X LDB EXT imm8 EX A Y LDB EXT imm8 EX B X LDB EXT imm8 EX B Y LDB EXT imm8 ADD A X LDB EXT imm8 ADD A Y...

Page 62: ...onic Operation Flag E I C Z 8 bit absolute addressing 2 4 LDB EXT imm8 ADC Y A LDB EXT imm8 ADC Y B LDB EXT imm8 ADC Y imm4 LDB EXT imm8 SUB A X LDB EXT imm8 SUB A Y LDB EXT imm8 SUB B X LDB EXT imm8 SUB B Y LDB EXT imm8 SUB X A LDB EXT imm8 SUB X B LDB EXT imm8 SUB X imm4 LDB EXT imm8 SUB Y A LDB EXT imm8 SUB Y B LDB EXT imm8 SUB Y imm4 LDB EXT imm8 SBC A X LDB EXT imm8 SBC A Y LDB EXT imm8 SBC B...

Page 63: ...00imm8 A A FFimm8 B B 00imm8 B B FFimm8 00imm8 00imm8 A 00imm8 00imm8 B 00imm8 00imm8 imm4 Mnemonic Operation Flag E I C Z 8 bit absolute addressing 3 4 LDB EXT imm8 ADC B X n4 LDB EXT imm8 ADC B Y n4 LDB EXT imm8 ADC X B n4 LDB EXT imm8 ADC X 0 n4 LDB EXT imm8 ADC Y B n4 LDB EXT imm8 ADC Y 0 n4 LDB EXT imm8 SBC B X n4 LDB EXT imm8 SBC B Y n4 LDB EXT imm8 SBC X B n4 LDB EXT imm8 SBC X 0 n4 LDB EXT...

Page 64: ...D3 D2 D1 D0 C FFimm8 C D3 D2 D1 D0 C Mnemonic Operation Flag E I C Z 8 bit absolute addressing 4 4 LDB EXT imm8 OR Y A LDB EXT imm8 OR Y B LDB EXT imm8 OR Y imm4 LDB EXT imm8 XOR A X LDB EXT imm8 XOR A Y LDB EXT imm8 XOR B X LDB EXT imm8 XOR B Y LDB EXT imm8 XOR X A LDB EXT imm8 XOR X B LDB EXT imm8 XOR X imm4 LDB EXT imm8 XOR Y A LDB EXT imm8 XOR Y B LDB EXT imm8 XOR Y imm4 LDB EXT imm8 BIT A X L...

Page 65: ...If C 1 then PC PC sign16 1 sign16 32767 32768 If C 0 then PC PC sign16 1 sign16 32767 32768 If Z 1 then PC PC sign16 1 sign16 32767 32768 If Z 0 then PC PC sign16 1 sign16 32767 32768 SP1 1 4 3 SP1 1 4 PC 1 SP1 SP1 1 PC PC sign16 1 sign16 32767 32768 Mnemonic Operation Flag E I C Z signed 16 bit PC relative addressing LDB EXT imm8 JR sign8 LDB EXT imm8 JRC sign8 LDB EXT imm8 JRNC sign8 LDB EXT imm...

Page 66: ...valid ADC r r 4 4 Detailed Explanation of Instructions This section explains the individual instructions in alphabetic order according to the following format View of the explanation Number of bus cycles Mnemonic meaning Mnemonic Function explanation Mnemonic and object codes Addressing mode Src indicates the source and Dst indicates the destination The meaning of the symbols are the same as for t...

Page 67: ...2 i1 i0 19D0H 19DFH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Invalid Add with carry r reg to r reg 1 cycle Function r r r C Adds the content of the r register A or B and carry C to the r register A or B Code Mnemonic MSB LSB ADC A A 1 1 0 0 1 1 1 1 1 0 0 0 X 19F0H 19F1H ADC A B 1 1 0 0 1 1 1 1 1 0 0 1 X 19F2H 19F3H ADC B A 1 1 0 0 1 1 1 1 1 0 1 0 X 19F4H 19F5H ...

Page 68: ...X r r 00imm8 C 00imm8 0000H 00H to FFH LDB EXT imm8 ADC r Y r r FFimm8 C FFimm8 FF00H 00H to FFH ADC r ir Add with carry location ir reg to r reg and increment ir reg 1 cycle Function r r ir C ir ir 1 Adds the content of the data memory addressed by the ir register X or Y and carry C to the r register A or B Then increments the ir register X or Y The flags change due to the operation result of the...

Page 69: ...mm8 00imm8 r C 00imm8 0000H 00H to FFH LDB EXT imm8 ADC Y r FFimm8 FFimm8 r C FFimm8 FF00H 00H to FFH ADC ir r Add with carry r reg to location ir reg and increment ir reg 2 cycles Function ir ir r C ir ir 1 Adds the content of the r register A or B and carry C to the data memory addressed by the ir register X or Y Then increments the ir register X or Y The flags change due to the operation result...

Page 70: ...C X imm4 00imm8 00imm8 imm4 C 00imm8 0000H 00H to FFH LDB EXT imm8 ADC Y imm4 FFimm8 FFimm8 imm4 C FFimm8 FF00H 00H to FFH Add with carry immediate data imm4 to location ir reg and increment ir reg 2 cycles Function ir ir imm4 C ir ir 1 Adds the immediate data imm4 and carry C to the data memory addressed by the ir register X or Y Then increments the ir register X or Y The flags change due to the ...

Page 71: ... ADC B ir n4 Add with carry location ir reg to B reg in specified radix 2 cycles Function B N s adjust B ir C Adds the content of the data memory addressed by the ir register X or Y and carry C to the B register The operation result is adjusted with n4 as the radix The C flag is set by a carry according to the radix Code Mnemonic MSB LSB ADC B X n4 1 1 1 0 1 1 1 0 0 10H n4 1DC0H 1DCFH ADC B Y n4 1...

Page 72: ...B EXT imm8 ADC Y B n4 FFimm8 N s adjust FFimm8 B C FFimm8 FF00H 00H to FFH Note n4 should be specified with a value from 1 to 16 Add with carry location ir reg to B reg in specified radix and increment ir reg 2 cycles Function B N s adjust B ir C ir ir 1 Adds the content of the data memory addressed by the ir register X or Y and carry C to the B register The operation result is adjusted with n4 as...

Page 73: ...c Register direct Dst Register indirect Extended addressing Invalid Note n4 should be specified with a value from 1 to 16 ADC ir 0 n4 Add carry to location ir reg in specified radix 2 cycles Function ir N s adjust ir 0 C Adds the carry C to the data memory addressed by the ir register X or Y The operation result is adjusted with n4 as the radix The C flag is set by a carry according to the radix T...

Page 74: ...ment ir reg 2 cycles Function ir N s adjust ir 0 C ir ir 1 Adds the carry C to the data memory addressed by the ir register X or Y The operation result is adjusted with n4 as the radix Then increments the ir register X or Y The flags change due to the operation result of the data memory and the increment result of the ir register does not affect the flags The C flag is set by a carry according to ...

Page 75: ...nded addressing Invalid ADD r ir Add location ir reg to r reg 1 cycle Function r r ir Adds the content of the data memory addressed by the ir register X or Y to the r register A or B Code Mnemonic MSB LSB ADD A X 1 1 0 0 1 0 1 1 0 0 0 0 0 1960H ADD A Y 1 1 0 0 1 0 1 1 0 0 0 1 0 1962H ADD B X 1 1 0 0 1 0 1 1 0 0 1 0 0 1964H ADD B Y 1 1 0 0 1 0 1 1 0 0 1 1 0 1966H Flags E I C Z Mode Src Register ind...

Page 76: ...1 1 0 0 1 0 1 1 0 0 1 0 1 1965H ADD B Y 1 1 0 0 1 0 1 1 0 0 1 1 1 1967H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid ADD ir r Add r reg to location ir reg 2 cycles Function ir ir r Adds the content of the r register A or B to the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB ADD X A 1 1 0 0 1 0 1 1 0 1 0 0 0 1968H ADD X B 1 1 0 0 ...

Page 77: ... 1 196DH ADD Y A 1 1 0 0 1 0 1 1 0 1 0 1 1 196BH ADD Y B 1 1 0 0 1 0 1 1 0 1 1 1 1 196FH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid ADD ir imm4 Add immediate data imm4 to location ir reg 2 cycles Function ir ir imm4 Adds the 4 bit immediate data imm4 to the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB ADD X imm4 1 1 0 0 1 0 0 0...

Page 78: ... the flags Code Mnemonic MSB LSB ADD X imm4 1 1 0 0 1 0 0 0 1 i3 i2 i1 i0 1910H 191FH ADD Y imm4 1 1 0 0 1 0 0 1 1 i3 i2 i1 i0 1930H 193FH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid ADD ir BA Add BA reg to ir reg 1 cycle Function ir ir BA Adds the content of the BA register to the ir register X or Y This instruction does not affect the C flag regardless...

Page 79: ...mmediate data Dst Register direct Extended addressing Valid Extended LDB EXT imm8 operation ADD ir sign8 ir ir sign16 upper 8 bit imm8 lower 8 bit sign8 AND r r Logical AND of r reg and r reg 1 cycle Function r r r Performs a logical AND operation of the content of the r register A or B and the content of the r register A or B and stores the result in the r register Code Mnemonic MSB LSB AND A A 1...

Page 80: ...FH AND B imm4 1 1 0 1 0 0 1 0 1 i3 i2 i1 i0 1A50H 1A5FH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Invalid AND F imm4 Logical AND of immediate data imm4 and F reg 1 cycle Function F F imm4 Performs a logical AND operation of the 4 bit immediate data imm4 and the content of the F flag register and stores the result in the r register It is possible to reset any fla...

Page 81: ... 1A63H AND B X 1 1 0 1 0 0 1 1 0 0 1 0 1 1A65H AND B Y 1 1 0 1 0 0 1 1 0 0 1 1 1 1A67H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid Logical AND of location ir reg and r reg 1 cycle Function r r ir Performs a logical AND operation of the content of the data memory addressed by the ir register X or Y and the content of the r register A or B and stores the ...

Page 82: ...0imm8 00imm8 r 00imm8 0000H 00H to FFH LDB EXT imm8 AND Y r FFimm8 FFimm8 r FFimm8 FF00H 00H to FFH AND ir r Logical AND of r reg and location ir reg and increment ir reg 2 cycles Function ir ir r ir ir 1 Performs a logical AND operation of the content of the r register A or B and the content of the data memory addressed by the ir register X or Y and stores the result in that address Then incremen...

Page 83: ...m8 00imm8 imm4 00imm8 0000H 00H to FFH LDB EXT imm8 AND Y imm4 FFimm8 FFimm8 imm4 FFimm8 FF00H 00H to FFH AND ir imm4 Logical AND of immediate data imm4 and location ir reg and increment ir reg 2 cycles Function ir ir imm4 ir ir 1 Performs a logical AND operation of the 4 bit immediate data imm4 and the content of the data memory addressed by the ir register X or Y and stores the result in that ad...

Page 84: ... 0 1 1 1 1 0 1 0 X 1AF4H 1AF5H BIT B B 1 1 0 1 0 1 1 1 1 0 1 1 X 1AF6H 1AF7H Flags E I C Z Mode Src Register direct Dst Register direct Extended addressing Invalid BIT r imm4 Test bit of r reg with immediate data imm4 1 cycle Function r imm4 Performs a logical AND of the 4 bit immediate data imm4 and the content of the r register A or B to check the bits of the r register The Z flag is changed due...

Page 85: ...0 0 1 0 1 1AE5H BIT B Y 1 1 0 1 0 1 1 1 0 0 1 1 1 1AE7H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid Test bit of r reg with location ir reg 1 cycle Function r ir Performs a logical AND of the content of the data memory addressed by the ir register X or Y and the content of the r register A or B to check the bits of the r register The Z flag is changed du...

Page 86: ...Extended LDB EXT imm8 operation BIT X r 00imm8 r 00imm8 0000H 00H to FFH LDB EXT imm8 BIT Y r FFimm8 r FFimm8 FF00H 00H to FFH BIT ir r Test bit of location ir reg with r reg and increment ir reg 1 cycle Function ir r ir ir 1 Performs a logical AND of the content of the r register A or B and the content of the data memory addressed by the ir register X or Y to check the bits of the memory The Z fl...

Page 87: ... BIT Y imm4 1 1 0 1 0 1 0 1 1 i3 i2 i1 i0 1AB0H 1ABFH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid Test bit of location ir reg with immediate data imm4 1 cycle Function ir imm4 Performs a logical AND of the 4 bit immediate data imm4 and the content of the data memory addressed by the ir register X or Y to check the bits of the memory The Z flag is changed...

Page 88: ...FH Flags E I C Z Mode 6 bit absolute Extended addressing Invalid CALR sign8 Call subroutine at relative location sign8 1 cycle Function SP1 1 4 3 SP1 1 4 PC 1 SP1 SP1 1 PC PC sign8 1 sign8 128 127 Saves the address next to this instruction to the stack as a return address then adds the related address specified with the sign8 to that address to unconditionally call the subroutine started from the ...

Page 89: ...B CALZ imm8 0 0 0 1 1 i7 i6 i5 i4 i3 i2 i1 i0 0300H 03FFH Flags E I C Z Mode Immediate data Extended addressing Invalid CLR addr6 imm2 Clear bit imm2 in location addr6 2 cycles Function addr6 addr6 not 2imm2 addr6 0000H 003FH or FFC0H FFFFH Clears the bit specified with the imm2 in the data memory specified with the addr6 to 0 Code Mnemonic MSB LSB CLR 00addr6 imm2 1 0 1 0 0 i1 i0 a5 a4 a3 a2 a1 a...

Page 90: ... i0 1E50H 1E5FH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Invalid Compare r reg with r reg 1 cycle Function r r Subtracts the content of the r register A or B from the content of the r register A or B It changes the flags Z and C but does not change the content of the register Code Mnemonic MSB LSB CMP A A 1 1 1 1 0 0 1 1 1 X 0 0 0 1E70H 1E78H CMP A B 1 1 1 1 0 ...

Page 91: ...ng Valid Extended LDB EXT imm8 operation CMP r X r 00imm8 00imm8 0000H 00H to FFH LDB EXT imm8 CMP r Y r FFimm8 FFimm8 FF00H 00H to FFH Compare r reg with location ir reg and increment ir reg 1 cycle Function r ir ir ir 1 Subtracts the content of the data memory addressed by the ir register X or Y from the content of the r register A or B It changes the flags Z and C but does not change the conten...

Page 92: ...0 1 0 1 1 1E6BH CMP Y B 1 1 1 1 0 0 1 1 0 1 1 1 1 1E6FH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid Compare location ir reg with r reg 1 cycle Function ir r Subtracts the content of the r register A or B from the content of the data memory addressed by the ir register X or Y It changes the flags Z and C but does not change the content of the memory Code...

Page 93: ... CMP Y imm4 1 1 1 1 0 0 0 1 1 i3 i2 i1 i0 1E30H 1E3FH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid Compare location ir reg with immediate data imm4 1 cycle Function ir imm4 Subtracts the 4 bit immediate data imm4 from the content of the data memory addressed by the ir register X or Y It changes the flags Z and C but does not change the content of the memo...

Page 94: ...1 0 FFH imm8 0E00H 0EFFH CMP Y imm8 0 1 1 1 1 FFH imm8 0F00H 0FFFH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Valid Extended LDB EXT imm8 operation CMP ir imm8 ir imm16 upper 8 bit FFH imm8 lower 8 bit imm8 Decrement location addr6 2 cycles Function addr6 addr6 1 addr6 0000H 003FH Decrements 1 the content of the data memory addressed by the addr6 Code Mnemonic MS...

Page 95: ...FFH Note n4 should be specified with a value from 1 to 16 When 16 is specified for n4 the low order 4 bits of the machine code n3 n0 become 0000B DEC ir n4 Decrement location ir in specified radix and increment ir reg 2 cycles Function ir N s adjust ir 1 ir ir 1 Decrements 1 the content of the data memory addressed by the ir register X or Y The operation result is adjusted with n4 as the radix The...

Page 96: ...Flags E I C Z Mode Src Register direct Dst Register direct Extended addressing Invalid Decrement stack pointer 1 cycle Function sp sp 1 Decrements 1 the content of the stack pointer sp SP1 or SP2 This instruction does not change the C flag regardless of the operation result Code Mnemonic MSB LSB DEC SP1 1 1 1 1 1 1 1 1 0 0 0 0 0 1FE0H DEC SP2 1 1 1 1 1 1 1 1 0 0 1 0 0 1FE4H Flags E I C Z Mode Regi...

Page 97: ... Extended LDB EXT imm8 operation EX r X r 00imm8 00imm8 0000H 00H to FFH LDB EXT imm8 EX r Y r FFimm8 FFimm8 FF00H 00H to FFH EX r ir Exchange r reg and location ir reg and increment ir reg 2 cycles Function r ir ir ir 1 Exchanges the contents of the r register A or B and data memory addressed by the ir register X or Y Then increments the ir register X or Y The increment result of the ir register ...

Page 98: ...operate An interrupt causes it to return from HALT status to the normal program execution status Code Mnemonic MSB LSB HALT 1 1 1 1 1 1 1 1 1 1 1 0 0 1FFCH Flags E I C Z INC addr6 Increment location addr6 2 cycles Function addr6 addr6 1 addr6 0000H 003FH Increments 1 the content of the data memory addressed by the addr6 Code Mnemonic MSB LSB INC addr6 1 0 0 0 0 0 1 a5 a4 a3 a2 a1 a0 1040H 107FH Fl...

Page 99: ...8 0000H 00H to FFH LDB EXT imm8 INC Y n4 FFimm8 N s adjust FFimm8 1 FFimm8 FF00H 00H to FFH Note n4 should be specified with a value from 1 to 16 INC ir n4 Increment location ir in specified radix and increment ir reg 2 cycles Function ir N s adjust ir 1 ir ir 1 Increments 1 the content of the data memory addressed by the ir register X or Y The operation result is adjusted with n4 as the radix The...

Page 100: ...T imm6 1 1 1 1 1 1 0 i5 i4 i3 i2 i1 i0 1F80H 1FBFH Flags E I C Z Mode Immediate data Extended addressing Invalid Note The RETI instruction which returns the content of the F register should be used for returning from the interrupt routine that is executed by this instruction Increment stack pointer 1 cycle Function sp sp 1 Increments 1 the content of the stack pointer sp SP1 or SP2 This instructio...

Page 101: ...H 1FF3H Flags E I C Z Mode Register direct Extended addressing Invalid JR A Jump to relative location A reg 1 cycle Function PC PC A 1 Adds the content of the A register to the address next to this instruction to unconditionally branch to that address Branch destination range is the next address of this instruction 0 to 15 Code Mnemonic MSB LSB JR A 1 1 1 1 1 1 1 1 1 0 0 0 1 1FF1H Flags E I C Z Mo...

Page 102: ... 1 1 1 1 1 1 1 1 0 0 0 0 1FF0H Flags E I C Z Mode Register direct Extended addressing Invalid JR addr6 Jump to relative location addr6 2 cycles Function PC PC addr6 1 addr6 0000H 003FH Adds the content of the data memory 0000H 003FH specified with the addr6 to the address next to this instruction to unconditionally branch to that address Branch destination range is the next address of this instruc...

Page 103: ... 8 bit PC relative Extended addressing Valid Extended LDB EXT imm8 operation JR sign8 PC PC sign16 1 sign16 32768 to 32767 upper 8 bit imm8 lower 8 bit sign8 JRC sign8 Jump to relative location sign8 if C flag is set 1 cycle Function If C 1 then PC PC sign8 1 sign8 128 127 Executes the JR sign8 instruction if the C carry flag has been set to 1 otherwise executes the next instruction Code Mnemonic ...

Page 104: ...Valid Extended LDB EXT imm8 operation JRNC sign8 If C 0 then PC PC sign16 1 sign16 32768 to 32767 upper 8 bit imm8 lower 8 bit sign8 JRNZ sign8 Jump to relative location sign8 if Z flag is reset 1 cycle Function If Z 0 then PC PC sign8 1 sign8 128 127 Executes the JR sign8 instruction if the Z zero flag has been set to 1 otherwise executes the next instruction Code Mnemonic MSB LSB JRNZ sign8 0 0 ...

Page 105: ...ded addressing Valid Extended LDB EXT imm8 operation JRZ sign8 If Z 1 then PC PC sign16 1 sign16 32768 to 32767 upper 8 bit imm8 lower 8 bit sign8 LD r r Load r reg into r reg 1 cycle Function r r Loads the content of the r register A B or F into the r register A B or F Code Mnemonic MSB LSB LD A A 1 1 1 1 0 1 1 1 1 0 0 0 0 1EF0H LD A B 1 1 1 1 0 1 1 1 1 0 0 1 0 1EF2H LD A F 1 1 1 1 1 1 1 1 1 0 1 ...

Page 106: ...ate data Dst Register direct Extended addressing Invalid LD r ir Load location ir reg into r reg 1 cycle Function r ir Loads the content of the data memory addressed by the ir register X or Y into the r register A or B Code Mnemonic MSB LSB LD A X 1 1 1 1 0 1 1 1 0 0 0 0 0 1EE0H LD A Y 1 1 1 1 0 1 1 1 0 0 0 1 0 1EE2H LD B X 1 1 1 1 0 1 1 1 0 0 1 0 0 1EE4H LD B Y 1 1 1 1 0 1 1 1 0 0 1 1 0 1EE6H Fla...

Page 107: ... 0 1 1 1 1EE7H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid LD ir r Load r reg into location ir reg 1 cycle Function ir r Loads the content of the r register A or B into the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB LD X A 1 1 1 1 0 1 1 1 0 1 0 0 0 1EE8H LD X B 1 1 1 1 0 1 1 1 0 1 1 0 0 1EECH LD Y A 1 1 1 1 0 1 1 1 0 1 0 1 0 1...

Page 108: ... 1 1 0 1 1 1 0 1 1 1 1 1EEFH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid LD ir imm4 Load immediate data imm4 into location ir reg 1 cycle Function ir imm4 Loads the 4 bit immediate data imm4 into the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB LD X imm4 1 1 1 1 0 1 0 0 0 i3 i2 i1 i0 1E80H 1E8FH LD Y imm4 1 1 1 1 0 1 0 1 0 i3 i2...

Page 109: ... i2 i1 i0 1E90H 1E9FH LD Y imm4 1 1 1 1 0 1 0 1 1 i3 i2 i1 i0 1EB0H 1EBFH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid LD ir ir Load location ir reg into location ir reg 2 cycles Function ir ir Loads the content of the data memory addressed by the ir register X or Y into the data memory addressed by the ir register Y or X Code Mnemonic MSB LSB LD X Y 1 1 ...

Page 110: ...H LD Y X 1 1 1 1 0 1 1 1 1 1 0 0 1 1EF9H Flags E I C Z Mode Src Register indirect Dst Register indirect Extended addressing Invalid LD ir ir Load location ir reg into location ir reg and increment ir reg 2 cycles Function ir ir ir ir 1 Loads the content of the data memory addressed by the ir register X or Y into the data memory addressed by the ir register Y or X Then increments the ir register X ...

Page 111: ...ments both the ir and ir registers Code Mnemonic MSB LSB LD X Y 1 1 1 1 0 1 1 1 1 1 1 1 1 1EFFH LD Y X 1 1 1 1 0 1 1 1 1 1 1 0 1 1EFDH Flags E I C Z Mode Src Register indirect Dst Register indirect Extended addressing Invalid LDB BA imm8 Load immediate data imm8 into BA reg 1 cycle Function BA imm8 Loads the 8 bit immediate data imm8 into the BA register Code Mnemonic MSB LSB LDB BA imm8 0 1 0 0 1...

Page 112: ...ress is loaded into the B register as the high order 4 bits The ir register X or Y is incremented by 2 words Code Mnemonic MSB LSB LDB BA X 1 1 1 1 1 1 1 0 1 1 0 0 0 1FD8H LDB BA Y 1 1 1 1 1 1 1 0 1 1 0 1 0 1FDAH Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid LDB BA EXT Load EXT reg into BA reg 1 cycle Function BA EXT Loads the content of the EXT register ...

Page 113: ...L 1 1 1 1 1 1 1 0 0 1 0 1 0 1FCAH LDB BA YH 1 1 1 1 1 1 1 0 0 1 0 1 1 1FCBH Flags E I C Z Mode Src Register direct Dst Register direct Extended addressing Invalid LDB BA sp Load stack pointer into BA reg 1 cycle Function BA sp Loads the content of the stack pointer sp SP1 or SP2 into the BA register Code Mnemonic MSB LSB LDB BA SP1 1 1 1 1 1 1 1 0 0 1 1 0 X 1FCCH 1FCDH LDB BA SP2 1 1 1 1 1 1 1 0 0...

Page 114: ...X BA 1 1 1 1 1 1 1 0 1 1 0 0 1 1FD9H LDB Y BA 1 1 1 1 1 1 1 0 1 1 0 1 1 1FDBH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid LDB X imm8 Load immediate data imm8 into location X reg and increment X reg 2 cycles Function X i3 0 X 1 i7 4 X X 2 Loads the 8 bit immediate data imm8 into the data memory The low order 4 bit data is loaded into the data memory addr...

Page 115: ... EXT imm8 0 1 0 0 0 i7 i6 i5 i4 i3 i2 i1 i0 0800H 08FFH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Invalid LDB EXT BA Load BA reg into EXT reg 1 cycle Function EXT BA Loads the content of the BA register into the EXT register The E flag is set to 1 Code Mnemonic MSB LSB LDB EXT BA 1 1 1 1 1 1 1 0 1 0 1 0 X 1FD4H 1FD5H Flags E I C Z Mode Src Register direct Dst Re...

Page 116: ...direct Extended addressing Valid Extended LDB EXT imm8 operation LDB XL imm8 X imm16 upper 8 bit imm8 lower 8 bit imm8 LDB EXT imm8 LDB YL imm8 Y imm16 upper 8 bit imm8 lower 8 bit imm8 LDB rr BA Load BA reg into rr reg 1 cycle Function rr BA Loads the content of the BA register into the rr register XL XH YL or YH Code Mnemonic MSB LSB LDB XL BA 1 1 1 1 1 1 1 0 0 0 0 0 0 1FC0H LDB XH BA 1 1 1 1 1 ...

Page 117: ...SP1 BA 1 1 1 1 1 1 1 0 0 0 1 0 X 1FC4H 1FC5H LDB SP2 BA 1 1 1 1 1 1 1 0 0 0 1 1 X 1FC6H 1FC7H Flags E I C Z Mode Src Register direct Dst Register direct Extended addressing Invalid NOP No operation 1 cycle Function No operation PC PC 1 Expends 1 cycle without doing an operation that otherwise exerts an affect The PC program counter is incremented Code Mnemonic MSB LSB NOP 1 1 1 1 1 1 1 1 1 1 1 1 X...

Page 118: ...B A 1 1 0 1 1 0 1 1 1 0 1 0 X 1B74H 1B75H OR B B 1 1 0 1 1 0 1 1 1 0 1 1 X 1B76H 1B77H Flags E I C Z Mode Src Register direct Dst Register direct Extended addressing Invalid Logical OR of immediate data imm4 and r reg 1 cycle Function r r imm4 Performs a logical OR operation of the 4 bit immediate data imm4 and the content of the r register A or B and stores the result in the r register Code Mnemo...

Page 119: ...essing Invalid OR r ir Logical OR of location ir reg and r reg 1 cycle Function r r ir Performs a logical OR operation of the content of the data memory addressed by the ir register X or Y and the content of the r register A or B and stores the result in the r register Code Mnemonic MSB LSB OR A X 1 1 0 1 1 0 1 1 0 0 0 0 0 1B60H OR A Y 1 1 0 1 1 0 1 1 0 0 0 1 0 1B62H OR B X 1 1 0 1 1 0 1 1 0 0 1 0...

Page 120: ...B X 1 1 0 1 1 0 1 1 0 0 1 0 1 1B65H OR B Y 1 1 0 1 1 0 1 1 0 0 1 1 1 1B67H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid OR ir r Logical OR of r reg and location ir reg 2 cycles Function ir ir r Performs a logical OR operation of the content of the r register A or B and the content of the data memory addressed by the ir register X or Y and stores the resu...

Page 121: ... 0 1 1B6DH OR Y A 1 1 0 1 1 0 1 1 0 1 0 1 1 1B6BH OR Y B 1 1 0 1 1 0 1 1 0 1 1 1 1 1B6FH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid OR ir imm4 Logical OR of immediate data imm4 and location ir reg 2 cycles Function ir ir imm4 Performs a logical OR operation of the 4 bit immediate data imm4 and the content of the data memory addressed by the ir register...

Page 122: ...ult of the ir register does not affect the flags Code Mnemonic MSB LSB OR X imm4 1 1 0 1 1 0 0 0 1 i3 i2 i1 i0 1B10H 1B1FH OR Y imm4 1 1 0 1 1 0 0 1 1 i3 i2 i1 i0 1B30H 1B3FH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid POP r Pop top of stack into r reg 1 cycle Function r SP2 SP2 SP2 1 Loads the 4 bit data that has been stored in the address indicated by ...

Page 123: ... 1 1 0 1FE6H PUSH F 1 1 1 1 1 1 1 1 0 0 1 0 1 1FE5H Flags E I C Z Mode Register direct Extended addressing Invalid Pop top of stack into ir reg 1 cycle Function ir SP1 4 3 SP1 4 SP1 SP1 1 Loads the 16 bit data that has been stored in the addresses 4 words indicated by the stack pointer SP1 SP1 indicates the lowest address into the ir register X or Y then increments the SP1 Code Mnemonic MSB LSB PO...

Page 124: ...MSB LSB PUSH X 1 1 1 1 1 1 1 1 0 0 0 0 1 1FE1H PUSH Y 1 1 1 1 1 1 1 1 0 0 0 1 X 1FE2H 1FE3H Flags E I C Z Mode Register direct Extended addressing Invalid RET Return from subroutine 1 cycle Function PC SP1 4 3 SP1 4 SP1 SP1 1 Loads the 16 bit data return address that has been stored in the addresses 4 words indicated by the stack pointer SP1 SP1 indicates the lowest address into the PC to return f...

Page 125: ...e X register is incremented by 2 words Code Mnemonic MSB LSB RETD imm8 1 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 1100H 11FFH Flags E I C Z Mode Immediate data Extended addressing Invalid RETI Return from interrupt routine 2 cycles Function PC SP1 4 3 SP1 4 SP1 SP1 1 F SP2 SP2 SP2 1 After executing the RET instruction loads the 4 bit data that has been stored in the address indicated by the stack pointer S...

Page 126: ... register and bit 3 moves to the C flag Code Mnemonic MSB LSB RL A 1 0 0 0 0 1 1 1 1 0 0 1 0 10F2H RL B 1 0 0 0 0 1 1 1 1 0 1 1 0 10F6H Flags E I C Z Mode Register direct Extended addressing Invalid Return and skip 2 cycles Function PC SP1 4 3 SP1 4 SP1 SP1 1 PC PC 1 After executing the RET instruction increments the PC to skip 1 instruction immediately after the return Code Mnemonic MSB LSB RETS ...

Page 127: ... RL X Rotates the content of 00imm8 00imm8 0000H 00H to FFH LDB EXT imm8 RL Y Rotates the content of FFimm8 FFimm8 FF00H 00H to FFH RL ir Rotate left location ir reg with carry and increment ir reg 2 cycles Function ir ir 1 Rotates the content of the data memory addressed by the ir register X or Y including the carry C to the left for 1 bit The content of the C flag moves to bit 0 of the data memo...

Page 128: ...ed addressing Invalid r C 3 2 1 0 ir C 3 2 1 0 Rotate right location ir reg with carry 2 cycles Function Rotates the content of the data memory addressed by the ir register X or Y including the carry C to the right for 1 bit The content of the C flag moves to bit 3 of the data memory and bit 0 moves to the C flag Code Mnemonic MSB LSB RR X 1 0 0 0 0 1 1 1 0 1 1 0 0 10ECH RR Y 1 0 0 0 0 1 1 1 0 1 1...

Page 129: ...es not affect the flags Code Mnemonic MSB LSB RR X 1 0 0 0 0 1 1 1 0 1 1 0 1 10EDH RR Y 1 0 0 0 0 1 1 1 0 1 1 1 1 10EFH Flags E I C Z Mode Register indirect Extended addressing Invalid SBC r r Subtract with carry r reg from r reg 1 cycle Function r r r C Subtracts the content of the r register A or B and carry C from the r register A or B Code Mnemonic MSB LSB SBC A A 1 1 0 0 0 1 1 1 1 0 0 0 X 18F...

Page 130: ...ed addressing Invalid SBC r ir Subtract with carry location ir reg from r reg 1 cycle Function r r ir C Subtracts the content of the data memory addressed by the ir register X or Y and carry C from the r register A or B Code Mnemonic MSB LSB SBC A X 1 1 0 0 0 1 1 1 0 0 0 0 0 18E0H SBC A Y 1 1 0 0 0 1 1 1 0 0 0 1 0 18E2H SBC B X 1 1 0 0 0 1 1 1 0 0 1 0 0 18E4H SBC B Y 1 1 0 0 0 1 1 1 0 0 1 1 0 18E6...

Page 131: ... 1 0 0 0 1 1 1 0 0 1 0 1 18E5H SBC B Y 1 1 0 0 0 1 1 1 0 0 1 1 1 18E7H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid SBC ir r Subtract with carry r reg from location ir reg 2 cycles Function ir ir r C Subtracts the content of the r register A or B and carry C from the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB SBC X A 1 1 0 0 0 ...

Page 132: ... 18EDH SBC Y A 1 1 0 0 0 1 1 1 0 1 0 1 1 18EBH SBC Y B 1 1 0 0 0 1 1 1 0 1 1 1 1 18EFH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid SBC ir imm4 Subtract with carry immediate data imm4 from location ir reg 2 cycles Function ir ir imm4 C Subtracts the 4 bit immediate data imm4 and carry C from the data memory addressed by the ir register X or Y Code Mnemon...

Page 133: ... i0 1890H 189FH SBC Y imm4 1 1 0 0 0 1 0 1 1 i3 i2 i1 i0 18B0H 18BFH Flags E I C Z Mode Src Immediate data Dst Register indirect Extended addressing Invalid SBC B A n4 Subtract with carry A reg from B reg in specified radix 2 cycles Function B N s adjust B A C Subtracts the content of the A register and carry C from the B register The operation result is adjusted with n4 as the radix The C flag is...

Page 134: ...h a value from 1 to 16 When 16 is specified for n4 the low order 4 bits of the machine code n3 n0 become 0000B SBC B ir n4 Subtract with carry location ir reg from B reg in specified radix and increment ir reg 2 cycles Function B N s adjust B ir C ir ir 1 Subtracts the content of the data memory addressed by the ir register X or Y and carry C from the B register The operation result is adjusted wi...

Page 135: ...ed with a value from 1 to 16 When 16 is specified for n4 the low order 4 bits of the machine code n3 n0 become 0000B SBC ir B n4 Subtract with carry B reg from location ir reg in specified radix and increment ir reg 2 cycles Function ir N s adjust ir B C ir ir 1 Subtracts the content of the B register and carry C from the data memory addressed by the ir register X or Y The operation result is adju...

Page 136: ...ed with a value from 1 to 16 When 16 is specified for n4 the low order 4 bits of the machine code n3 n0 become 0000B SBC ir 0 n4 Subtract carry from location ir reg in specified radix and increment ir reg 2 cycles Function ir N s adjust ir 0 C ir ir 1 Subtracts the carry C from the data memory addressed by the ir register X or Y The opera tion result is adjusted with n4 as the radix Then increment...

Page 137: ...4 a3 a2 a1 a0 1600H 16FFH SET FFaddr6 imm2 1 0 1 1 1 i1 i0 a5 a4 a3 a2 a1 a0 1700H 17FFH Flags E I C Z Mode Src Immediate data Dst 6 bit absolute Extended addressing Invalid SLL r Shift left r reg logical 1 cycle Function Shifts the content of the r register A or B to the left for 1 bit Bit 3 of the r register moves to the C flag and bit 0 goes 0 Code Mnemonic MSB LSB SLL A 1 0 0 0 0 1 1 1 1 0 0 0...

Page 138: ... 10E1H SLL Y 1 0 0 0 0 1 1 1 0 0 0 1 1 10E3H Flags E I C Z Mode Register indirect Extended addressing Invalid Shift left location ir reg logical 2 cycles Function Shifts the content of the data memory addressed by the ir register X or Y to the left for 1 bit Bit 3 of the r register moves to the C flag and bit 0 goes 0 Code Mnemonic MSB LSB SLL X 1 0 0 0 0 1 1 1 0 0 0 0 0 10E0H SLL Y 1 0 0 0 0 1 1 ...

Page 139: ...he MCU causes it to return from SLEEP status to the normal program execution status Code Mnemonic MSB LSB SLP 1 1 1 1 1 1 1 1 1 1 1 0 1 1FFDH Flags E I C Z SRL r Shift right r reg logical 1 cycle Function Shifts the content of the r register A or B to the right for 1 bit Bit 0 of the r register moves to the C flag and bit 3 goes 0 Code Mnemonic MSB LSB SRL A 1 0 0 0 0 1 1 1 1 0 0 0 1 10F1H SRL B 1...

Page 140: ...RL X Shifts the content of 00imm8 00imm8 0000H 00H to FFH LDB EXT imm8 SRL Y Shifts the content of FFimm8 FFimm8 FF00H 00H to FFH SRL ir Shift right location ir reg logical and increment ir reg 2 cycles Function ir ir 1 Shifts the content of the data memory addressed by the ir register X or Y to the right for 1 bit Bit 0 of the r register moves to the C flag and bit 3 goes 0 Then increments the ir...

Page 141: ...0 1 1 1 0 1 0 X 1874H 1875H SUB B B 1 1 0 0 0 0 1 1 1 0 1 1 X 1876H 1877H Flags E I C Z r r r r Mode Src Register direct Dst Register direct Extended addressing Invalid SUB r imm4 Subtract immediate data imm4 from r reg 1 cycle Function r r imm4 Subtracts the 4 bit immediate data imm4 from the r register A or B Code Mnemonic MSB LSB SUB A imm4 1 1 0 0 0 0 1 0 0 i3 i2 i1 i0 1840H 184FH SUB B imm4 1...

Page 142: ...1 1863H SUB B X 1 1 0 0 0 0 1 1 0 0 1 0 1 1865H SUB B Y 1 1 0 0 0 0 1 1 0 0 1 1 1 1867H Flags E I C Z Mode Src Register indirect Dst Register direct Extended addressing Invalid Subtract location ir reg from r reg 1 cycle Function r r ir Subtracts the content of the data memory addressed by the ir register X or Y from the r register A or B Code Mnemonic MSB LSB SUB A X 1 1 0 0 0 0 1 1 0 0 0 0 0 186...

Page 143: ...DH SUB Y A 1 1 0 0 0 0 1 1 0 1 0 1 1 186BH SUB Y B 1 1 0 0 0 0 1 1 0 1 1 1 1 186FH Flags E I C Z Mode Src Register direct Dst Register indirect Extended addressing Invalid Subtract r reg from location ir reg 2 cycles Function ir ir r Subtracts the content of the r register A or B from the data memory addressed by the ir register X or Y Code Mnemonic MSB LSB SUB X A 1 1 0 0 0 0 1 1 0 1 0 0 0 1868H ...

Page 144: ...m8 00imm8 imm4 00imm8 0000H 00H to FFH LDB EXT imm8 SUB Y imm4 FFimm8 FFimm8 imm4 FFimm8 FF00H 00H to FFH SUB ir imm4 Subtract immediate data imm4 from location ir reg and increment ir reg 2 cycles Function ir ir imm4 ir ir 1 Subtracts the 4 bit immediate data imm4 from the data memory addressed by the ir register X or Y Then increments the ir register X or Y The flags change due to the operation ...

Page 145: ...X 1BF4H 1BF5H XOR B B 1 1 0 1 1 1 1 1 1 0 1 1 X 1BF6H 1BF7H Flags E I C Z r r r r Mode Src Register direct Dst Register direct Extended addressing Invalid Test bit imm2 in location addr6 1 cycle Function addr6 2imm2 addr6 0000H 003FH or FFC0H FFFFH Tests the bit specified with the imm2 in the data memory specified with the addr6 and sets resets the Z flag It does not change the content of the data...

Page 146: ...H XOR B imm4 1 1 0 1 1 1 1 0 1 i3 i2 i1 i0 1BD0H 1BDFH Flags E I C Z Mode Src Immediate data Dst Register direct Extended addressing Invalid XOR F imm4 Exclusive OR immediate data imm4 and F reg 1 cycle Function F F imm4 Performs an exclusive OR operation of the 4 bit immediate data imm4 and the content of the F flag register and stores the result in the r register It is possible to set reset any ...

Page 147: ... r X r r 00imm8 00imm8 0000H 00H to FFH LDB EXT imm8 XOR r Y r r FFimm8 FFimm8 FF00H 00H to FFH XOR r ir Exclusive OR location ir reg and r reg and increment ir reg 1 cycle Function r r ir ir ir 1 Performs an exclusive OR operation of the content of the data memory addressed by the ir register X or Y and the content of the r register A or B and stores the result in the r register Then increments t...

Page 148: ...0imm8 00imm8 r 00imm8 0000H 00H to FFH LDB EXT imm8 XOR Y r FFimm8 FFimm8 r FFimm8 FF00H 00H to FFH XOR ir r Exclusive OR r reg and location ir reg and increment ir reg 2 cycles Function ir ir r ir ir 1 Performs an exclusive OR operation of the content of the r register A or B and the content of the data memory addressed by the ir register X or Y and stores the result in that address Then incremen...

Page 149: ...m8 00imm8 imm4 00imm8 0000H 00H to FFH LDB EXT imm8 XOR Y imm4 FFimm8 FFimm8 imm4 FFimm8 FF00H 00H to FFH XOR ir imm4 Exclusive OR immediate data imm4 and location ir reg and increment ir reg 2 cycles Function ir ir imm4 ir ir 1 Performs an exclusive OR operation of the 4 bit immediate data imm4 and the content of the data memory addressed by the ir register X or Y and stores the result in that ad...

Page 150: ... 97 JRNC sign8 98 JRNZ sign8 98 JRZ sign8 99 LD r r 99 LD r imm4 100 LD r ir 100 LD r ir 101 LD ir r 101 LD ir r 102 LD ir imm4 102 LD ir imm4 103 LD ir ir 103 LD ir ir 104 LD ir ir 104 LD ir ir 105 LDB BA imm8 105 LDB BA ir 106 LDB BA EXT 106 LDB BA rr 107 LDB BA sp 107 LDB ir BA 108 LDB X imm8 108 LDB EXT imm8 109 LDB EXT BA 109 LDB rr imm8 110 LDB rr BA 110 LDB sp BA 111 NOP 111 OR r r 112 OR r...

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Page 153: ...http www epson co jp device Core CPU Manual S1C63000 EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue July 1995 Printed February 2001 in Japan A M ...

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