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Epson S1C17M20, Technical Manual

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16  SOUND GENERATOR (SNDA)

16-4

 

Seiko Epson Corporation 

S1C17M20/M21/M22/M23/M24/M25

 

 

TECHNICAL MANUAL (Rev. 1.0)

2.  Write data to the following sound buffer (SNDDAT register) bits. 

(Start buzzer output)

-  SNDDAT.SLEN[5:0] bits 

(Set buzzer output signal duty ratio)

-  SNDDAT.SFRQ[7:0] bits 

(Set buzzer output signal frequency)

3.  Write 1 to the SNDCTL.SSTP bit after the output period has elapsed.  (Stop buzzer output)

Normal buzzer output operations

 

When data is written to the sound buffer (SNDDAT register), SNDA clears the SNDINTF.EMIF bit (sound buf-
fer empty interrupt flag) to 0 and starts buzzer output operations.

 

The data written to the sound buffer is loaded into the sound register in sync with the CLK_SNDA clock. At 
the same time, the SNDINTF.EMIF bit and SNDINTF.SBSY bit are both set to 1. The output pin outputs the 
buzzer signal with the frequency/duty ratio specified.

 

Writing 1 to the SNDCTL.SSTP bit stops buzzer output and sets the SNDINTF.EDIF bit (sound output comple-
tion interrupt flag) to 1. The SNDINTF.SBSY bit is cleared to 0.

 

Figure 16.4.2.1 shows a buzzer output timing chart in normal buzzer mode.

CLK_SNDA

Sound buffer

(SNDDAT register)

Sound register

SNDCTL.SSTP

SNDINTF.SBSY

SNDINTF.EMIF

SNDINTF.EDIF

BZOUT pin

#BZOUT pin

Writing to the SNDDAT register

Writing to the SNDDAT register

Software operation

(When SNDSEL.SINV bit = 0)

SSTP = 1

Figure 16.4.2.1  Buzzer Output Timing Chart in Normal Buzzer Mode

Buzzer output waveform configuration (normal buzzer mode/one-shot buzzer mode)

 

Set the buzzer signal frequency and duty ratio (high period/cycle) using the SNDDAT.SFRQ[7:0] and SND-
DAT.SLEN[5:0] bits, respectively. Use the following equations to calculate these setting values. 

  

f

CLK_SNDA

SNDDAT.SFRQ[7:0] bits = ————— -1 

 

 

(Eq. 16.1)

  

f

BZOUT

  

f

CLK_SNDA 

DUTY

SNDDAT.SLEN[5:0] bits = 

(

————— 

×

 ————

)

 -1 

 

(Eq. 16.2)

  

f

BZOUT 

100

Where
 f

CLK_SNDA

:  CLK_SNDA frequency [Hz]

 f

BZOUT

: 

Buzzer signal frequency [Hz]

 

DUTY: 

Buzzer signal duty ratio [%]

However, the following settings are prohibited:
 

•  Settings as SNDDAT.SFRQ[7:0] bits 

≤

 SNDDAT.SLEN[5:0] bits

 

•  Settings as SNDDAT.SFRQ[7:0] bits = 0x00

Summary of Contents for S1C17M20

Page 1: ...Rev 1 0 CMOS 16 BIT SINGLE CHIP MICROCONTROLLER S1C17M20 M21 M22 M23 M24 M25 Technical Manual ...

Page 2: ... any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party When exporting the products or technology described in this material you should comply with the applicable export control laws and regulations and follow the pr...

Page 3: ...the reset group H0 H1 or S0 For more information on the reset groups refer to Initialization Conditions Reset Groups in the Power Supply Reset and Clocks chapter R W R Read only bit W Write only bit WP Write only bit with a write protection using the MSCPROT PROT 15 0 bits R W Read write bit R WP Read write bit with a write protection using the MSCPROT PROT 15 0 bits Control bit read write values ...

Page 4: ...Groups 2 3 2 3 Clock Generator CLG 2 4 2 3 1 Overview 2 4 2 3 2 Input Output Pins 2 5 2 3 3 Clock Sources 2 5 2 3 4 Operations 2 8 2 4 Operating Mode 2 12 2 4 1 Initial Boot Sequence 2 12 2 4 2 Transition between Operating Modes 2 12 2 5 Interrupts 2 14 2 6 Control Registers 2 14 PWG VD1 Regulator Control Register 2 14 CLG System Clock Control Register 2 15 CLG Oscillation Control Register 2 16 CL...

Page 5: ...TBR 5 3 5 3 Initialization 5 3 5 4 Maskable Interrupt Control and Operations 5 3 5 4 1 Peripheral Circuit Interrupt Control 5 3 5 4 2 ITC Interrupt Request Processing 5 4 5 4 3 Conditions to Accept Interrupt Requests by the CPU 5 4 5 5 NMI 5 4 5 6 Software Interrupts 5 4 5 7 Interrupt Processing by the CPU 5 5 5 8 Control Registers 5 5 MISC Vector Table Address Low Register 5 5 MISC Vector Table A...

Page 6: ...tiplexer UPMUX 7 1 7 1 Overview 7 1 7 2 Peripheral Circuit I O Function Assignment 7 1 7 3 Control Registers 7 2 Pxy xz Universal Port Multiplexer Setting Register 7 2 8 Watchdog Timer WDT2 8 1 8 1 Overview 8 1 8 2 Clock Settings 8 1 8 2 1 WDT2 Operating Clock 8 1 8 2 2 Clock Supply in DEBUG Mode 8 1 8 3 Operations 8 2 8 3 1 WDT2 Control 8 2 8 3 2 Operations in HALT and SLEEP Modes 8 3 8 4 Control...

Page 7: ...t 10 4 10 5 1 SVD3 Interrupt 10 4 10 5 2 SVD3 Reset 10 5 10 6 Control Registers 10 5 SVD3 Clock Control Register 10 5 SVD3 Control Register 10 6 SVD3 Status and Interrupt Flag Register 10 7 SVD3 Interrupt Enable Register 10 8 11 16 bit Timers T16 11 1 11 1 Overview 11 1 11 2 Input Pin 11 1 11 3 Clock Settings 11 2 11 3 1 T16 Operating Clock 11 2 11 3 2 Clock Supply in SLEEP Mode 11 2 11 3 3 Clock ...

Page 8: ...2 7 Interrupts 12 9 12 8 Control Registers 12 9 UART3 Ch n Clock Control Register 12 9 UART3 Ch n Mode Register 12 10 UART3 Ch n Baud Rate Register 12 11 UART3 Ch n Control Register 12 12 UART3 Ch n Transmit Data Register 12 12 UART3 Ch n Receive Data Register 12 12 UART3 Ch n Status and Interrupt Flag Register 12 13 UART3 Ch n Interrupt Enable Register 12 14 UART3 Ch n Carrier Waveform Register 1...

Page 9: ...r Mode 14 7 14 4 4 10 bit Addressing in Master Mode 14 9 14 4 5 Data Transmission in Slave Mode 14 10 14 4 6 Data Reception in Slave Mode 14 12 14 4 7 Slave Operations in 10 bit Address Mode 14 14 14 4 8 Automatic Bus Clearing Operation 14 14 14 4 9 Error Detection 14 15 14 5 Interrupts 14 16 14 6 Control Registers 14 17 I2C Ch n Clock Control Register 14 17 I2C Ch n Mode Register 14 18 I2C Ch n B...

Page 10: ...in DEBUG Mode 16 3 16 4 Operations 16 3 16 4 1 Initialization 16 3 16 4 2 Buzzer Output in Normal Buzzer Mode 16 3 16 4 3 Buzzer Output in One shot Buzzer Mode 16 6 16 4 4 Output in Melody Mode 16 7 16 5 Interrupts 16 9 16 6 Control Registers 16 9 SNDA Clock Control Register 16 9 SNDA Select Register 16 10 SNDA Control Register 16 11 SNDA Data Register 16 11 SNDA Interrupt Flag Register 16 12 SNDA...

Page 11: ...ing Function 18 7 18 5 Interrupts 18 7 18 6 Control Registers 18 8 RFC Ch n Clock Control Register 18 8 RFC Ch n Control Register 18 8 RFC Ch n Oscillation Trigger Register 18 9 RFC Ch n Measurement Counter Low and High Registers 18 10 RFC Ch n Time Base Counter Low and High Registers 18 10 RFC Ch n Interrupt Flag Register 18 11 RFC Ch n Interrupt Enable Register 18 11 19 12 bit A D Converter ADC1...

Page 12: ...eripheral Circuit Control Registers AP A 1 0x4000 0x4008 Misc Registers MISC AP A 1 0x4020 Power Generator PWG AP A 1 0x4040 0x4050 Clock Generator CLG AP A 1 0x4080 0x4094 Interrupt Controller ITC AP A 2 0x40a0 0x40a4 Watchdog Timer WDT2 AP A 4 0x40c0 0x40d2 Real time Clock RTCA AP A 4 0x4100 0x4106 Supply Voltage Detector SVD3 AP A 6 0x4160 0x416c 16 bit Timer T16 Ch 0 AP A 6 0x41b0 Flash Contro...

Page 13: ...ter ADC12A AP A 31 0xffff90 Debugger DBG AP A 33 Appendix B Power Saving AP B 1 B 1 Operating Status Configuration Examples for Power Saving AP B 1 B 2 Other Power Saving Methods AP B 2 Appendix C Mounting Precautions AP C 1 Appendix D Measures Against Noise AP D 1 Appendix E Initialization Routine AP E 1 Revision History ...

Page 14: ...tection circuit included OSC3 oscillator circuit 21 MHz max crystal ceramic oscillator 12 16 and 20 MHz switchable embedded oscillator Auto trimming function for the embedded oscillator EXOSC clock input 21 MHz max square or sine wave input Other Configurable system clock division ratio Configurable system clock used at wake up from SLEEP state Operating clock frequency for the CPU and all periphe...

Page 15: ... 1 channel Number of analog signal input ports 4 ports 6 ports 8 ports Multiplier divider COPRO2 Arithmetic functions 16 bit 16 bit multiplier 16 bit 16 bit 32 bit multiply and accumulation unit 32 bit 32 bit divider Reset RESET pin Reset when the reset pin is set to low Power on reset Reset at power on Brownout reset Reset when the power supply voltage drops Key entry reset Reset when the P00 to ...

Page 16: ... bit PWM timer T16B 2Ch SDI0 1 SDO0 1 SPICLK0 1 SPISS0 1 Synchronous serial interface SPIA 2 Ch USIN0 1 USOUT0 1 UART UART3 2 Ch Flash memory 16KB M20 M21 M22 32KB M23 M24 M25 VPP Flash programming voltage booster IOSC oscillator OSC1 oscillator EXOSC input circuit Clock generator CLG FOUT OSC1 OSC2 OSC3 OSC4 EXOSC OSC3 oscillator RTC1S Real time clock RTCA Power on reset POR System reset controll...

Page 17: ...MUX ADIN02 P26 UPMUX ADIN01 P00 PD2 PD1 PD0 V DD RESET P00 EXCL00 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 V DD RESET 12 11 10 9 8 7 19 20 21 22 23 24 VSS VD1 P32 P31 P30 P27 VSS VD1 P32 RTC1S UPMUX EXSVD0 P31 EXOSC UPMUX P30 UPMUX VREFA0 P27 UPMUX ADIN00 Pin name P01 P02 P03 VPP P12 P13 Port function or signal assignment P01 EXCL01 UPMUX P02 BZOUT UPMUX P03 BZOUT UPMUX VPP P12 REMO UPMUX P13 FOUT UPMUX T...

Page 18: ...D3 PD4 V DD RESET P00 EXCL00 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 PD3 OSC3 PD4 OSC4 V DD RESET 16 15 14 13 12 11 10 9 Top View 25 26 27 28 29 30 31 32 VSS VD1 OSC2 OSC1 P32 P31 P30 P27 VSS VD1 OSC2 OSC1 P32 RTC1S UPMUX EXSVD0 P31 EXOSC UPMUX P30 UPMUX VREFA0 P27 UPMUX ADIN00 Pin name P01 P02 P03 P10 P11 VPP P12 P13 Port function or signal assignment P01 EXCL01 UPMUX P02 BZOUT UPMUX P03 BZOUT UPMUX P10...

Page 19: ...ESET P00 EXCL00 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 PD3 OSC3 PD4 OSC4 V DD RESET S1C17M21 S1C17M24 VSS VD1 OSC2 OSC1 P32 P31 P30 P27 VSS VD1 OSC2 OSC1 P32 RTC1S UPMUX EXSVD0 P31 EXOSC UPMUX P30 UPMUX VREFA0 P27 UPMUX ADIN00 Pin name P01 P02 P03 P10 P11 VPP P12 P13 Port function or signal assignment P01 EXCL01 UPMUX P02 BZOUT UPMUX P03 BZOUT UPMUX P10 UPMUX P11 UPMUX VPP P12 REMO UPMUX P13 FOUT UPMUX ...

Page 20: ...UPMUX DCLK PD2 DSIO PD1 DST2 PD0 P42 RFIN1 P41 REF1 P40 SENA1 P37 SENB1 UPMUX PD3 OSC3 PD4 OSC4 V DD RESET 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 VSS VD1 OSC2 OSC1 P36 P35 P34 P33 P32 P31 P30 P27 VSS VD1 OSC2 OSC1 P36 RFIN0 UPMUX P35 REF0 UPMUX P34 SENA0 UPMUX P33 SENB0 UPMUX P32 RTC1S UPMUX EXSVD0 P31 EXOSC UPMUX P30 UPMUX VREFA0 P27 UPMUX ADIN00 Pin name P01 P02 ...

Page 21: ... RESET I I Pull up Reset input P00 P00 I O Hi Z I O port EXCL00 I 16 bit PWM timer Ch 0 event counter input 0 UPMUX I O User selected I O universal port multiplexer P01 P01 I O Hi Z I O port EXCL01 I 16 bit PWM timer Ch 0 event counter input 1 UPMUX I O User selected I O universal port multiplexer P02 P02 I O Hi Z I O port BZOUT O Sound generator output UPMUX I O User selected I O universal port m...

Page 22: ...t 4 P24 P24 I O Hi Z I O port EXCL10 I 16 bit PWM timer Ch 1 event counter input 0 UPMUX I O User selected I O universal port multiplexer ADIN03 A 12 bit A D converter Ch 0 analog signal input 3 P25 P25 I O Hi Z I O port EXCL11 I 16 bit PWM timer Ch 1 event counter input 1 UPMUX I O User selected I O universal port multiplexer ADIN02 A 12 bit A D converter Ch 0 analog signal input 2 P26 P26 I O Hi...

Page 23: ...tput port PD3 PD3 I O Hi Z I O port OSC3 A OSC3 oscillator circuit input PD4 PD4 I O Hi Z I O port OSC4 A OSC3 oscillator circuit output Note In the peripheral circuit descriptions the assigned signal name is used as the pin name Universal port multiplexer UPMUX The universal port multiplexer UPMUX allows software to select the peripheral circuit input output function to be assigned to each pin fr...

Page 24: ... 2 1 2 1 lists the PWG pins Table 2 1 2 1 List of PWG Pins Pin name I O Initial status Function VDD P Power supply VSS P GND VD1 A Embedded regulator output pin For the VDD operating voltage range and recommended external parts refer to Recommended Operating Condi tions Power supply voltage VDD in the Electrical Characteristics chapter and the Basic External Connection Diagram chapter respectively...

Page 25: ...l bits will be reset with an appropriate initialization condition ac cording to changes in status Figure 2 2 1 1 shows the SRC configuration Reset hold circuit SRC RESET Key entry reset Watchdog timer reset Supply voltage detector reset Software reset 0 Software reset n Internal reset signals Reset group SYSRST_H0 SYSRST_H1 SYSRST_S0_0 SYSRST_S0_n To CPU and peripheral circuits To CPU and peripher...

Page 26: ...tion refer to the I O Ports chapter Watchdog timer reset Setting the watchdog timer into reset mode will issue a reset request when the counter overflows This helps re turn the runaway CPU to a normal operating state For more information refer to the Watchdog timer chapter Supply voltage detector reset By enabling the low power supply voltage detection reset function the supply voltage detector wi...

Page 27: ...XOSC clock input circuit that allows input of square wave and sine wave clock signals The system clock SYSCLK which is used as the operating clock for the CPU and bus and the peripheral cir cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting Controls...

Page 28: ...UT FOUTDIV 2 0 FOUTEN Figure 2 3 1 1 CLG Configuration 2 3 2 Input Output Pins Table 2 3 2 1 lists the CLG pins Table 2 3 2 1 List of CLG Pins Pin name I O Initial status Function OSC1 A OSC1 oscillator circuit input OSC2 A OSC1 oscillator circuit output OSC3 A OSC3 oscillator circuit input OSC4 A OSC3 oscillator circuit output EXOSC I I EXOSC clock input FOUT O O L FOUT clock output Indicates the...

Page 29: ... environments that may stop the oscil lation The oscillation startup control circuit operates for a set period of time after the oscillation is enabled to assist the oscillator in initiating this makes it possible to use a low power resonator that is difficult to start up Note Depending on the circuit board or the crystal resonator type used an external gate capacitor CG1 and a drain capacitor CD1...

Page 30: ...back resistor RF3 Drain resistor RD3 Crystal ceramic oscillator OSC3EN Oscillation stabilization waiting circuit Noise filter Selector OSC3INV 1 0 OSC3WT 2 0 OSC3 OSC4 Interrupt controller OSC3CLK OSC3MD X tal3 Ceramic3 VSS VSS Internal data bus Internal oscillator External gate capacitor CG3 Internal gate capacitor CGI3C Internal drain capacitor CDI3C Peripheral I O function 4 External drain capa...

Page 31: ...stabilization waiting time for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16 384 OSC1CLK clocks or more when crystal oscillator is selected or 4 096 OSC1CLK clocks or more when internal oscillator is selected The oscillation stabilization waiting time for the OSC3 oscillator circuit should be...

Page 32: ...hen using the crystal oscillator CLGOSC1 INV1N 1 0 bits Set oscillation inverter gain CLGOSC1 CGI1 2 0 bits Set internal gate capacitor CLGOSC1 INV1B 1 0 bits Set oscillation inverter gain for startup boosting period CLGOSC1 OSC1BUP bit Enable disable oscillation startup control circuit 5 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection 6 Write 1 to the CLGOSC OS...

Page 33: ...be altered For the transition between the operating modes including the system clock switching refer to Oper ating Mode Clock control in SLEEP mode The CPU enters SLEEP mode when it executes the slp instruction Whether the clock sources being operated are stopped or not at this point can be selected in each source individually This allows the CPU to fast switch between SLEEP mode and RUN mode and ...

Page 34: ...GFOUT FOUTSRC 1 0 bits Select clock source CLGFOUT FOUTDIV 2 0 bits Set clock division ratio Set the CLGFOUT FOUTEN bit to 1 Enable clock external output OSC3 oscillation auto trimming function The OSC3 internal oscillator circuit has the auto trimming function that adjusts the OSC3CLK clock frequency by trimming the clock with reference to the high precision OSC1CLK clock generated by the OSC1 cr...

Page 35: ...oot Sequence Figure 2 4 1 1 shows the initial boot sequence after power is turned on VDD Reset request from POR IOSCCLK Initial SYSCLK Internal reset signal SYSRST H0 H1 S1C17 core program counter PC Cancel reset request Undefined Undefined 1 1 Reset vector reset handler start address 2 Address reset vector 2 2 Cancel reset request Reset hold time tRSTR Figure 2 4 1 1 Initial Boot Sequence Note Th...

Page 36: ...uction is executed For more information on DEBUG mode refer to Debugger in the CPU and Debugger chapter IOSC RUN OSC1 RUN IOSC HALT OSC3 HALT OSC3 RUN RESET Initial state RUN HALT SLEEP DEBUG Transition takes place automatically by the initial boot sequence after a request from the reset source is canceled In RUN and HALT modes the clock sources not used as SYSCLK can be all disabled H A L T S L E...

Page 37: ...AIF When the OSC3 oscillation stabilization waiting operation has completed after the oscillation starts Writing 1 OSC1 oscillation stop CLGINTF OSC1STPIF When OSC1CLK is stopped or when the CLGOSC OSC1EN or CLGOSC1 OSDEN bit setting is al tered from 1 to 0 Writing 1 OSC3 oscillation auto trimming completion CLGINTF OSC3TEDIF When the OSC3 oscillation auto trimming opera tion has completed Writing...

Page 38: ...cks after a system wake up However the enable bit of the clock source being operated during SLEEP mode by setting the CLGOSC SLPC bit retains 1 after a wake up Bit 14 Reserved Bits 13 12 WUPDIV 1 0 These bits select the SYSCLK division ratio for resetting the CLGSCLK CLKDIV 1 0 bits at wake up This setting is ineffective when the CLGSCLK WUPMD bit 0 Bits 11 10 Reserved Bits 9 8 WUPSRC 1 0 These bi...

Page 39: ... 15 12 Reserved Bit 11 EXOSCSLPC Bit 10 OSC3SLPC Bit 9 OSC1SLPC Bit 8 IOSCSLPC These bits control the clock source operations in SLEEP mode 1 R W Stop clock source in SLEEP mode 0 R W Continue operation state before SLEEP Each bit corresponds to the clock source as follows CLGOSC EXOSCSLPC bit EXOSC clock input CLGOSC OSC3SLPC bit OSC3 oscillator circuit CLGOSC OSC1SLPC bit OSC1 oscillator circuit...

Page 40: ...p detector off Note Do not write 1 to the CLGOSC1 OSDEN bit before stabilized OSC1CLK is supplied Further more the CLGOSC1 OSDEN bit should be set to 0 when the CLGOSC OSC1EN bit is set to 0 Bit 12 OSC1BUP This bit enables the oscillation startup control circuit in the OSC1 crystal oscillator circuit 1 R WP Enable Activate booster operation at startup 0 R WP Disable Bit 11 OSC1SELCR This bit selec...

Page 41: ...r the OSC1 oscillator circuit Table 2 6 7 OSC1 Oscillation Stabilization Waiting Time Setting CLGOSC1 OSC1WT 1 0 bits Oscillation stabilization waiting time 0x3 65 536 clocks 0x2 16 384 clocks 0x1 4 096 clocks 0x0 Reserved CLG OSC3 Control Register Register name Bit Bit name Initial Reset R W Remarks CLGOSC3 15 12 0x0 R 11 10 OSC3FQ 1 0 0x1 H0 R WP 9 OSC3MD 0 H0 R WP 8 0 R 7 6 0x0 R 5 4 OSC3INV 1 ...

Page 42: ...ake sure the CLGINTF OSC1STAIF bit is set to 1 before starting the trimming operation Do not alter the CLGOSC3 OSC3FQ 1 0 bits while auto trimming is being executed Select the 32 768 kHz crystal oscillator for the OSC1 oscillator circuit when using the auto trimming function The clock cannot be adjusted properly by the internal oscillator Bits 2 0 OSC3WT 2 0 These bits set the oscillation stabiliz...

Page 43: ...ion interrupt Note The CLGINTF IOSCSTAIF bit is 0 after system reset is canceled but IOSCCLK has already been stabilized CLG Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks CLGINTE 15 8 0x00 R 7 0 R 6 reserved 0 H0 R 5 OSC1STPIE 0 H0 R W 4 OSC3TEDIE 0 H0 R W 3 0 R 2 OSC3STAIE 0 H0 R W 1 OSC1STAIE 0 H0 R W 0 IOSCSTAIE 0 H0 R W Bits 15 6 3 Reserved Bit 5 OSC1STPIE Bit ...

Page 44: ...IV 2 0 bits CLGFOUT FOUTSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSCCLK OSC1CLK OSC3CLK SYSCLK 0x7 1 128 1 32 768 1 128 Reserved 0x6 1 64 1 4 096 1 64 Reserved 0x5 1 32 1 1 024 1 32 Reserved 0x4 1 16 1 256 1 16 Reserved 0x3 1 8 1 8 1 8 Reserved 0x2 1 4 1 4 1 4 Reserved 0x1 1 2 1 2 1 2 Reserved 0x0 1 1 1 1 1 1 1 1 Note When the CLGFOUT FOUTSRC 1 0 bits are set to 0x3 the FOUT output will be stopped in SLEEP H...

Page 45: ... be extended up to 24 bits Supports reset NMI address misaligned debug and external interrupts Reads a vector from the vector table and branches to the interrupt handler routine directly Can generate software interrupts with a vector number specified all vector numbers specifiable HALT mode halt instruction and SLEEP mode slp instruction are provided as the standby function Incorporates a debugger...

Page 46: ... I O area reserved for the S1C17 core Do not access this area ex cept when it is required 3 3 Debugger 3 3 1 Debugging Functions The debugger provides the following functions Instruction break A debug interrupt is generated immediately before the set instruction address is executed An instruction break can be set at up to four addresses Single step A debug interrupt is generated after each instruc...

Page 47: ...h a high level from outside e g pulling up with a resistor Also do not connect short circuit between the DCLK pin and another GPIO port In the both cases the IC may not start up normally due to unstable pin input output status at power on 3 3 4 External Connection Figure 3 3 4 1 shows a connection example between this IC and ICDmini when performing debugging DCLK DSIO DST2 DCLK DSIO DST2 VDD ICDmi...

Page 48: ...egister name Bit Bit name Initial Reset R W Remarks MSCPSR 15 8 0x00 R 7 5 PSRIL 2 0 0x0 H0 R 4 PSRIE 0 H0 R 3 PSRC 0 H0 R 2 PSRV 0 H0 R 1 PSRZ 0 H0 R 0 PSRN 0 H0 R Bits 15 8 Reserved Bits 7 5 PSRIL 2 0 The value 0 to 7 of the PSR IL 2 0 interrupt level bits can be read out with these bits Bit 4 PSRIE The value 0 or 1 of the PSR IE interrupt enable bit can be read out with this bit Bit 3 PSRC The ...

Page 49: ...x00 7fff Reserved 0x00 7fff Reserved 0x00 6000 0x00 6000 0x00 5fff Peripheral circuit area 8K bytes Device size 16 bits 0x00 5fff Peripheral circuit area 8K bytes Device size 16 bits 0x00 4000 0x00 4000 0x00 3fff Reserved 0x00 3fff Reserved 0x00 0800 0x00 0800 0x00 07ff 0x00 07c0 Debug RAM area 64 bytes 0x00 07ff 0x00 07c0 Debug RAM area 64 bytes 0x00 07bf RAM area 2K bytes Device size 32 bits 0x0...

Page 50: ...ber of data area bus cycles When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area When the CPU executes an instruction stored in the internal RAM area and accesses data in the internal RAM area 4 3 Flash Memory The Flash memory is used to store application programs and data Address 0x8000 in the Flash area is defined as the vector table base address by d...

Page 51: ...h memory by supplying the VPP voltage externally 2 4 V or more VDD voltage is required When programming the Flash memory by generating the VPP voltage internally 2 7 V or more VDD voltage is required Be sure to avoid using the VPP pin output for driving external circuits when the VPP voltage is generated internally 4 4 RAM The RAM can be used to execute the instruction codes copied from another me...

Page 52: ...Control Register 0x40a2 WDTCTL WDT2 Control Register 0x40a4 WDTCMP WDT2 Counter Compare Match Register Real time clock RTCA 0x40c0 RTCCTL RTC Control Register 0x40c2 RTCALM1 RTC Second Alarm Register 0x40c4 RTCALM2 RTC Hour Minute Alarm Register 0x40c6 RTCSWCTL RTC Stopwatch Control Register 0x40c8 RTCSEC RTC Second 1Hz Register 0x40ca RTCHUR RTC Hour Minute Register 0x40cc RTCMON RTC Month Day Re...

Page 53: ...egister 0x42d4 PDRCTL Pd Port Pull up down Control Register 0x42dc PDMODSEL Pd Port Mode Select Register 0x42de PDFNCSEL Pd Port Function Select Register 0x42e0 PCLK P Port Clock Control Register 0x42e2 PINTFGRP P Port Interrupt Flag Group Register Universal port multiplexer UPMUX 0x4300 P0UPMUX0 P00 01 Universal Port Multiplexer Setting Register 0x4302 P0UPMUX1 P02 03 Universal Port Multiplexer S...

Page 54: ...rrupt Flag Register 0x500c T16B0INTE T16B Ch 0 Interrupt Enable Register 0x5010 T16B0CCCTL0 T16B Ch 0 Compare Capture 0 Control Register 0x5012 T16B0CCR0 T16B Ch 0 Compare Capture 0 Data Register 0x5018 T16B0CCCTL1 T16B Ch 0 Compare Capture 1 Control Register 0x501a T16B0CCR1 T16B Ch 0 Compare Capture 1 Data Register 16 bit PWM timer T16B Ch 1 0x5040 T16B1CLK T16B Ch 1 Clock Control Register 0x504...

Page 55: ...0INTF RFC Ch 0 Interrupt Flag Register 1 2 3 0x5450 RFC0INTE RFC Ch 0 Interrupt Enable Register 1 2 3 R F converter RFC Ch 1 0x5460 RFC1CLK RFC Ch 1 Clock Control Register 1 2 3 0x5462 RFC1CTL RFC Ch 1 Control Register 1 2 3 0x5464 RFC1TRG RFC Ch 1 Oscillation Trigger Register 1 2 3 0x5466 RFC1MCL RFC Ch 1 Measurement Counter Low Register 1 2 3 0x5468 RFC1MCH RFC Ch 1 Measurement Counter High Regi...

Page 56: ...s MSCPROT 15 0 PROT 15 0 0x0000 H0 R W Bits 15 0 PROT 15 0 These bits protect the control registers related to the system against writings 0x0096 R W Disable system protection Other than 0x0096 R W Enable system protection While the system protection is enabled any data will not be written to the affected control bits bits with WP or R WP appearing in the R W column MISC IRAM Size Register Registe...

Page 57: ...ble 4 6 2 Setting Number of Bus Access Cycles for Flash Read FLASHCWAIT RDWAIT 1 0 bits Number of bus Access cycles System clock frequency 0x3 4 21 0 MHz max 0x2 3 18 9 MHz max 0x1 2 12 6 MHz max 0x0 1 6 3 MHz max Note Be sure to set the FLASHCWAIT RDWAIT 1 0 bits before the system clock is configured ...

Page 58: ...set signal Debug interrupt HALT SLEEP cancelation signal Interrupt request NMI ILVx 2 0 Interrupt control circuit ILVy 2 0 Interrupt request Peripheral circuit Peripheral circuit Internal data bus Figure 5 1 1 ITC Configuration 5 2 Vector Table The vector table contains the vectors to the interrupt handler routines handler routine start address that will be read by the CPU to execute the handler w...

Page 59: ...nous serial interface Ch 0 interrupt End of transmission Receive buffer full Transmit buffer empty Overrun error 13 0x0d TTBR 0x34 I2 C interrupt End of data transfer General call address reception NACK reception STOP condition START condition Error detection Receive buffer full Transmit buffer empty 14 0x0e TTBR 0x38 16 bit PWM timer Ch 0 interrupt Capture overwrite Compare capture Counter MAX Counte...

Page 60: ...ault address set it to the MSCTTBRL and MSCTTBRH registers after removing system protection by writing 0x0096 to the MSCPROT PROT 15 0 bits Then write a value other than 0x0096 to the MSCPROT PROT 15 0 bits to set system protection 3 Set the interrupt enable bit of the peripheral circuit to 0 interrupt disabled 4 Set the interrupt level for the peripheral circuit using the ITCLVx ILVx 2 0 bits in ...

Page 61: ... signals to the setting in formation on the more recent interrupt The previously occurring interrupt is held The held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software Note Before changing the interrupt level make sure that no interrupt of which the level is changed can be generated the interrupt enable bit of the peripheral...

Page 62: ...routines using the reti instruction returns the PSR to the state before the interrupt occurred The program resumes processing following the instruction being executed at the time the interrupt occurred Note When HALT or SLEEP mode is canceled the CPU jumps to the interrupt handler routine after executing one instruction To execute the interrupt handler routine immediately after HALT or SLEEP mode ...

Page 63: ...TCLV3 ITC Interrupt Level Setup Register 3 15 11 0x00 R 10 8 ILV7 2 0 0x0 H0 R W 16 bit timer Ch 1 interrupt ILVT16_1 7 3 0x00 R 2 0 ILV6 2 0 0x0 H0 R W UART Ch 0 interrupt ILVUART3_0 ITCLV4 ITC Interrupt Level Setup Register 4 15 11 0x00 R 10 8 ILV9 2 0 0x0 H0 R W I2C interrupt ILVI2C_0 7 3 0x00 R 2 0 ILV8 2 0 0x0 H0 R W Synchronous serial interface Ch 0 interrupt ILVSPIA_0 ITCLV5 ITC Interrupt L...

Page 64: ... Level Setup Register 9 15 11 0x00 R 10 8 ILV19 2 0 0x0 H0 R W Synchronous serial interface Ch 1 interrupt ILVSPIA_1 7 3 0x00 R 2 0 ILV18 2 0 0x0 H0 R W 16 bit timer Ch 2 interrupt ILVT16_2 ITCLV10 ITC Interrupt Level Setup Register 10 15 11 0x00 R 10 8 ILV21 2 0 0x0 R W 12 bit A D converter interrupt ILVADC12A_0 7 3 0x00 R 2 0 ILV20 2 0 0x0 R W 16 bit timer Ch 3 interrupt ILVT16_3 ...

Page 65: ... to a port group x 0 1 2 d and y refers to a port number y 0 1 2 7 Figure 6 1 1 shows the configuration of PPORT Table 6 1 1 Port Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 pin package Port groups included P0 P0 3 0 4 1 2 P0 3 0 4 1 2 P0 3 0 4 1 2 P0 7 0 8 1 2 P1 P1 5 2 4 1 2 P1 5 0 6 1 2 P1 5 0 6 1 2 P1 7 0 8 1 2 P2 P2 7 4 4 1 2 P2 ...

Page 66: ...set control circuit PxCHATENy PxEDGEy PxIFy PxIEy PxINT Key entry reset signal Figure 6 1 1 PPORT Configuration 6 2 I O Cell Structure and Functions Figure 6 2 1 shows the I O cell Configuration Pull up down Control signal Over voltage tolerant fail safe type I O cell Input signal Input control signal Output signal Output control signal Analog signal Analog control signal Pull up down Control sign...

Page 67: ...ance and the pin load capacitance The rising falling time is commonly de termined by the following equation tPR RINU CIN CBOARD ln 1 VT VDD Eq 6 1 tPF RIND CIN CBOARD ln 1 VT VDD Where tPR Rising time port level low high second tPF Falling time port level high low second VT High level Schmitt input threshold voltage V VT Low level Schmitt input threshold voltage V RINU RIND Pull up pull down resis...

Page 68: ... ports except for the debugging function are configured as shown below Port input Disabled Port output Disabled Pull up Off Pull down Off Port pins High impedance state Port function Configured to GPIO This status continues until the ports are configured via software The debugging function ports are configured for debug signal input output Initial settings when using a port for a peripheral I O fu...

Page 69: ...the PxIOEN PxOENy bit to 0 Disable output Set the PxIOEN PxIENy bit to 1 Enable input Steps 1 and 5 are required for the ports with an interrupt function Step 2 is required for the ports with a chat tering filter function Table 6 4 1 1 lists the port status according to the combination of data input output control and pull up down control Table 6 4 1 1 GPIO Port Control List PxIOEN PxIENy bit PxIO...

Page 70: ...tly to itself Key entry reset function This function issues a reset request when low level pulses are input to all the specified ports simultaneously Make the following settings when using this function 1 Configure the ports to be used for key entry reset as general purpose input ports refer to Initial settings when using a port as a general purpose input port only for the ports with GPIO function...

Page 71: ... of this IC Px Port Data Register Register name Bit Bit name Initial Reset R W Remarks PxDAT 15 8 PxOUT 7 0 0x00 H0 R W 7 0 PxIN 7 0 0x00 H0 R 1 This register is effective when the GPIO function is selected 2 The bit configuration differs depending on the port group 3 The initial value may be changed by the port Bits 15 8 PxOUT 7 0 These bits are used to set data to be output from the GPIO port pi...

Page 72: ...0 PxREN 7 0 These bits enable disable the port pull up down control 1 R W Enable The built in pull up down resistor is used 0 R W Disable No pull up down control is performed Enabling this function pulls up or down the port when output is disabled PxIOEN PxOENy bit 0 When output is enabled PxIOEN PxOENy bit 1 the PxRCTL PxRENy bit setting is ineffective re gardless of how the PxIOEN PxIENy bit is ...

Page 73: ...e The chattering filter is used 0 R W Disable The chattering filter is bypassed Px Port Mode Select Register Register name Bit Bit name Initial Reset R W Remarks PxMODSEL 15 8 0x00 R 7 0 PxSEL 7 0 0x00 H0 R W 1 The bit configuration differs depending on the port group 2 The initial value may be changed by the port Bits 15 8 Reserved Bits 7 0 PxSEL 7 0 These bits select whether each port is used fo...

Page 74: ...e or not 1 R WP Clock supplied in DEBUG mode 0 R WP No clock supplied in DEBUG mode Bits 7 4 CLKDIV 3 0 These bits select the division ratio of the PPORT operating clock chattering filter clock Bits 3 2 KRSTCFG 1 0 These bits configure the key entry reset function Table 6 6 2 Key Entry Reset Function Settings PCLK KRSTCFG 1 0 bits key entry reset 0x3 Reset when P0 3 0 inputs all low 0x2 Reset when...

Page 75: ...ck source P Port Interrupt Flag Group Register Register name Bit Bit name Initial Reset R W Remarks PINTFGRP 15 13 0x0 R 12 PcINT 0 H0 R 11 PbINT 0 H0 R 10 PaINT 0 H0 R 9 P9INT 0 H0 R 8 P8INT 0 H0 R 7 P7INT 0 H0 R 6 P6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R 1 Only the bits corresponding to the port groups that support interrupts are prov...

Page 76: ... Registers for P0 Port Group Register name Bit Bit name Initial Reset R W Remarks M20 M23 M21 M24 M22 M25 24pin 32pin P0DAT P0 Port Data Register 15 P0OUT7 0 H0 R W 14 P0OUT6 0 H0 R W 13 P0OUT5 0 H0 R W 12 P0OUT4 0 H0 R W 11 P0OUT3 0 H0 R W 10 P0OUT2 0 H0 R W 9 P0OUT1 0 H0 R W 8 P0OUT0 0 H0 R W 7 P0IN7 0 H0 R 6 P0IN6 0 H0 R 5 P0IN5 0 H0 R 4 P0IN4 0 H0 R 3 P0IN3 0 H0 R 2 P0IN2 0 H0 R 1 P0IN1 0 H0 R...

Page 77: ...rrupt Flag Register 15 8 0x00 R 7 P0IF7 0 H0 R W Cleared by writing 1 6 P0IF6 0 H0 R W 5 P0IF5 0 H0 R W 4 P0IF4 0 H0 R W 3 P0IF3 0 H0 R W 2 P0IF2 0 H0 R W 1 P0IF1 0 H0 R W 0 P0IF0 0 H0 R W P0INTCTL P0 Port Interrupt Control Register 15 P0EDGE7 0 H0 R W 14 P0EDGE6 0 H0 R W 13 P0EDGE5 0 H0 R W 12 P0EDGE4 0 H0 R W 11 P0EDGE3 0 H0 R W 10 P0EDGE2 0 H0 R W 9 P0EDGE1 0 H0 R W 8 P0EDGE0 0 H0 R W 7 P0IE7 0...

Page 78: ... P0yMUX 0x0 Function 0 P0yMUX 0x1 Function 1 P0yMUX 0x2 Function 2 P0yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin 24pin 32pin P00 P00 T16B Ch 0 EXCL00 UPMUX 1 P01 P01 T16B Ch 0 EXCL01 UPMUX 1 P02 P02 SNDA BZOUT UPMUX 1 P03 P03 SNDA BZOUT UPMUX 1 P04 P04 RFC Ch 0 RFCLKO0 UPMUX 1 P05 P05 RFC Ch 1 RFCLKO1 UPMUX 1 P06 P06 UPMUX 1 P07 P07 UPMUX 1 1 Refer to the Univer...

Page 79: ...P1PDPU5 0 H0 R W 12 P1PDPU4 0 H0 R W 11 P1PDPU3 0 H0 R W 10 P1PDPU2 0 H0 R W 9 P1PDPU1 0 H0 R W 8 P1PDPU0 0 H0 R W 7 P1REN7 0 H0 R W 6 P1REN6 0 H0 R W 5 P1REN5 0 H0 R W 4 P1REN4 0 H0 R W 3 P1REN3 0 H0 R W 2 P1REN2 0 H0 R W 1 P1REN1 0 H0 R W 0 P1REN0 0 H0 R W P1INTF P1 Port Interrupt Flag Register 15 8 0x00 R 7 P1IF7 0 H0 R W Cleared by writing 1 6 P1IF6 0 H0 R W 5 P1IF5 0 H0 R W 4 P1IF4 0 H0 R W 3...

Page 80: ...1 P1SEL1 0 H0 R W 0 P1SEL0 0 H0 R W P1FNCSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R W 13 12 P16MUX 1 0 0x0 H0 R W 11 10 P15MUX 1 0 0x0 H0 R W 9 8 P14MUX 1 0 0x0 H0 R W 7 6 P13MUX 1 0 0x0 H0 R W 5 4 P12MUX 1 0 0x0 H0 R W 3 2 P11MUX 1 0 0x0 H0 R W 1 0 P10MUX 1 0 0x0 H0 R W Table 6 7 2 2 P1 Port Group Function Assignment Port name P1SELy 0 P1SELy 1 M20 M23 M21 M24 M22 M25 GPIO P1y...

Page 81: ... P2IN4 0 H0 R 3 P2IN3 0 H0 R 2 P2IN2 0 H0 R 1 P2IN1 0 H0 R 0 P2IN0 0 H0 R P2IOEN P2 Port Enable Register 15 P2IEN7 0 H0 R W 14 P2IEN6 0 H0 R W 13 P2IEN5 0 H0 R W 12 P2IEN4 0 H0 R W 11 P2IEN3 0 H0 R W 10 P2IEN2 0 H0 R W 9 P2IEN1 0 H0 R W 8 P2IEN0 0 H0 R W 7 P2OEN7 0 H0 R W 6 P2OEN6 0 H0 R W 5 P2OEN5 0 H0 R W 4 P2OEN4 0 H0 R W 3 P2OEN3 0 H0 R W 2 P2OEN2 0 H0 R W 1 P2OEN1 0 H0 R W 0 P2OEN0 0 H0 R W P...

Page 82: ... 0 H0 R W 6 P2IE6 0 H0 R W 5 P2IE5 0 H0 R W 4 P2IE4 0 H0 R W 3 P2IE3 0 H0 R W 2 P2IE2 0 H0 R W 1 P2IE1 0 H0 R W 0 P2IE0 0 H0 R W P2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 P2CHATEN7 0 H0 R W 6 P2CHATEN6 0 H0 R W 5 P2CHATEN5 0 H0 R W 4 P2CHATEN4 0 H0 R W 3 P2CHATEN3 0 H0 R W 2 P2CHATEN2 0 H0 R W 1 P2CHATEN1 0 H0 R W 0 P2CHATEN0 0 H0 R W P2MODSEL P2 Port Mode Select Register 15...

Page 83: ...Port Multiplexer chapter 6 7 4 P3 Port Group The P3 port group supports the GPIO and interrupt functions Table 6 7 4 1 Control Registers for P3 Port Group Register name Bit Bit name Initial Reset R W Remarks M20 M23 M21 M24 M22 M25 24pin 32pin P3DAT P3 Port Data Register 15 P3OUT7 0 H0 R W 14 P3OUT6 0 H0 R W 13 P3OUT5 0 H0 R W 12 P3OUT4 0 H0 R W 11 P3OUT3 0 H0 R W 10 P3OUT2 0 H0 R W 9 P3OUT1 0 H0 ...

Page 84: ...rrupt Flag Register 15 8 0x00 R 7 P3IF7 0 H0 R W Cleared by writing 1 6 P3IF6 0 H0 R W 5 P3IF5 0 H0 R W 4 P3IF4 0 H0 R W 3 P3IF3 0 H0 R W 2 P3IF2 0 H0 R W 1 P3IF1 0 H0 R W 0 P3IF0 0 H0 R W P3INTCTL P3 Port Interrupt Control Register 15 P3EDGE7 0 H0 R W 14 P3EDGE6 0 H0 R W 13 P3EDGE5 0 H0 R W 12 P3EDGE4 0 H0 R W 11 P3EDGE3 0 H0 R W 10 P3EDGE2 0 H0 R W 9 P3EDGE1 0 H0 R W 8 P3EDGE0 0 H0 R W 7 P3IE7 0...

Page 85: ...3yMUX 0x1 Function 1 P3yMUX 0x2 Function 2 P3yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin 24pin 32pin P30 P30 UPMUX 1 ADC12A VREFA0 P31 P31 CLG EXOSC UPMUX 1 P32 P32 RTCA RTC1S UPMUX 1 SVD3 EXSVD0 P33 P33 RFC Ch 0 SENB0 UPMUX 1 P34 P34 RFC Ch 0 SENA0 UPMUX 1 P35 P35 RFC Ch 0 REF0 UPMUX 1 P36 P36 RFC Ch 0 RFIN0 UPMUX 1 P37 P37 RFC Ch 1 SENB1 UPMUX 1 1 Refer to the...

Page 86: ...P4EDGE0 0 H0 R W 7 3 0x00 R 2 P4IE2 0 H0 R W 1 P4IE1 0 H0 R W 0 P4IE0 0 H0 R W P4CHATEN P4 Port Chattering Filter Enable Register 15 8 0x00 R 7 3 0x00 R 2 P4CHATEN2 0 H0 R W 1 P4CHATEN1 0 H0 R W 0 P4CHATEN0 0 H0 R W P4MODSEL P4 Port Mode Select Register 15 8 0x00 R 7 3 0x00 R 2 P4SEL2 0 H0 R W 1 P4SEL1 0 H0 R W 0 P4SEL0 0 H0 R W P4FNCSEL P4 Port Function Select Register 15 8 0x00 R 7 6 0x0 R 5 4 P...

Page 87: ...W 9 PDOUT1 0 H0 R W 8 PDOUT0 0 H0 R W 7 5 0 R 4 PDIN4 X H0 R 3 PDIN3 X H0 R 2 0 R 1 PDIN1 X H0 R 0 PDIN0 X H0 R PDIOEN Pd Port Enable Register 15 13 0x0 R 12 PDIEN4 0 H0 R W 11 PDIEN3 0 H0 R W 10 reserved 0 H0 R W 9 PDIEN1 0 H0 R W 8 PDIEN0 0 H0 R W 7 5 0 R 4 PDOEN4 0 H0 R W 3 PDOEN3 0 H0 R W 2 PDOEN2 0 H0 R W 1 PDOEN1 0 H0 R W 0 PDOEN0 0 H0 R W PDRCTL Pd Port Pull up down Control Register 15 13 0...

Page 88: ...yMUX 0x1 Function 1 PDyMUX 0x2 Function 2 PDyMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin 24pin 32pin Pd0 PD0 DBG DST2 Pd1 PD1 DBG DSIO Pd2 PD2 DBG DCLK Pd3 PD3 CLG OSC3 Pd4 PD4 CLG OSC4 6 7 7 Common Registers between Port Groups Table 6 7 7 1 Control Registers for Common Use with Port Groups Register name Bit Bit name Initial Reset R W Remarks M20 M23 M21 M24 M22...

Page 89: ...H 1 0 PxyPERISEL 2 0 Output data selector Peripheral circuit I O port Pxy Internal data bus Figure 7 1 1 UPMUX Configuration 7 2 Peripheral Circuit I O Function Assignment An I O function of a peripheral circuit supported may be assigned to peripheral I O function 1 of an I O port listed above The following shows the procedure to assign a peripheral I O function and enable it in the I O port 1 Con...

Page 90: ... circuit channel number See Table 7 3 1 Bits 10 8 PxzPERISEL 2 0 Bits 2 0 PxyPERISEL 2 0 These bits specify a peripheral circuit See Table 7 3 1 Table 7 3 1 Peripheral I O Function Selections PxUPMUXn PxyPPFNC 2 0 bits Peripheral I O function PxUPMUXn PxyPERISEL 2 0 bits Peripheral circuit 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 None I2C SPIA UART3 T16B Reserved Reserved Reserved PxUPMUXn PxyPERICH 1 0 bi...

Page 91: ...2 must be supplied to WDT2 from the clock generator The CLK_WDT2 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following WDTCLK register bits WDTCLK CLKSRC 1 0 bits Clock...

Page 92: ...unter must be reset periodically via software while WDT2 is running 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Write 1 to the WDTCTL WDTCNTRST bit Reset WDT2 counter 3 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection A location should be provided for periodically processing this routine Process this routine within the tWDT cycle After...

Page 93: ...r reset after clearing SLEEP mode reset WDT2 before executing the slp instruction WDT2 should also be stopped as required us ing the WDTCTL WDTRUN 3 0 bits 8 4 Control Registers WDT2 Clock Control Register Register name Bit Bit name Initial Reset R W Remarks WDTCLK 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP Bits 15 9 Reserved Bit 8 DBRUN...

Page 94: ... Bit 8 STATNMI This bit indicates that a counter compare match and NMI have occurred 1 R NMI counter compare match occurred 0 R NMI not occurred When the NMI generation function of WDT2 is used read this bit in the NMI handler routine to con firm that WDT2 was the source of the NMI The WDTCTL STATNMI bit set to 1 is cleared to 0 by writing 1 to the WDTCTL WDTCNTRST bit Bits 7 5 Reserved Bit 4 WDTC...

Page 95: ...Epson Corporation 8 5 TECHNICAL MANUAL Rev 1 0 Bits 9 0 CMP 9 0 These bits set the NMI reset generation cycle The value set in this register is compared with the 10 bit counter value while WDT2 is running and an NMI or reset is generated when they are matched ...

Page 96: ...Hz RTC 16HZ 8 Hz RTC 8HZ 4 Hz RTC 4HZ 2 Hz RTC 2HZ 1 Hz RTC 1HZ Clock generator Interrupt controller RTCTRMBSY RTCHLD RTC24H RTCADJ Stopwatch count control circuit Interrupt control circuit SWRST SWRUN SW1IE SW10IE SW100IE ALARMIE 1DAYIE 1HURIE 1MINIE 1SECIE 1_2SECIE 1_4SECIE 1_8SECIE 1_32SECIE SW1IF SW10IF SW100IF ALARMIF 1DAYIF 1HURIF 1MINIF 1SECIF 1_2SECIF 1_4SECIF 1_8SECIF 1_32SECIF RTCRST RTC...

Page 97: ...l regulation can be specified within the range from 64 to 63 and it should be written to the RTCCTL RTCTRM 6 0 bits as a two s complement number Use Eq 9 1 to calculate the correction value m RTCTRM 6 0 256 n However RTCTRM 6 0 is an integer after rounding off to 64 to 63 Eq 9 1 106 Where n Theoretical regulation execution cycle time second time interval to write the correct value to the RTCCTL RT...

Page 98: ...te 30 second correction using a time signal to adjust the time For more information on the 30 second correction refer to Real Time Clock Counter Operations 6 Write 1 to the real time clock counter interrupt flags in the RTCINTF register to clear them 7 Write 1 to the interrupt enable bits in the RTCINTE register to enable real time clock counter interrupts Time read 1 Check to see if the RTCCTL RT...

Page 99: ...59 seconds or clears the second counter with the minute counter left unchanged if the second counter represents 0 to 29 seconds 1 second correction If a second count up timing occurred while the RTCCTL RTCHLD bit 1 count hold state the real time clock counter counts up by 1 second performs 1 second correction after the counting has resumed by writ ing 0 to the RTCCTL RTCHLD bit Note If two or more...

Page 100: ... count up Writing 1 1 second RTCINTF 1SECIF Second counter count up Writing 1 1 2 second RTCINTF 1_2SECIF See Figure 9 5 1 Writing 1 1 4 second RTCINTF 1_4SECIF See Figure 9 5 1 Writing 1 1 8 second RTCINTF 1_8SECIF See Figure 9 5 1 Writing 1 1 32 second RTCINTF 1_32SECIF See Figure 9 5 1 Writing 1 Stopwatch 1 Hz RTCINTF SW1IF 1 10 second counter overflow Writing 1 Stopwatch 10 Hz RTCINTF SW10IF 1 ...

Page 101: ...d execution Bits 14 8 RTCTRM 6 0 Write the correction value for adjusting the 1 Hz frequency to these bits to execute theoretical regula tion For a calculation method of correction value refer to Theoretical Regulation Function Notes When the RTCCTL RTCTRMBSY bit 1 the RTCCTL RTCTRM 6 0 bits cannot be re written Writing 0x00 to the RTCCTL RTCTRM 6 0 bits sets the RTCCTL RTCTRMBSY bit to 1 as well ...

Page 102: ...d For more information on the 30 second correction refer to Real Time Clock Counter Operations Notes Be sure to avoid writing to this bit when the RTCCTL RTCBSY bit 1 Do not write 1 to this bit again while the RTCCTL RTCADJ bit 1 Bit 1 RTCRST This bit resets the 1 Hz counter the RTCCTL RTCADJ bit and the RTCCTL RTCHLD bit 1 W Reset 0 W Ineffective 1 R Reset is being executed 0 R Reset has finished...

Page 103: ...ode RTCCTL RTC24H bit 1 Bits 13 12 RTCHHA 1 0 Bits 11 8 RTCHLA 3 0 The RTCALM2 RTCHHA 1 0 bits and the RTCALM2 RTCHLA 3 0 bits set the 10 hour digit and 1 hour digit of the alarm time respectively A value within 1 to 12 o clock in 12H mode or 0 to 23 in 24H mode can be set in BCD code Bit 7 Reserved Bits 6 4 RTCMIHA 2 0 Bits 3 0 RTCMILA 3 0 The RTCALM2 RTCMIHA 2 0 bits and the RTCALM2 RTCMILA 3 0 ...

Page 104: ... bit the counter retains the value when it stopped Writing 1 to this bit again resumes counting from the value retained Note The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the RTC SWCTL SWRUN bit Therefore the counter value may be incremented 1 from the value at writing 0 RTC Second 1Hz Register Register name Bit Bit name Initial Reset R W Remarks RTCSEC 15 0 R ...

Page 105: ...Register Register name Bit Bit name Initial Reset R W Remarks RTCHUR 15 0 R 14 RTCAP 0 H0 R W 13 12 RTCHH 1 0 0x1 H0 R W 11 8 RTCHL 3 0 0x2 H0 R W 7 0 R 6 4 RTCMIH 2 0 0x0 H0 R W 3 0 RTCMIL 3 0 0x0 H0 R W Bit 15 Reserved Bit 14 RTCAP This bit is used to set and read A M or P M data in 12H mode RTCCTL RTC24H bit 0 1 R W P M 0 R W A M In 24H mode RTCCTL RTC24H bit 1 this bit is fixed at 0 and writin...

Page 106: ...The setting read values are a BCD code within the range from 1 to 12 Note Be sure to avoid writing to the RTCMON RTCMOH RTCMOL 3 0 bits while the RTCCTL RTCBSY bit 1 Bits 7 6 Reserved Bits 5 4 RTCDH 1 0 Bits 3 0 RTCDL 3 0 The RTCMON RTCDH 1 0 bits and the RTCMON RTCDL 3 0 bits are used to set and read the 10 day digit and the 1 day digit of the day counter respectively The setting read values are ...

Page 107: ...RTCCTL RT CBSY bit 1 RTC Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks RTCINTF 15 RTCTRMIF 0 H0 R W Cleared by writing 1 14 SW1IF 0 H0 R W 13 SW10IF 0 H0 R W 12 SW100IF 0 H0 R W 11 9 0x0 R 8 ALARMIF 0 H0 R W Cleared by writing 1 7 1DAYIF 0 H0 R W 6 1HURIF 0 H0 R W 5 1MINIF 0 H0 R W 4 1SECIF 0 H0 R W 3 1_2SECIF 0 H0 R W 2 1_4SECIF 0 H0 R W 1 1_8SECIF 0 H0 R W 0 1_32SE...

Page 108: ...RTCINTF 1_4SECIF bit 1 4 second interrupt RTCINTF 1_8SECIF bit 1 8 second interrupt RTCINTF 1_32SECIF bit 1 32 second interrupt RTC Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RTCINTE 15 RTCTRMIE 0 H0 R W 14 SW1IE 0 H0 R W 13 SW10IE 0 H0 R W 12 SW100IE 0 H0 R W 11 9 0x0 R 8 ALARMIE 0 H0 R W 7 1DAYIE 0 H0 R W 6 1HURIE 0 H0 R W 5 1MINIE 0 H0 R W 4 1SECIE 0 H0 R W 3...

Page 109: ...ck interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt RTCINTE ALARMIE bit Alarm interrupt RTCINTE 1DAYIE bit 1 day interrupt RTCINTE 1HURIE bit 1 hour interrupt RTCINTE 1MINIE bit 1 minute interrupt RTCINTE 1SECIE bit 1 second interrupt RTCINTE 1_2SECIE bit 1 2 second interrupt RTCINTE 1_4SECIE bit 1 4 second interrupt R...

Page 110: ... intermittent operations Three detection cycles are selectable Low power supply voltage detection count function to generate an inter rupt reset when low power supply voltage is successively detected the number of times specified Continuous operation is also possible Figure 10 1 1 shows the configuration of SVD3 Table 10 1 1 SVD3 Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C1...

Page 111: ...e Electrical Characteristics chapter 10 3 Clock Settings 10 3 1 SVD3 Operating Clock When using SVD3 the SVD3 operating clock CLK_SVD3 must be supplied to SVD3 from the clock generator The CLK_SVD3 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer ...

Page 112: ... the interrupt Write 1 to the SVDINTF SVDIF bit Clear interrupt flag Set the SVDINTE SVDIE bit to 1 Enable SVD3 interrupt 5 Set the SVDCTL MODEN bit to 1 Enable SVD3 detection 6 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection Terminating detection Follow the procedure shown below to stop SVD3 operation 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system p...

Page 113: ...eset can be generated when SVD3 has successively detected low power supply voltage the number of times speci fied by the SVDCTL SVDSC 1 0 bits 1 When the SVDCTL SVDMD 1 0 bits 0x0 continuous operation mode VSVD VSVD VDD SVDCTL MODEN SVD3 operating status SVDINTF SVDDT Low power supply voltage detection interrupt DET 2 When the SVDCTL SVDMD 1 0 bits 0x0 intermittent operation mode VSVD Level set us...

Page 114: ... the reset state is can celed After that SVD3 resumes operating in the operation mode set previously via the initialization routine During reset state the SVD3 control bits are set as shown in Table 10 5 2 1 Table 10 5 2 1 SVD3 Control Bits During Reset State Control register Control bit Setting SVDCLK DBRUN Reset to the initial values CLKDIV 2 0 CLKSRC 1 0 SVDCTL VDSEL The set value is retained S...

Page 115: ...Bits 14 13 SVDSC 1 0 These bits set the condition to generate an interrupt reset number of successive low voltage detec tions in intermittent operation mode SVDCTL SVDMD 1 0 bits 0x1 to 0x3 Table 10 6 2 Interrupt Reset Generating Condition in Intermittent Operation Mode SVDCTL SVDSC 1 0 bits Interrupt reset generating condition 0x3 Low power supply voltage is successively detected eight times 0x2 ...

Page 116: ...and continuous operation modes refer to SVD3 Operations Bit 0 MODEN This bit enables disables for the SVD3 circuit to operate 1 R WP Enable Start detection operations 0 R WP Disable Stop detection operations After this bit has been altered wait until the value written is read out from this bit without subsequent operations being performed Notes Writing 0 to the SVDCTL MODEN bit resets the SVD3 har...

Page 117: ...3 is in opera tion after 1 is written to the SVDCTL MODEN bit SVD3 Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SVDINTE 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0 H0 R W Bits 15 1 Reserved Bit 0 SVDIE This bit enables low power supply voltage detection interrupts 1 R W Enable interrupts 0 R W Disable interrupts Notes If the SVDCTL SVDRE 3 0 bits are set to 0xa no low power ...

Page 118: ...e provided Peripheral clock output Outputs the counter underflow signal Ch 1 Synchronous serial interface Ch 0 master clock Ch 2 Synchronous serial interface Ch 1 master clock Ch 3 12 bit A D converter trigger signal T16 Ch n To interrupt controller To peripheral circuit Underflow PRESET Timer control circuit Interrupt control circuit PRUN TRMD CLKSRC 1 0 CLKDIV 3 0 Clock generator UFIE UFIF DBRUN...

Page 119: ...6_n supply during DEBUG mode should be controlled using the T16_nCLK DBRUN bit The CLK_T16_n supply to T16 Ch n is suspended when the CPU enters DEBUG mode if the T16_nCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_T16_n supply resumes Although T16 Ch n stops operat ing when the CLK_T16_n supply is suspended the counter and registers retain the status before DEBUG mode was entered If...

Page 120: ... operating clock frequency Hz 11 4 3 Operations in Repeat Mode T16 Ch n enters repeat mode by setting the T16_nMOD TRMD bit to 0 In repeat mode the count operation starts by writing 1 to the T16_nCTL PRUN bit and continues until 0 is written A counter underflow presets the T16_nTR register value to the counter so underflow occurs periodically Select this mode to generate periodic underflow interru...

Page 121: ...ag Set condition Clear condition Underflow T16_nINTF UFIF When the counter underflows Writing 1 T16 provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller c...

Page 122: ... IC cannot be selected as the clock source Note 2 When the T16_nCLK CLKSRC 1 0 bits are set to 0x3 EXCLm is selected for the channel with an event counter function or EXOSC is selected for other channels T16 Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks T16_nMOD 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W Bits 15 1 Reserved Bit 0 TRMD This bit selects the T16 operation mode 1 ...

Page 123: ...lying operating clock 0 R W Disable Stop supplying operating clock T16 Ch n Reload Data Register Register name Bit Bit name Initial Reset R W Remarks T16_nTR 15 0 TR 15 0 0xffff H0 R W Bits 15 0 TR 15 0 These bits are used to set the initial value to be preset to the counter The value set to this register will be preset to the counter when 1 is written to the T16_nCTL PRESET bit or when the counte...

Page 124: ...r name Bit Bit name Initial Reset R W Remarks T16_nINTE 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W Bits 15 1 Reserved Bit 0 UFIE This bit enables T16 Ch n underflow interrupts 1 R W Enable interrupts 0 R W Disable interrupts Note To prevent generating unnecessary interrupts the corresponding interrupt flag should be cleared before enabling interrupts ...

Page 125: ...smission parity error framing error and overrun error interrupts Input pin can be pulled up with an internal resistor The output pin is configurable as an open drain output Provides the carrier modulation output function Figure 12 1 1 shows the UART3 configuration Table 12 1 1 UART3 Channel Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 ...

Page 126: ...Nn pin 12 2 4 Output Pin Open Drain Output Function The USOUTn pin supports the open drain output function Default configuration is a push pull output and it is switched to an open drain output by setting the UAnMOD OUTMD bit to 1 12 2 5 Input Output Signal Inverting Function The UART3 can invert the signal polarities of the USINn pin input and the USOUTn pin output by setting the UAn MOD INVRX bi...

Page 127: ...ed by the UAnMOD BRDIV UAnBR BRT 7 0 and UAnBR FMD 3 0 bit settings Use the following equations to calculate the setting values for obtaining the desired transfer rate CLK_UART3 CLK_UART3 bps BRT BRDIV FMD 1 Eq 12 1 BRT 1 bps FMD BRDIV Where bps Transfer rate bit s CLK_UART3 UART3 operating clock frequency Hz BRDIV Baud rate division ratio 1 16 or 1 4 Selected by the UAnMOD BRDIV bit BRT UAnBR BRT...

Page 128: ...nMOD INVTX bit Enable disable USOUTn output signal inversion UAnMOD PUEN bit Enable disable USINn pin pull up UAnMOD OUTMD bit Enable disable USOUTn pin open drain output UAnMOD IRMD bit Enable disable IrDA interface UAnMOD CHLN bit Set data length 7 or 8 bits UAnMOD PREN bit Enable disable parity function UAnMOD PRMD bit Select parity mode even or odd UAnMOD STPB bit Set stop bit length 1 or 2 bi...

Page 129: ...set to 1 transmit busy The shift register data bits are then output successively from the LSB Following output of MSB the parity bit if parity is en abled and the stop bit are output Even if transmit data is being output from the USOUTn pin the next transmit data can be written to the UAnTXD register after making sure the UAnINTF TBEIF bit is set to 1 If no transmit data remains in the UAnTXD regi...

Page 130: ...ts and loads the received data into the receive shift register The UAnINTF RBSY bit is set to 1 when the start bit is detected The UAnINTF RBSY bit is cleared to 0 and the receive shift register data is transferred to the receive data buf fer at the stop bit receive timing The receive data buffer consists of a 2 byte FIFO and receives data until it becomes full When the receive data buffer receive...

Page 131: ...width is converted into 3 16 by the RZI modulator in SIR method Modulator input shift register output Modulator output USOUTn T1 T1 3 16 T1 3 16 Figure 12 5 4 2 IrDA Transmission Signal Waveform The received IrDA signal is input to the RZI demodulator and the low pulse width is converted into the normal width before input to the receive shift register Demodulator input USINn Demodulator output shi...

Page 132: ...n error is still transferred to the receive data buffer and the UAnINTF FEIF bit framing error interrupt flag is set to 1 when the data becomes ready to read from the UAnRXD register Note Framing error parity error interrupt flag set timings These interrupt flags will be set after the data that encountered an error is transferred to the re ceive data buffer Note however that the set timing depends...

Page 133: ...When the second received data byte is loaded to the receive data buffer in which the first byte is already received Reading received data or software reset Receive buffer one byte full UAnINTF RB1FIF When the first received data byte is load ed to the emptied receive data buffer Reading data to empty the receive data buffer or software reset Transmit buffer empty UAnINTF TBEIF When transmit data w...

Page 134: ...H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W Bits 15 13 Reserved Bit 12 PECAR This bit selects the carrier modulation period 1 R W Carrier modulation during H data period 0 R W Carrier modulation during L data period Bit 11 CAREN This bit enables the carrier modulation function 1 R W Enable carrier mo...

Page 135: ...RMD This bit selects either odd parity or even parity when using the parity function 1 R W Odd parity 0 R W Even parity Bit 0 STPB This bit sets the stop bit length 1 R W 2 bits 0 R W 1 bit Notes The UAnMOD register settings can be altered only when the UAnCTL MODEN bit 0 Do not set both the UAnMOD IRMD and UAnMOD CAREN bits simultaneously UART3 Ch n Baud Rate Register Register name Bit Bit name I...

Page 136: ...s supplied 0 R W Disable UART3 operations The operating clock is stopped Note If the UAnCTL MODEN bit is altered from 1 to 0 while sending receiving data the data being sent received cannot be guaranteed When setting the UAnCTL MODEN bit to 1 again after that be sure to write 1 to the UAnCTL SFTRST bit as well UART3 Ch n Transmit Data Register Register name Bit Bit name Initial Reset R W Remarks U...

Page 137: ...iving status See Figure 12 5 3 1 1 R During receiving 0 R Idle Bit 8 TBSY This bit indicates the sending status See Figure 12 5 2 1 1 R During sending 0 R Idle Bit 7 Reserved Bit 6 TENDIF Bit 5 FEIF Bit 4 PEIF Bit 3 OEIF Bit 2 RB2FIF Bit 1 RB1FIF Bit 0 TBEIF These bits indicate the UART3 interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear ...

Page 138: ...isable interrupts The following shows the correspondence between the bit and interrupt UAnINTE TENDIE bit End of transmission interrupt UAnINTE FEIE bit Framing error interrupt UAnINTE PEIE bit Parity error interrupt UAnINTE OEIE bit Overrun error interrupt UAnINTE RB2FIE bit Receive buffer two bytes full interrupt UAnINTE RB1FIE bit Receive buffer one byte full interrupt UAnINTE TBEIE bit Transmi...

Page 139: ...external input clock SPICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by an SPIA interrupt Input pins can be pulled up down with an internal resistor Figure 13 1 1 shows the SPIA configuration Table 13 1 1 SPIA Channel Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 pin package Number of channels 2 chann...

Page 140: ...r functions the SPIA input output function must be assigned to the port before activating SPIA For more information refer to the I O Ports chapter 13 2 2 External Connections SPIA operates in master mode or slave mode Figures 13 2 2 1 and 13 2 2 2 show connection diagrams between SPIA in each mode and external SPI devices Px1 Px2 Px3 SDIn SDOn SPICLKn SPISS SDO SDI SPICLK SPISS SDO SDI SPICLK SPIS...

Page 141: ... or SDIn SPICLKn and SPISSn pins in slave mode have a pull up or pull down function as shown in Table 13 2 4 1 This function is enabled by setting the SPInMOD PUEN bit to 1 Table 13 2 4 1 Pull Up or Pull Down of Input Pins Pin Master mode Slave mode SDIn Pull up Pull up SPICLKn SPInMOD CPOL bit 1 Pull up SPInMOD CPOL bit 0 Pull down SPISSn Pull up 13 3 Clock Settings 13 3 1 SPIA Operating Clock Op...

Page 142: ...ng the T16_mCLK DB RUN bit The CLK_T16_m supply to SPIA Ch n is suspended when the CPU enters DEBUG mode if the T16_mCLK DB RUN bit 0 After the CPU returns to normal mode the CLK_T16_m supply resumes Although SPIA Ch n stops operating when the CLK_T16_m supply is suspended the output pins and registers retain the status before DEBUG mode was entered If the T16_mCLK DBRUN bit 1 the CLK_T16_m supply...

Page 143: ...InMOD register bits SPInMOD PUEN bit Enable input pin pull up down SPInMOD NOCLKDIV bit Select master mode operating clock SPInMOD LSBFST bit Select MSB first LSB first SPInMOD CPHA bit Select clock phase SPInMOD CPOL bit Select clock polarity SPInMOD MST bit Select master slave mode 3 Assign the SPIA Ch n input output function to the ports Refer to the I O Ports chapter 4 Set the following SPInCT...

Page 144: ...Even if the clock is being output from the SPICLKn pin the next transmit data can be written to the SPInTXD register after making sure the SPInINTF TBEIF bit is set to 1 If transmit data has not been written to the SPInTXD register after the last clock is output from the SPICLKn pin the clock output halts and the SPInINTF TENDIF bit is set to 1 At the same time SPIA issues an end of transmission i...

Page 145: ...ta sending operations when transmit data may be dummy data if data transmission is not required is written to the SPInTXD register The SPICLKn pin outputs clocks of the number of the bits specified by the SPInMOD CHLN 3 0 bits The transmit data bits are output in sequence from the SDOn pin in sync with these clocks and the receive data bits input from the SDIn pin are shifted into the shift regist...

Page 146: ...output from a general purpose port Assert the slave select signal output from a general purpose port Figure 13 5 3 2 Data Reception Flowcharts in Master Mode 13 5 4 Terminating Data Transfer in Master Mode A procedure to terminate data transfer in master mode is shown below 1 Wait for an end of transmission interrupt SPInINTF TENDIF bit 1 2 Set the SPInCTL MODEN bit to 0 to disable the SPIA Ch n o...

Page 147: ...d Slave mode starts data transfer when SPICLKn is input from the external SPI master after the SPISSn signal is asserted Writing transmit data is not a trigger to start data transfer Therefore it is not necessary to write dummy data to the transmit data buffer when performing data reception only Data transmission reception can be performed even in SLEEP mode it makes it possible to wake the CPU up...

Page 148: ...d of transmission SPInINTF TENDIF When the SPInINTF TBEIF bit 1 after data of the specified bit length defined by the SPInMOD CHLN 3 0 bits has been sent Writing 1 Receive buffer full SPInINTF RBFIF When data of the specified bit length is received and the received data is transferred from the shift register to the received data buffer Reading the SPIn RXD register Transmit buffer empty SPInINTF T...

Page 149: ...TENDIF SPInMOD register 1 2 3 7 8 CPHA bit 1 0 CPOL bit 1 0 Writing data to the SPInTXD register Figure 13 6 1 SPInINTF BSY and SPInINTF TENDIF Bit Set Timings when SPInMOD CHLN 3 0 bits 0x7 13 7 Control Registers SPIA Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks SPInMOD 15 12 0x0 R 11 8 CHLN 3 0 0x7 H0 R W 7 6 0x0 R 5 PUEN 0 H0 R W 4 NOCLKDIV 0 H0 R W 3 LSBFST 0 H0 R W ...

Page 150: ...r mode This setting is ineffective in slave mode 1 R W SPICLKn frequency CLK_SPIAn frequency 16 bit timer operating clock frequency 0 R W SPICLKn frequency 16 bit timer output frequency 2 For more information refer to SPIA Operating Clock Bit 3 LSBFST This bit configures the data format input output permutation 1 R W LSB first 0 R W MSB first Bit 2 CPHA Bit 1 CPOL These bits set the SPI clock phas...

Page 151: ...master mode writing to these bits starts data transfer Transmit data can be written when the SPInINTF TBEIF bit 1 regardless of whether data is being output from the SDOn pin or not Note that the upper data bits that exceed the data bit length configured by the SPInMOD CHLN 3 0 bits will not be output from the SDOn pin Note Be sure to avoid writing to the SPInTXD register when the SPInINTF TBEIF b...

Page 152: ...NTF OEIF bit Overrun error interrupt SPInINTF TENDIF bit End of transmission interrupt SPInINTF RBFIF bit Receive buffer full interrupt SPInINTF TBEIF bit Transmit buffer empty interrupt SPIA Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SPInINTE 15 8 0x00 R 7 4 0x0 R 3 OEIE 0 H0 R W 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W Bits 15 4 Reserved Bit 3 ...

Page 153: ...de supports automatic bus clear sending function Can generate receive buffer full transmit buffer empty and other interrupts Figure 14 1 1 shows the I2C configuration Table 14 1 1 I2C Channel Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 pin package Number of channels 1 channel Ch 0 I2C Ch n Interrupt control circuit BYTEENDIE GCIE NACK...

Page 154: ...lock SCL lines must be pulled up with an external resistor When the I2C is set into master mode one or more slave devices that have a unique address may be connected to the I2C bus When the I2C is set into slave mode one or more master and slave devices that have a unique address may be connected to the I2C bus SCLn VDD SDAn S1C17 Serial data SDA Serial clock SCL I2C bus External I2C device Extern...

Page 155: ... Mode In master mode the CLK_I2Cn supply during DEBUG mode should be controlled using the I2CnCLK DBRUN bit The CLK_I2Cn supply to the I2C Ch n is suspended when the CPU enters DEBUG mode if the I2CnCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_I2Cn supply resumes Although the I2C Ch n stops oper ating when the CLK_I2Cn supply is suspended the output pin and registers retain the sta...

Page 156: ...C in master mode 1 Configure the operating clock and the baud rate generator using the I2CnCLK and I2CnBR registers 2 Assign the I2C Ch n input output function to the ports Refer to the I O Ports chapter 3 Set the following bits when using the interrupt Write 1 to the interrupt flags in the I2CnINTF register Clear interrupt flags Set the interrupt enable bits in the I2CnINTE register to 1 Enable i...

Page 157: ...START condition when the I2CnCTL TXSTART bit is set to 1 When the generating operation has completed the I2C Ch n clears the I2CnCTL TXSTART bit to 0 and sets both the I2CnINTF STARTIF and I2CnINTF TBEIF bits to 1 Sending slave address and data If the I2CnINTF TBEIF bit 1 a slave address or data can be written to the I2CnTXD register The I2C Ch n pulls down SCL to low and enters standby state unti...

Page 158: ...erations by the external slave Standby state SCL low TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A S TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A TBEIF 1 TBEIF 1 NACKIF 1 NACKIF 1 NACKIF 1 Figure 14 4 2 1 Example of Data Sending Operations in Master Mode Data transmission End Write slave address and WRITE 0 to the I2CnTXD...

Page 159: ...CTL TXNACK bit to send a NACK after the last data is received and then go to Step 7 ii When the last data is received read the received data from the I2CnRXD register and set the I2CnCTL TXSTOP to 1 to generate a STOP condition Then go to Step 9 7 Read the received data from the I2CnRXD register 8 Repeat Steps 5 to 7 until the end of data reception 9 Wait for a STOP condition interrupt I2CnINTF ST...

Page 160: ...tion A ACK A NACK Saddr R Slave address R 1 Data n 8 bit data Hardware bit operations Operations by the external slave Standby state SCL low RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 Figure 14 4 3 1 Example of Data Receiving Operations in Master Mode Data reception Write 1 to the I2CnCTL TXNACK bit YES NO One byte reception End Write slave address and READ 1 to the I2CnTXD register Write ...

Page 161: ...START condition by setting the I2CnCTL TXSTART bit to 1 2 Wait for a transmit buffer empty interrupt I2CnINTF TBEIF bit 1 or a START condition interrupt I2C nINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 3 Write the first address to the I2CnTXD TXD 7 1 bits and 0 that represents WRITE as the data transfer di rection to the I2CnTXD TXD0 bit 4 Wait f...

Page 162: ...e A data sending procedure in slave mode and the I2C Ch n operations are shown below Figures 14 4 5 1 and 14 4 5 2 show an operation example and a flowchart respectively Data sending procedure 1 Wait for a START condition interrupt I2CnINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 2 Check to see if the I2CnINTF TR bit 1 transmission mode Start a da...

Page 163: ...itten during data transmission If the I2CnINTF TBEIF bit is still set to 1 when the data transmission from the shift register has completed the I2C Ch n pulls down SCL to low sets the I2C bus into clock stretching state until transmit data is written to the I2CnTXD register If the next transmit data already exists in the I2CnTXD register or data has been written after the above the I2C Ch n sends ...

Page 164: ...I2CnINTF STOPIF bit 1 or a START condition interrupt I2CnINTF STARTIF bit 1 i Go to Step 10 when a STOP condition interrupt has occurred ii Go to Step 3 when a START condition interrupt has occurred 10 Clear the I2CnINTF STOPIF bit and then terminate data receiving operations Data receiving operations START condition detection and slave address check It is the same as the data transmission in slav...

Page 165: ...as the data transmission in slave mode S P Sr A STARTIF 1 BSY 0 STOPIF 1 Saddr W A Data 1 A Data 2 A Data N A RXD 7 0 Data 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 P Sr A Data N TXNACK 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 I2C bus Clock stretching by I2C Software bit operations Operations by the external maste...

Page 166: ...a sending mode A 1stAddr W A 2ndAddr A 1stAddr W A 2ndAddr At start of data transmission At start of data reception S STARTIF 1 STARTIF 1 A Data 1 A Data 2 I2C bus Clock stretching by I2C I2C bus Clock stretching by I2C Software bit operations Operations by the external master S START condition Sr Repeated START condition P STOP condition A ACK A NACK 1stAddr W 1st address W 0 1stAddr R 1st addres...

Page 167: ...an be performed The table below lists the hardware error detection conditions and the notification method Table 14 4 9 1 Hardware Error Detection Function No Error detecting period timing I2C bus line monitored and error condition Notification method 1 While the I2C Ch n controls SDA to high for sending address data or a NACK SDA low I2CnINTF ERRIF 1 2 Master mode only When 1 is written to the I2C...

Page 168: ... condition is issued Slave mode When an address match is detected including general call Writing 1 software reset Error detection I2CnINTF ERRIF Refer to Error Detection Writing 1 software reset Receive buffer full I2CnINTF RBFIF When received data is loaded to the receive data buffer Reading received data to empty the receive data buffer software reset Transmit buffer empty I2CnINTF TBEIF Master mode...

Page 169: ... CLKSRC 1 0 0x0 H0 R W Bits 15 9 Reserved Bit 8 DBRUN This bit sets whether the I2C operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the I2C operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the I2C Table 14...

Page 170: ...ister Register name Bit Bit name Initial Reset R W Remarks I2CnBR 15 8 0x00 R 7 0 R 6 0 BRT 6 0 0x7f H0 R W Bits 15 7 Reserved Bits 6 0 BRT 6 0 These bits set the I2C Ch n transfer rate for master mode For more information refer to Baud Rate Generator Notes The I2CnBR register settings can be altered only when the I2CnCTL MODEN bit 0 Be sure to avoid setting the I2CnBR register to 0 I2C Ch n Own A...

Page 171: ...rating a STOP condition 0 R STOP condition has been generated This bit is automatically cleared when the bus free time tBUF defined in the I2C Specifications has elapsed after the STOP condition has been generated Bit 2 TXSTART This bit issues a START condition in master mode This bit is ineffective in slave mode 1 W Issue a START condition 0 W Ineffective 1 R On standby or during generating a STA...

Page 172: ...ise transmit data cannot be guaranteed I2C Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks I2CnRXD 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R Bits 15 8 Reserved Bits 7 0 RXD 7 0 The receive data buffer can be read through these bits I2C Ch n Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks I2CnINTF 15 13 0x0 R 12 SDALOW 0 H0 R 11 SCLLOW...

Page 173: ...urred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt I2CnINTF BYTEENDIF bit End of transfer interrupt I2CnINTF GCIF bit General call address reception interrupt I2CnINTF NACKIF bit NACK reception interrupt I2CnINTF STOPIF bit STOP condition interrupt I2CnINTF STARTIF bit START condition interrupt I2CnINTF ERRIF bit Error detection interrupt I2Cn...

Page 174: ... interrupts The following shows the correspondence between the bit and interrupt I2CnINTE BYTEENDIE bit End of transfer interrupt I2CnINTE GCIE bit General call address reception interrupt I2CnINTE NACKIE bit NACK reception interrupt I2CnINTE STOPIE bit STOP condition interrupt I2CnINTE STARTIE bit START condition interrupt I2CnINTE ERRIE bit Error detection interrupt I2CnINTE RBFIE bit Receive bu...

Page 175: ... generate interrupt sig nals and a PWM waveform Can be used as an interval timer PWM waveform generator and external event counter The capture circuit captures counter values using external software trigger signals and generates interrupts Can be used to measure external event periods cycles Figure 15 1 1 shows the T16B configuration Table 15 1 1 T16B Channel Configuration of S1C17M20 M21 M22 M23 ...

Page 176: ...ternal data bus TOUT control circuit 1 TOUT00 TOUT control circuit 0 TOUTMT TOUTO TOUTMD 2 0 TOUTINV TOUTMT TOUTO TOUTMD 2 0 TOUTINV Interrupt control circuit CAPOWmIE CMPCAPmIE CAPOW0IE CMPCAP0IE CNTMAXIE CNTZEROIE CAPI1 CAPOWmIF CMPCAPmIF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF UP_DOWN BSY MATCH signal MATCH signal ZERO MAX signal CAP02 03 TOUT02 03 CAP04 05 TOUT04 05 CAPn0 1 TOUTn0 1 CAPn2 3 TOUT...

Page 177: ...tained at those before enter ing SLEEP mode After the CPU returns to normal mode CLK_T16Bn is supplied and the T16B operation re sumes 15 3 3 Clock Supply in DEBUG Mode The CLK_T16Bn supply during DEBUG mode should be controlled using the T16BnCLK DBRUN bit The CLK_T16Bn supply to T16B Ch n is suspended when the CPU enters DEBUG mode if the T16BnCLK DB RUN bit 0 After the CPU returns to normal mod...

Page 178: ...llowing bits when using the interrupt Write 1 to the interrupt flags in the T16BnINTF register Clear interrupt flags Set the interrupt enable bits in the T16BnINTE register to 1 Enable interrupts 7 Set the following T16BnCTL register bits T16BnCTL CNTMD 1 0 bits Select count up down operation T16BnCTL ONEST bit Select one shot repeat operation Set the T16BnCTL PRESET bit to 1 Reset counter Set the...

Page 179: ...uld be written after the counter has been reset to the previously set MAX value Counter reset Setting the T16BnCTL PRESET bit to 1 resets the counter This clears the counter to 0x0000 in up or up down mode or presets the MAX value to the counter in down mode The counter is also cleared to 0x0000 when the counter value exceeds the MAX value during count up operation Counting start To start counting...

Page 180: ...es Operations in repeat down count and one shot down count modes In these modes the counter operates as a down counter and counts from the MAX value or current value to 0x0000 In repeat down count mode the counter returns to the MAX value if a counter underflow occurs and continues counting until the T16BnCTL RUN bit is set to 0 If the MAX value is altered during counting the counter keeps countin...

Page 181: ... than the current counter value during count up operation the counter keeps counting up to the new MAX value If the MAX value is altered to a value smaller than the current counter value the counter is cleared to 0x0000 and continues counting up to the new MAX value If the MAX value is altered during count down operation the counter keeps counting down to 0x0000 and then starts counting up to the ...

Page 182: ...tched The T16BnCCRm register functions as the compare data register used for setting a comparison value in this mode The TOUTnm CAPnm pin is configured to the TOUTnm pin When the counter reaches the value set in the T16BnCCRm register during counting the comparator asserts the MATCH signal and sets the T16BnINTF COMPCAPmIF bit compare interrupt flag to 1 When the counter reaches the MAX value in c...

Page 183: ...register setting value 0 to 65 535 MAX T16BnMC register setting value 0 to 65 535 fCLK_T16B Count clock frequency Hz The comparator MATCH signal and counter MAX ZERO signals are also used to generate a timer output wave form TOUT Refer to TOUT Output Control for more information Compare buffer The comparator loads the comparison value which has been written to the T16BnCCRm register to the compare...

Page 184: ...xffff 0x0000 1 3 T16BnCCCTLm CBUFMD 2 0 bits 0x2 Count cycle RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTMAXIF 1 CNTMAXIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Compare period Counter Time Compare buffer value MAX value T16BnMC register 0xffff 0x0000 1 4 T16BnCCCTLm CBUFMD 2 0 bits 0x3 Count cycle RUN 1 Data W CC 15 0 Data...

Page 185: ...Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16BnMC register Count cycle Compare period 2 1 T16BnCCCTLm CBUFMD 2 0 bits 0x0 2 Repeat down count mode Software operation Hardware operation 2 2 T16BnCCCTLm CBUFMD 2 0 bits 0x1 0xffff 0x0000 RUN 1 Data W CC 1...

Page 186: ...re period 2 4 T16BnCCCTLm CBUFMD 2 0 bits 0x3 0xffff 0x0000 RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16BnMC register Count cycle Compare period 2 5 T16BnCCCTLm CBUFMD 2 0 bits 0x4 0xffff 0x0000 RUN 1 Data W CC 15 0 Data W CC 15 0...

Page 187: ...unting up 3 2 T16BnCCCTLm CBUFMD 2 0 bits 0x1 CNTZEROIF 1 0xffff 0x0000 RUN 1 Data W MC 15 0 Data W CC 15 0 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTZEROIF 1 CNTMAXIF 1 PRESET 1 Counter Time Count cycle Compare buffer value MAX value T16BnMC register Compare period during counting down Compare period during counting up 3 3 T16BnCCCTLm CBUF...

Page 188: ...re Figure 15 4 3 2 Compare Buffer Operations Operations in capture mode The capture mode captures the counter value when an external event such as a key entry occurs at the speci fied edge of the external input software trigger signal In this mode the T16BnCCRm register functions as the capture register from which the captured data is read Furthermore the TOUTnm CAPnm pin is configured to the CAPn...

Page 189: ...bility of invalid data reading by capturing counter data simultaneously with the counter being counted up down Set the T16BnCCCTLm SCS bit to 1 to set the capture circuit to synchronous capture mode This mode captures counter data by synchronizing the capture signal with the counter clock On the other hand asynchronous capture mode can capture counter data by detecting a trigger pulse even if the ...

Page 190: ... 15 4 4 1 TOUT Output Circuits Circuits 0 and 1 Each timer channel includes two four or six TOUT output circuits and their signal generation and output can be controlled individually TOUT generation mode The T16BnCCCTLm TOUTMD 2 0 bits are used to set how the TOUT signal waveform is changed by the MATCH and MAX ZERO signals Furthermore when the T16BnCCCTLm TOUTMT bit is set to 1 the TOUT circuit u...

Page 191: ...et set mode 0x7 MAX value 5 Compare buffer value 2 T16BnCCCTLm TOUTINV bit 0 1 Repeat up count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value 4 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 RUN PRESET Count clock T16BnTC TC 15 0 MATCH signal ZERO signal T16BnCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle s...

Page 192: ...T output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16BnCCCTLm TOUTINV bit 0 3 Repeat up down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value 1 0 2 3 4 5 4 3 2 1 0 1 2 3 4 5 Figure 15 4 4 2 TOUT Output Waveform T16BnCCCTLm TOUTMT bit 0 ...

Page 193: ... output Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 1 Repeat up count mode indicates the T16Bn...

Page 194: ... TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 2 Repeat down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting v...

Page 195: ...gle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 1 0 2 3 4 5 4 3 2 1 0 1 2 3 4 5 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 3 Repeat up down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value Figur...

Page 196: ...g 1 Counter zero T16BnINTF CNTZEROIF When the counter reaches 0x0000 Writing 1 T16B provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter 15 6 Co...

Page 197: ...upported in this IC cannot be selected as the clock source T16B Ch n Counter Control Register Register name Bit Bit name Initial Reset R W Remarks T16BnCTL 15 9 0x00 R 8 MAXBSY 0 H0 R 7 6 0x0 R 5 4 CNTMD 1 0 0x0 H0 R W 3 ONEST 0 H0 R W 2 RUN 0 H0 R W 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W Bits 15 9 Reserved Bit 8 MAXBSY This bit indicates whether data can be written to the T16BnMC register or not 1 R ...

Page 198: ...value which has been set to the T16BnMC register is preset to the counter However the T16BnCTL MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance Bit 0 MODEN This bit enables the T16B Ch n operations 1 R W Enable Start supplying operating clock 0 R W Disable Stop supplying operating clock Note The counter reset operation using the T16BnCTL PRESET bit and the count...

Page 199: ...se bits indicate the signal level currently input to the CAPnm pin 1 R Input signal High level 0 R Input signal Low level The following shows the correspondence between the bit and the CAPnm pin T16BnCS CAPI5 bit CAPn5 pin T16BnCS CAPI4 bit CAPn4 pin T16BnCS CAPI3 bit CAPn3 pin T16BnCS CAPI2 bit CAPn2 pin T16BnCS CAPI1 bit CAPn1 pin T16BnCS CAPI0 bit CAPn0 pin Note The configuration of the T16BnCS...

Page 200: ... R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt T16BnINTF CAPOW5IF bit Capture 5 overwrite interrupt T16BnINTF CMPCAP5IF bit Compare capture 5 interrupt T16BnINTF CAPOW4IF bit Capture 4 overwrite interrupt T16BnINTF CMPCAP4IF bit Compare capture 4 interrupt T16BnINTF CAPOW3IF bit Capture 3 overwrite interrupt T16...

Page 201: ... the bit and interrupt T16BnINTE CAPOW5IE bit Capture 5 overwrite interrupt T16BnINTE CMPCAP5IE bit Compare capture 5 interrupt T16BnINTE CAPOW4IE bit Capture 4 overwrite interrupt T16BnINTE CMPCAP4IE bit Compare capture 4 interrupt T16BnINTE CAPOW3IE bit Capture 3 overwrite interrupt T16BnINTE CMPCAP3IE bit Compare capture 3 interrupt T16BnINTE CAPOW2IE bit Capture 2 overwrite interrupt T16BnINTE...

Page 202: ...to the comparison value set previously Also the counter is reset to 0x0000 simultaneously Down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to the MAX value simultaneously Up down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to 0x0000 simultaneously 0x3 Up mode When the counter reverts t...

Page 203: ...ator mode and is ineffective in capture mode Bits 4 2 TOUTMD 2 0 These bits configure how the TOUTnm signal waveform is changed by the comparator MATCH and counter MAX ZERO signals The T16BnCCCTLm TOUTMD 2 0 bits are control bits for comparator mode and are ineffective in capture mode Table 15 6 5 TOUT Generation Mode T16BnCCCTLm TOUTMD 2 0 bits TOUT generation mode and operations T16BnCCCTLm TOUT...

Page 204: ...Tnm The signal is inverted by the MATCHm signal and it be comes inactive by the MATCHm 1 signal TOUTnm 1 The signal is inverted by the MATCHm 1 signal and it be comes inactive by the MATCHm signal 0x1 Set mode 0 All count modes TOUTnm The signal becomes active by the MATCH signal 1 All count modes TOUTnm The signal becomes active by the MATCHm or MATCHm 1 signal TOUTnm 1 The signal becomes active ...

Page 205: ... output duration Can be set within the range of 15 6 ms to 250 ms 16 types 3 Melody mode for playing single note melody Pitch Can be set within the range of 128 Hz to 16 384 Hz Scale 3 octave from C3 to C6 with reference to A4 443 Hz Duration Can be set within the range of half note rest to thirty second note rest 7 types Tempo Can be set within the range of 30 to 480 16 types Other Tie and slur c...

Page 206: ...ve Mode The drive mode of the BZOUT and BZOUT pins can be set to one of the two types shown below using the SND SEL SINV bit Direct drive mode SNDSEL SINV bit 0 This mode drives both the BZOUT and BZOUT pins to low while the buzzer signal output is off to prevent the piezoelectric buzzer from applying unnecessary bias Normal drive mode SNDSEL SINV bit 1 In this mode the BZOUT pin always outputs th...

Page 207: ...CLK_SNDA supply during DEBUG mode should be controlled using the SNDCLK DBRUN bit The CLK_SNDA supply to SNDA is suspended when the CPU enters DEBUG mode if the SNDCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_SNDA supply resumes Although SNDA stops operating when the CLK_SNDA supply is suspended the output pin and registers retain the status before DEBUG mode was entered If the SND...

Page 208: ...put and sets the SNDINTF EDIF bit sound output comple tion interrupt flag to 1 The SNDINTF SBSY bit is cleared to 0 Figure 16 4 2 1 shows a buzzer output timing chart in normal buzzer mode CLK_SNDA Sound buffer SNDDAT register Sound register SNDCTL SSTP SNDINTF SBSY SNDINTF EMIF SNDINTF EDIF BZOUT pin BZOUT pin Writing to the SNDDAT register Writing to the SNDDAT register Software operation When S...

Page 209: ...35 606 8 0x25 862 3 0x15 1 489 5 0x05 5 461 3 0x34 618 3 0x24 885 6 0x14 1 560 4 0x04 6 553 6 0x33 630 2 0x23 910 2 0x13 1 638 4 0x03 8 192 0 0x32 642 5 0x22 936 2 0x12 1 724 6 0x02 10 922 7 0x31 655 4 0x21 963 8 0x11 1 820 4 0x01 16 384 0 0x30 668 7 0x20 993 0 0x10 1 927 5 0x00 Cannot be set Table 16 4 2 2 Buzzer Duty Ratio Setting Examples when fCLK_SNDA 32 768 Hz SNDDAT SLEN 5 0 bits Duty ratio...

Page 210: ...to Buzzer Output in Normal Buzzer Mode One shot buzzer output start procedure 1 Set the following SNDSEL register bits Set the SNDSEL MOSEL 1 0 bits to 0x1 Set one shot buzzer mode SNDSEL STIM 3 0 bits Set output duration 2 Write data to the following sound buffer SNDDAT register bits Start buzzer output SNDDAT SLEN 5 0 bits Set buzzer output signal duty ratio SNDDAT SFRQ 7 0 bits Set buzzer outpu...

Page 211: ... Set tempo 2 Write data to the following sound buffer SNDDAT register bits Start sound output SNDDAT MDTI bit Set tie slur SNDDAT MDRS bit Set note rest SNDDAT SLEN 5 0 bits Set duration SNDDAT SFRQ 7 0 bits Set scale 3 Check to see if the SNDINTF EMIF bit is set to 1 an interrupt can be used 4 Repeat Steps 2 and 3 until the end of the melody Melody output operations When data is written to the so...

Page 212: ... 768 Hz SNDDAT SLEN 5 0 bits SNDDAT MDRS bit 0 Note 1 Rest 0x0f Half note Half rest 0x0b Dotted quarter note Dotted quarter rest 0x07 Quarter note Quarter rest 0x05 Dotted eighth note Dotted eighth rest 0x03 Eighth note Eighth rest 0x01 Sixteenth note Sixteenth rest 0x00 Thirty second note Thirty second rest Other Setting prohibited Tie slur specification A tie or slur takes effect by setting the ...

Page 213: ... sound buffer SNDDAT regis ter is transferred to the sound register or 1 is written to the SNDCTL SSTP bit Writing to the SNDDAT register Sound output completion SNDINTF EDIF When a sound output has completed Writing 1 or writing to the SNDDAT register SNDA provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the inter rupt controller only when the in...

Page 214: ...ter settings can be altered only when the SNDCTL MODEN bit 0 SNDA Select Register Register name Bit Bit name Initial Reset R W Remarks SNDSEL 15 12 0x0 R 11 8 STIM 3 0 0x0 H0 R W 7 3 0x00 R 2 SINV 0 H0 R W 1 0 MOSEL 1 0 0x0 H0 R W Bits 15 12 Reserved Bits 11 8 STIM 3 0 These bits select a tempo when melody mode is selected or a one shot buzzer output duration when one shot buzzer mode is selected ...

Page 215: ...al buzzer mode After 1 is written this bit is cleared to 0 when the sound output has completed Also in one shot buzzer mode melody mode writing 1 to this bit can forcibly terminate the sound output Bits 7 1 Reserved Bit 0 MODEN This bit enables the SNDA operations 1 R W Enable SNDA operations The operating clock is supplied 0 R W Disable SNDA operations The operating clock is stopped SNDA Data Reg...

Page 216: ...bits SNDDAT SFRQ 5 0 bits are effective within the SNDDAT SFRQ 7 0 bits Always set the SNDDAT SFRQ 7 6 bits to 0x0 The SNDDAT register allows 16 bit data writing only Data writings in 8 bit size will be ig nored SNDA Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks SNDINTF 15 9 0x00 R 8 SBSY 0 H0 R 7 2 0x00 R 1 EMIF 1 H0 R Cleared by writing to the SNDDAT register 0 EDI...

Page 217: ...al Reset R W Remarks SNDINTE 15 8 0x00 R 7 2 0x00 R 1 EMIE 0 H0 R W 0 EDIE 0 H0 R W Bits 15 2 Reserved Bit 1 EMIE Bit 0 EDIE These bits enable SNDA interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt SNDINTE EMIE bit Sound buffer empty interrupt SNDINTE EDIE bit Sound output completion interrupt ...

Page 218: ...the REMC3 configuration Table 17 1 1 REMC3 Channel Configuration of S1C17M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 pin package Number of channels 1 transmitter channel REMC3 Carrier signal generator Data signal generator DBCNT 15 0 CLKSRC 1 0 CLKDIV 3 0 Clock generator DBRUN MODEN DBLENBSY CLK_REMC3 REMO Interrupt control circuit CRPER 7 0 CRDTY 7 0 CARR...

Page 219: ...3 during SLEEP mode the REMC3 operating clock CLK_REMC3 must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_REMC3 clock source If the CLGOSC xxxxSLPC bit for the CLK_REMC3 clock source is 1 the CLK_REMC3 clock source is deacti vated during SLEEP mode and REMC3 stops with the register settings maintained at those before entering SLEEP mode After the...

Page 220: ...ister bits Set the REMDBCTL PRESET bit to 1 Reset internal counters Set the REMDBCTL PRUN bit to 1 Start counting Continuous data transmission control The following shows a procedure to send data continuously after starting data transmission after Step 3 above 1 Set the duty and cycle for the subsequent data to the REMAPLEN APLEN 15 0 and REMDBLEN DBLEN 15 0 bits respectively before a compare DB i...

Page 221: ...frequency and duty ratio can be calculated by the equations shown below fCLK_REMC3 CRDTY 1 Carrier frequency Duty ratio Eq 17 1 CRPER 1 CRPER 1 Where fCLK_REMC3 CLK_REMC3 frequency Hz CRPER REMCARR CRPER 7 0 bit setting value 1 255 CRDTY REMCARR CRDTY 7 0 bit setting value 0 254 REMCARR CRDTY 7 0 bits REMCARR CRPER 7 0 bits The 8 bit counter for carrier generation is reset by the REMDBCTL PRESET b...

Page 222: ...65 534 REMAPLEN APLEN 15 0 bits REMDBLEN DBLEN 15 0 bits The 16 bit counter for data signal generation is reset by the REMDBCTL PRESET bit and is started stopped by the REMDBCTL PRUN bit When the counter value is matched with the REMAPLEN APLEN 15 0 bits compare AP the data signal waveform is inverted When the counter value is matched with the REMDBLEN DBLEN 15 0 bits compare DB the data signal wa...

Page 223: ...EMDBLEN buffer and the 16 bit counter value is compared with the compare buffers The comparison values are loaded into the compare buffers when the 16 bit counter is matched with the REM DBLEN buffer when the count for the data length has completed Therefore the next transmit data can be set during the current data transmission When the compare buffers are enabled the buffer status flags REMINTF A...

Page 224: ...N APLEN 15 0 REMDBLEN DBLEN 15 0 REMCARR CRPER 7 0 REMCARR CRDTY 7 0 Figure 17 6 2 Example of Generated Drive Waveform The REMO and CLPLS signals are output from the respective pins while the REMDBCTL PRUN bit 1 The dif ference between the setting values of the REMDBLEN DBLEN 15 0 bits and REMAPLEN APLEN 15 0 bits becomes the CLPLS pulse width high period 17 7 Control Registers REMC3 Clock Control...

Page 225: ...nly when the REMDBCTL MODEN bit 0 REMC3 Data Bit Counter Control Register Register name Bit Bit name Initial Reset R W Remarks REMDBCTL 15 10 0x00 R 9 PRESET 0 H0 S0 R W Cleared by writing 1 to the REMDBCTL REMCRST bit 8 PRUN 0 H0 S0 R W 7 5 0x0 R 4 REMOINV 0 H0 R W 3 BUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W Bits 15 10 Reserved Bit 9 PRESET This bit resets the internal coun...

Page 226: ...One shot mode 0 R W Repeat mode For more information refer to REMO Output Waveform Data signal Bit 1 REMCRST This bit issues software reset to the REMC3 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R Software reset has finished During normal operation Setting this bit resets the REMC3 internal counters and interrupt flags This bit is automatically cleared after the re...

Page 227: ...00 and ends when the counter exceeds the REMDBLEN DBLEN 15 0 bit setting value See Figure 17 4 3 3 Before this register can be rewritten the REMDBCTL MODEN bit must be set to 1 REMC3 Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks REMINTF 15 11 0x00 R 10 DBCNTRUN 0 H0 S0 R Cleared by writing 1 to the REMDBCTL REMCRST bit 9 DBLENBSY 0 H0 R Effective when the ...

Page 228: ...errupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt REMINTE DBIE bit Compare DB interrupt REMINTE APIE bit Compare AP interrupt REMC3 Carrier Waveform Register Register name Bit Bit name Initial Reset R W Remarks REMCARR 15 8 CRDTY 7 0 0x00 H0 R W 7 0 CRPER 7 0 0x00 H0 R W Bits 15 8 CRDTY 7 0 These bits set the high level pe...

Page 229: ...INVEN 0 H0 R W 7 1 0x00 R 0 CARREN 0 H0 R W Bits 15 9 Reserved Bit 8 OUTINVEN This bit inverts the REMO output polarity 1 R W Inverted 0 R W Non inverted For more information see Figure 17 4 3 1 Bits 7 1 Reserved Bit 0 CARREN This bit enables carrier modulation 1 R W Enable carrier modulation 0 R W Disable carrier modulation output data signal only Note When carrier modulation is disabled the REMD...

Page 230: ... sensor and a few passive elements resistor and capacitor Allows measurement counting by inputting external clocks Provides an output and continuous oscillation function for monitoring the oscillation frequency Can generate reference oscillation completion sensor A and B oscillation completion measurement counter overflow error and time base counter overflow error interrupts Figure 18 1 1 shows th...

Page 231: ...o the port before activating the RFC For more information refer to the I O Ports chapter Note The RFINn pin goes to VSS level when the port is switched Be aware that large current may flow if the pin is biased by an external circuit 18 2 2 External Connections The figures below show connection examples between the RFC and external sensors For the oscillation mode and external clock input mode refe...

Page 232: ...tion 18 3 2 Clock Supply in SLEEP Mode When using RFC during SLEEP mode the RFC operating clock TCCLK must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the TCCLK clock source 18 3 3 Clock Supply in DEBUG Mode The TCCLK supply during DEBUG mode should be controlled using the RFCnCLK DBRUN bit The TCCLK supply to the RFC is suspended when the CPU enters DE...

Page 233: ... Schmitt input threshold voltage VT and Low level Schmitt input thresh old voltage VT in the Electrical Characteristics chapter This function is enabled by setting the RFCnCTL EVTEN bit to 1 The measurement procedure is the same as when the internal oscillation circuit is used 18 4 3 RFC Counters The RFC incorporates two counters shown below Measurement counter MC The measurement counter is a 24 b...

Page 234: ...nINTF EREFIF bit and then go to Step 6 ii If the RFCnINTF OVTCIF bit 1 time base counter overflow error clear the RFCnINTF OVTCIF bit and terminate measurement as an error or retry after altering the measurement counter initial value 6 Clear the RFCnINTF ESENAIF RFCnINTF ESENBIF and RFCnINTF OVMCIF bits by writing 1 7 Set the RFCnTRG SSENA bit sensor A or the RFCnTRG SSENB bit sensor B correspondi...

Page 235: ... at this point Max count value 0xffffff Min count value 0x000000 Max count value 0xffffff Min count value 0x000000 Overflow normal termination EREFIF 1 SREF 0 Overflow error termination OVMCIF 1 SSENx 0 Count value m1 Count value m2 Varies depending on the environment Calculate the sensor detecting value from the measurement counter value m1 and m2 Overflow error termination OVTCIF 1 SREF 0 Underf...

Page 236: ... VDD VSS RFCnCTL CONEN Writing 1 Writing 0 Figure 18 4 5 1 CR Oscillation Clock RFCLK Waveform 18 5 Interrupts The RFC has a function to generate the interrupts shown in Table 18 5 1 Table 18 5 1 RFC Interrupt Function Interrupt Interrupt flag Set condition Clear condition Reference oscillation completion RFCnINTF EREFIF When reference oscillation has been completed normally due to a measurement c...

Page 237: ...ck source of the RFC Table 18 6 1 Clock Source and Division Ratio Settings RFCnCLK CLKDIV 1 0 bits RFCnCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4 1 4 0x1 1 2 1 2 0x0 1 1 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source Note The RFCnCLK register settings can be altered only when the RF...

Page 238: ...istive sensor measurements 0x0 DC oscillation mode for resistive sensor measurements Bits 3 1 Reserved Bit 0 MODEN This bit enables the RFC operations 1 R W Enable RFC operations The operating clock is supplied 0 R W Disable RFC operations The operating clock is stopped Note If the RFCnCTL MODEN bit is altered from 1 to 0 during R F conversion the counter value being converted cannot be guaranteed...

Page 239: ...H0 R W Or Register name Bit Bit name Initial Reset R W Remarks RFCnMCL RFCnMCH 31 24 0x00 R 23 0 MC 23 0 0x000000 H0 R W Bits 31 24 Reserved Bits 23 0 MC 23 0 Measurement counter data can be read and written through these bits Note The measurement counter must be set from the low order value RFCnMCL MC 15 0 bits first when data is set using a 16 bit access instruction The counter may not be set to...

Page 240: ...or interrupt RFCnINTF ESENBIF bit Sensor B oscillation completion interrupt RFCnINTF ESENAIF bit Sensor A oscillation completion interrupt RFCnINTF EREFIF bit Reference oscillation completion interrupt RFC Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RFCnINTE 15 8 0x00 R 7 5 0x0 R 4 OVTCIE 0 H0 R W 3 OVMCIE 0 H0 R W 2 ESENBIE 0 H0 R W 1 ESENAIE 0 H0 R W 0 ERE...

Page 241: ...M20 M21 M22 M23 M24 M25 Item S1C17M20 M23 S1C17M21 M24 S1C17M22 M25 24 pin package 32 pin package Number of channels 1 channel Ch 0 Number of analog signal inputs per channel Ch 0 4 inputs ADIN00 ADIN03 Ch 0 6 inputs ADIN00 ADIN05 Ch 0 8 inputs ADIN00 ADIN07 16 bit timer used as conversion clock and trigger sources Ch 0 16 bit timer Ch 3 ADC12A Ch n Trigger select circuit Successive approximation ...

Page 242: ...nm DC DC converter Sensor 3 3 V Figure 19 2 2 1 Connections between ADC12A and External Devices 19 3 Clock Settings 19 3 1 ADC12A Operating Clock The 16 bit timer Ch k operating clock CLK_T16_k is also used as the ADC12A operating clock For more informa tion on the CLK_T16_k settings and clock supply in SLEEP and DEBUG modes refer to Clock Settings in the 16 bit Timers chapter Note When the CLK_T1...

Page 243: ...C12_nTRG CNVMD bit Set conversion mode ADC12_nTRG STMD bit Set data storing mode ADC12_nTRG STAAIN 2 0 bits Set analog input pin to be A D converted first ADC12_nTRG ENDAIN 2 0 bits Set analog input pin to be A D converted last 5 Set the ADC12_nCFG VRANGE 1 0 bits Set operating voltage range according to VDD 6 Set the following bits when using the interrupt Write 1 to the interrupt flags in the AD...

Page 244: ...TF ADmOVIF bit 1 analog input signal m A D conversion result overwrite error inter rupt clear the ADC12_nINTF ADmOVIF bit and terminate as an error or retry A D conversion 3 Read the A D conversion result of the analog input m ADC12_nADmD ADmD 15 0 bits The 12 bit conversion results are located at the low order 12 bits or high order 12 bits within the ADC12_ nADmD ADmD 15 0 bits according to the A...

Page 245: ...L ADSTAT 2 0 A D conversion operations ADC12_nAD2D AD2D 15 0 ADC12_nAD3D AD3D 15 0 ADC12_nAD4D AD4D 15 0 ADC12_nINTF AD2CIF ADC12_nINTF AD3CIF ADC12_nINTF AD4CIF ADINn2 ADINn2 Sampling A D converting Conversion ADINn3 ADINn3 Sampling Conversion ADINn4 ADINn4 Sampling Conversion Cleared Cleared Cleared ADINn2 conversion result 0x2 ADINn2 0x3 ADINn3 0x4 ADINn4 0x5 ADINn5 ADINn3 conversion result ADI...

Page 246: ...nt to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter 19 6 Control Registers ADC12A Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks ADC12_nCTL 15 0 R 14 12 ADSTAT 2 0 0x0 H0 R 11 0 R 10 BSYSTAT 0 H0 R 9 8 0x0 R 7...

Page 247: ...s written Bit 0 MODEN This bit enables the ADC12A operations 1 R W Enable ADC12A operations The operating clock is supplied 0 R W Disable ADC12A operations The operating clock is stopped Note After 0 is written to the ADC12_nCTL MODEN bit the ADC12A executes a terminate processing Before the clock source is deactivated read the ADC12_nCTL MODEN bit to make sure that it is set to 0 ADC12A Ch n Trig...

Page 248: ...W Continuous conversion mode 0 R W One time conversion mode Bits 5 4 CNVTRG 1 0 These bits select a trigger source to start A D conversion Table 19 6 2 Trigger Source Selection ADC12_nTRG CNVTRG 1 0 bits Trigger source 0x3 ADTRGn pin external trigger 0x2 Reserved 0x1 16 bit timer Ch k underflow 0x0 ADC12_nCTL ADST bit software trigger Bit 3 Reserved Bits 2 0 SMPCLK 2 0 These bits set the analog in...

Page 249: ...rrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks ADC12_nINTF 15 AD7OVIF 0 H0 R W Cleared by writing 1 14 AD6OVIF 0 H0 R W 13 AD5OVIF 0 H0 R W 12 AD4OVIF 0 H0 R W 11 AD3OVIF 0 H0 R W 10 AD2OVIF 0 H0 R W 9 AD1OVIF 0 H0 R W 8 AD0OVIF 0 H0 R W 7 AD7CIF 0 H0 R W 6 AD6CIF 0 H0 R W 5 AD5CIF 0 H0 R W 4 AD4CIF 0 H0 R W 3 AD3CIF 0 H0 R W 2 AD2CIF 0 H0 R W 1 AD1CIF 0 H0 R W 0 AD0CIF 0...

Page 250: ... 3 AD3CIE 0 H0 R W 2 AD2CIE 0 H0 R W 1 AD1CIE 0 H0 R W 0 AD0CIE 0 H0 R W Bits 15 8 ADmOVIE Bits 7 0 ADmCIE These bits enable ADC12A interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt ADC12_nINTE ADmOVIE bit Analog input signal m A D conversion result overwrite error interrupt ADC12_nINTE ADmCIE bit Analog input signal m ...

Page 251: ...register 0 Operation result register 1 Mode setting Selector Argument 2 Argument 1 Coprocessor output Flag output Operation result COPRO2 Figure 20 1 1 COPRO2 Configuration 20 2 Operation Mode and Output Mode COPRO2 operates according to the operation mode specified by the application program As listed in Table 20 2 1 COPRO2 supports 11 operations The multiplication division and MAC results are 32...

Page 252: ...nd 1 without computation 0x4 0x7 Reserved 0x4 Unsigned multiplication mode Performs unsigned multiplication 0x5 Signed multiplication mode Performs signed multiplication 0x6 Unsigned MAC mode Performs unsigned MAC operation 0x7 Signed MAC mode Performs signed MAC operation 0x8 Unsigned division mode Performs unsigned division 0x9 Signed division mode Performs signed division 0xa Initialize mode 3 ...

Page 253: ... following shows a procedure to perform a division 1 Set the mode to 0x02 initialize mode 2 2 Set the 32 bit dividend B to the operation result register 0 using a ld cf instruction 3 Set the mode to 0x08 unsigned division 16 low order bits output mode 0 or 0x09 signed division 16 low order bits output mode 0 4 Send the 32 bit divisor C to COPRO2 using a ld ca instruction 5 Read the one half result...

Page 254: ... 0 Quotient psr CVZN 0b0000 The operation result regis ters 0 and 1 keep the op eration results until they are rewritten by other opera tion COPRO2 does not support 0 0 division ext imm9 ld ca rd imm7 res0 31 0 rd imm7 16 res0 31 0 Quotient res1 31 0 Remainder rd res0 15 0 Quotient 0x18 or 0x19 ld ca rd rs res0 31 0 rd rs res0 31 0 Quotient res1 31 0 Remainder rd res0 31 16 Quotient ext imm9 ld ca...

Page 255: ... C 16 bits A 32 bits The following shows a procedure to perform a MAC operation 1 Set the initial value A to the operation result register 0 To clear the operation result registers A 0 Set the mode to 0x00 initialize mode 0 It is not necessary to send 0x00 to COPRO2 with another instruc tion To load a 16 bit value to the operation result register 0 Set the operation mode to 0x01 initialize mode 1 ...

Page 256: ...e set ting value Instruction Operations Flags Remarks 0x06 or 0x07 ld ca rd rs res0 31 0 rd rs res0 31 0 rd res0 15 0 psr CVZN 0b0100 if an overflow has oc curred Otherwise psr CVZN 0b0000 The operation result register 0 keeps the operation result until it is rewritten by other operation Overflow can be de tected only in signed MAC mode it does not occur in unsigned MAC mode ext imm9 ld ca rd imm7...

Page 257: ...ration or when the ld ca or ld cf instruction is executed in an operation mode other than operation result read mode 20 6 Reading Operation Results The ld ca instruction cannot load a 32 bit operation result to a CPU register so a multiplication division or MAC operation returns the one half 16 bits according to the output mode result A 15 0 or A 31 16 and the flag status to the CPU registers Anot...

Page 258: ...rated internally 2 7 5 5 V Flash programming voltage VPP 7 3 7 5 7 7 V OSC1 oscillator oscillation frequency fOSC1 Crystal oscillator 32 768 kHz OSC3 oscillator oscillation frequency fOSC3 Crystal ceramic oscillator 1 21 MHz EXOSC external clock frequency fEXOSC When supplied from an external oscillator 0 016 21 MHz Bypass capacitor between VSS and VDD CPW1 3 3 µF Capacitor between VSS and VD1 CPW...

Page 259: ...C1 5 5 12 µA IRUN3 5 IOSC OFF OSC1 32 768 kHz 1 OSC3 1 MHz ceramic oscillator 3 SYSCLK OSC3 160 320 µA IOSC OFF OSC1 32 768 kHz 1 OSC3 12 MHz internal oscillator 4 SYSCLK OSC3 1 800 2 800 µA 1 OSC1 oscillator CLGOSC1 OSC1SELCR bit 0 CLGOSC1 INV1N 1 0 bits 0x0 CLGOSC1 CGI1 2 0 bits 0x0 CLGOSC1 OSDEN bit 0 CG1 CD1 0 pF Crystal resonator C 002RX manufactured by Seiko Epson Corporation R1 50 kW Max CL...

Page 260: ...100 Ta C I HALT3 µA 20 MHz 16 MHz 12 MHz Current consumption temperature characteristic Current consumption temperature characteristic in RUN mode IOSC operation in RUN mode OSC1 operation IOSC ON OSC1 32 768 kHz OSC3 OFF Typ value IOSC OFF OSC1 32 768 kHz OSC3 OFF Typ value 50 250 200 150 100 50 0 25 0 25 50 75 100 Ta C I RUN1 µA 50 10 8 6 4 2 0 25 0 25 50 75 100 Ta C I RUN2 µA Current consumptio...

Page 261: ... reset request hold time tRRQ 0 01 4 ms POR BOR reset request VDD VSS VRSTOP VRST VRST VRST VRST Indefinite operating limit POR BOR reset request tRRQ X X X REQ REQ tRRQ REQ tRRQ tRST tRST tRST X VRSTOP VRSTOP VRST REQ V RST Note When performing a power on reset again after the power is turned off decrease the VDD voltage to VRSTOP or less Reset hold circuit characteristics Unless otherwise specif...

Page 262: ...SC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x4 19 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x5 21 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x6 23 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x7 24 pF Crystal oscillator internal drain capacitance CDI1C CLGOSC1 OSC1SELCR bit 0 6 pF Crystal oscillator oscillator circuit current oscillation inverter drivability ratio 1 IOSC1C CLGOSC1 OS...

Page 263: ...FQ 1 0 bits 0x0 10 to 40 C 11 88 12 12 12 MHz 10 to 60 C 11 76 12 12 24 MHz 40 to 85 C 11 70 12 12 30 MHz Crystal ceramic oscillator oscillation start time 1 tsta3C CLGOSC3 OSC3MD bit 1 CLGOSC3 OSC3INV 1 0 bits 0x0 10 ms Crystal ceramic oscillator internal gate capacitance CGI3C CLGOSC3 OSC3MD bit 1 8 pF Crystal ceramic oscillator internal drain capacitance CDI3C CLGOSC3 OSC3MD bit 1 8 pF Crystal ...

Page 264: ... ROM data programmed 21 7 Input Output Port PPORT Characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit High level Schmitt input threshold voltage VT P00 07 P10 17 P20 27 P30 37 P40 42 PD0 D1 PD3 D4 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT P00 07 P10 17 P20 27 P30 37 P40 42 PD0 D1 PD3 D4 0 2 VDD 0 5 VDD V Schm...

Page 265: ...bits 0x0b 551 603 655 kW SVDCTL SVDC 4 0 bits 0x0c 571 626 682 kW SVDCTL SVDC 4 0 bits 0x0d 593 649 705 kW SVDCTL SVDC 4 0 bits 0x0e 616 672 727 kW SVDCTL SVDC 4 0 bits 0x0f 635 695 754 kW SVDCTL SVDC 4 0 bits 0x10 658 718 777 kW SVDCTL SVDC 4 0 bits 0x11 679 741 804 kW SVDCTL SVDC 4 0 bits 0x12 698 765 833 kW SVDCTL SVDC 4 0 bits 0x13 739 812 885 kW SVDCTL SVDC 4 0 bits 0x14 761 834 908 kW SVDCTL...

Page 266: ...4 0 bits 0x09 2 34 2 4 2 46 V SVDCTL SVDC 4 0 bits 0x0a 2 44 2 5 2 56 V SVDCTL SVDC 4 0 bits 0x0b 2 54 2 6 2 67 V SVDCTL SVDC 4 0 bits 0x0c 2 63 2 7 2 77 V SVDCTL SVDC 4 0 bits 0x0d 2 73 2 8 2 87 V SVDCTL SVDC 4 0 bits 0x0e 2 83 2 9 2 97 V SVDCTL SVDC 4 0 bits 0x0f 2 93 3 0 3 08 V SVDCTL SVDC 4 0 bits 0x10 3 02 3 1 3 18 V SVDCTL SVDC 4 0 bits 0x11 3 12 3 2 3 28 V SVDCTL SVDC 4 0 bits 0x12 3 22 3 3...

Page 267: ...mode 150 921 600 bps UBRT2 IrDA mode 150 115 200 bps 21 10 Synchronous Serial Interface SPIA Characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition VDD Min Typ Max Unit SPICLKn cycle time tSCYC 4 5 to 5 5 V 250 ns 1 8 to 4 5 V 500 ns SPICLKn High pulse width tSCKH 4 5 to 5 5 V 100 ns 1 8 to 4 5 V 200 ns SPICLKn Low pulse width tSCKL 4 5 to 5 5 V 100...

Page 268: ...x Min Typ Max SCLn frequency fSCL 0 100 0 400 kHz Hold time repeated START condition tHD STA 4 0 0 6 µs SCLn Low pulse width tLOW 4 7 1 3 µs SCLn High pulse width tHIGH 4 0 0 6 µs Repeated START condition setup time tSU STA 4 7 0 6 µs Data hold time tHD DAT 0 0 µs Data setup time tSU DAT 250 100 ns SDAn SCLn rise time tr 1 000 300 ns SDAn SCLn fall time tf 300 300 ns STOP condition setup time tSU ...

Page 269: ... 21 MHz High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV R F converter operating current IRFC CREF 1 000 pF RREF RSEN 100 kW Ta 25 C 3 6 to 5 5 V 130 200 µA 1 8 to 3 6 V 60 85 µA 1 In this characteristic unevenness between production lots and variations in measurement board res...

Page 270: ...Max Unit VREFAn voltage range VREFA 1 8 VDD V A D conversion clock frequency fCLK_ADC12A 16 2 200 kHz Sampling rate 1 fSMP 100 ksps Integral nonlinearity 2 INL VDD VREFAn 3 3 LSB Differential nonlinearity DNL VDD VREFAn 3 3 LSB Zero scale error ZSE VDD VREFAn 3 5 LSB Full scale error FSE VDD VREFAn 3 5 LSB Analog input resistance RADIN 4 kW Analog input capacitance CADIN 30 pF A D converter circui...

Page 271: ...HNICAL MANUAL Rev 1 0 A D converter current consumption power supply voltage characteristic VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C Typ value 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 1 000 900 800 700 600 500 400 300 200 100 0 VDD VREFA V I ADC µA 0x3 0x2 0x1 ADC12_nCFG VRANGE 1 0 bits ...

Page 272: ...2 M23 M24 M25 The potential of the substrate back of the chip is VSS CD1 CG1 X tal1 CD3 CG3 X tal3 Ceramic RTMP2 RTMP1 RREF CREF BZ VDD CVPP REMO VDD IR transmitter module A D conversion inputs CVREFA 1 8 5 5 V 2 4 5 5 V 1 or 2 7 5 5 V 2 4 5 3 1 For Flash programming when VPP is supplied externally 2 For Flash programming when VPP is generated internally 3 When the OSC1 crystal oscillator is used ...

Page 273: ...3 OSC3 gate capacitor Ceramic capacitor CD3 OSC3 drain capacitor Ceramic capacitor CPW1 Bypass capacitor between VSS and VDD Ceramic capacitor or electrolytic capacitor CPW2 Capacitor between VSS and VD1 Ceramic capacitor BZ Piezoelectric buzzer PS1240P02 manufactured by TDK Corporation RDBG DSIO pull up resistor Thick film chip resistor RREF RFC reference resistor Thick film chip resistor RTMP1 2...

Page 274: ... Unit mm 3 9min 4 1max 0 35min 0 45max 6 13 1 18 7 24 12 19 INDEX EXPOSED DIE PAD 2 4min 2 6max 3 9 min 4 1 max 0 min 1 max Top View Bottom View 0 2 min 0 3 max 0 5 C0 3 2 4 min 2 6 max Figure 23 1 SQFN4 24 Package Dimensions The potential of the EXPOSED DIE PAD is the same as that of the substrate potential VSS on the back of the IC ...

Page 275: ... mm 4 9min 5 1max 0 35min 0 45max 8 17 1 24 9 32 16 25 INDEX EXPOSED DIE PAD 4 9 min 5 1 max 0 min 1 max Top View Bottom View 0 2 min 0 3 max 0 5 3 0min 3 2max C0 3 3 0 min 3 2 max Figure 23 2 SQFN5 32 Package Dimensions The potential of the EXPOSED DIE PAD is the same as that of the substrate potential VSS on the back of the IC ...

Page 276: ... 7 9 9 16 INDEX 0 32min 0 42max 8 1 32 25 1 0 1 1 2 max 1 0 5min 0 7max 0 min 10 max 0 09min 0 2max 0 8 Figure 23 3 TQFP12 32pin Package Dimensions TQFP12 48pin package S1C17M20 M21 Unit mm 7 9 25 36 7 9 13 24 INDEX 0 17min 0 27max 12 1 48 37 1 0 1 1 2 max 1 0 3min 0 7max 0 min 10 max 0 09min 0 2max 0 5 Figure 23 1 QFP12 48pin Package Dimensions ...

Page 277: ...16 0x00 H0 R WP 0x4008 MSCPSR MISC PSR Register 15 8 0x00 R 7 5 PSRIL 2 0 0x0 H0 R 4 PSRIE 0 H0 R 3 PSRC 0 H0 R 2 PSRV 0 H0 R 1 PSRZ 0 H0 R 0 PSRN 0 H0 R 0x4020 Power Generator PWG Address Register name Bit Bit name Initial Reset R W Remarks 0x4020 PWGVD1CTL PWG VD1 Regulator Control Register 15 8 0x00 R 7 2 0x00 R 1 0 REGMODE 1 0 0x0 H0 R WP 0x4040 0x4050 Clock Generator CLG Address Register name...

Page 278: ...d 0 H0 R 5 OSC1STPIF 0 H0 R W Cleared by writing 1 4 OSC3TEDIF 0 H0 R W 3 0 R 2 OSC3STAIF 0 H0 R W Cleared by writing 1 1 OSC1STAIF 0 H0 R W 0 IOSCSTAIF 0 H0 R W 0x404e CLGINTE CLG Interrupt Enable Register 15 8 0x00 R 7 0 R 6 reserved 0 H0 R 5 OSC1STPIE 0 H0 R W 4 OSC3TEDIE 0 H0 R W 3 0 R 2 OSC3STAIE 0 H0 R W 1 OSC1STAIE 0 H0 R W 0 IOSCSTAIE 0 H0 R W 0x4050 CLGFOUT CLG FOUT Control Register 15 8 ...

Page 279: ... R W 16 bit PWM timer Ch 1 interrupt ILVT16B_1 7 3 0x00 R 2 0 ILV10 2 0 0x0 H0 R W 16 bit PWM timer Ch 0 interrupt ILVT16B_0 0x408c ITCLV6 ITC Interrupt Level Setup Register 6 15 11 0x00 R 10 8 ILV13 2 0 0x0 H0 R W Sound generator interrupt ILVSNDA_0 7 3 0x00 R 2 0 ILV12 2 0 0x0 H0 R W UART Ch 1 interrupt ILVUART3_1 0x408e ITCLV7 ITC Interrupt Level Setup Register 7 15 8 0x00 R 7 3 0x00 R 2 0 ILV1...

Page 280: ...0d2 Real time Clock RTCA Address Register name Bit Bit name Initial Reset R W Remarks 0x40c0 RTCCTL RTC Control Register 15 RTCTRMBSY 0 H0 R 14 8 RTCTRM 6 0 0x00 H0 W Read as 0x00 7 0 R 6 RTCBSY 0 H0 R 5 RTCHLD 0 H0 R W Cleared by setting the RTCCTL RTCRST bit to 1 4 RTC24H 0 H0 R W 3 0 R 2 RTCADJ 0 H0 R W Cleared by setting the RTCCTL RTCRST bit to 1 1 RTCRST 0 H0 R W 0 RTCRUN 0 H0 R W 0x40c2 RTC...

Page 281: ...5 13 0x0 R 12 RTCMOH 0 H0 R W 11 8 RTCMOL 3 0 0x1 H0 R W 7 6 0x0 R 5 4 RTCDH 1 0 0x0 H0 R W 3 0 RTCDL 3 0 0x1 H0 R W 0x40ce RTCYAR RTC Year Week Register 15 11 0x00 R 10 8 RTCWK 2 0 0x0 H0 R W 7 4 RTCYH 3 0 0x0 H0 R W 3 0 RTCYL 3 0 0x0 H0 R W 0x40d0 RTCINTF RTC Interrupt Flag Register 15 RTCTRMIF 0 H0 R W Cleared by writing 1 14 SW1IF 0 H0 R W 13 SW10IF 0 H0 R W 12 SW100IF 0 H0 R W 11 9 0x0 R 8 AL...

Page 282: ... x R 7 1 0x00 R 0 SVDIF 0 H1 R W Cleared by writing 1 0x4106 SVDINTE SVD3 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0 H0 R W 0x4160 0x416c 16 bit Timer T16 Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x4160 T16_0CLK T16 Ch 0 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x4162 T16_0MOD T16 Ch 0...

Page 283: ...R W 9 P0OUT1 0 H0 R W 8 P0OUT0 0 H0 R W 7 P0IN7 0 H0 R 6 P0IN6 0 H0 R 5 P0IN5 0 H0 R 4 P0IN4 0 H0 R 3 P0IN3 0 H0 R 2 P0IN2 0 H0 R 1 P0IN1 0 H0 R 0 P0IN0 0 H0 R 0x4202 P0IOEN P0 Port Enable Register 15 P0IEN7 0 H0 R W 14 P0IEN6 0 H0 R W 13 P0IEN5 0 H0 R W 12 P0IEN4 0 H0 R W 11 P0IEN3 0 H0 R W 10 P0IEN2 0 H0 R W 9 P0IEN1 0 H0 R W 8 P0IEN0 0 H0 R W 7 P0OEN7 0 H0 R W 6 P0OEN6 0 H0 R W 5 P0OEN5 0 H0 R ...

Page 284: ...GE0 0 H0 R W 7 P0IE7 0 H0 R W 6 P0IE6 0 H0 R W 5 P0IE5 0 H0 R W 4 P0IE4 0 H0 R W 3 P0IE3 0 H0 R W 2 P0IE2 0 H0 R W 1 P0IE1 0 H0 R W 0 P0IE0 0 H0 R W 0x420a P0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 P0CHATEN7 0 H0 R W 6 P0CHATEN6 0 H0 R W 5 P0CHATEN5 0 H0 R W 4 P0CHATEN4 0 H0 R W 3 P0CHATEN3 0 H0 R W 2 P0CHATEN2 0 H0 R W 1 P0CHATEN1 0 H0 R W 0 P0CHATEN0 0 H0 R W 0x420c P0MODS...

Page 285: ... P1IEN5 0 H0 R W 12 P1IEN4 0 H0 R W 11 P1IEN3 0 H0 R W 10 P1IEN2 0 H0 R W 9 P1IEN1 0 H0 R W 8 P1IEN0 0 H0 R W 7 P1OEN7 0 H0 R W 6 P1OEN6 0 H0 R W 5 P1OEN5 0 H0 R W 4 P1OEN4 0 H0 R W 3 P1OEN3 0 H0 R W 2 P1OEN2 0 H0 R W 1 P1OEN1 0 H0 R W 0 P1OEN0 0 H0 R W 0x4214 P1RCTL P1 Port Pull up down Control Register 15 P1PDPU7 0 H0 R W 14 P1PDPU6 0 H0 R W 13 P1PDPU5 0 H0 R W 12 P1PDPU4 0 H0 R W 11 P1PDPU3 0 H...

Page 286: ... H0 R W 1 P1IE1 0 H0 R W 0 P1IE0 0 H0 R W 0x421a P1CHATEN P1 Port Chattering Filter Enable Register 15 8 0x00 R 7 P1CHATEN7 0 H0 R W 6 P1CHATEN6 0 H0 R W 5 P1CHATEN5 0 H0 R W 4 P1CHATEN4 0 H0 R W 3 P1CHATEN3 0 H0 R W 2 P1CHATEN2 0 H0 R W 1 P1CHATEN1 0 H0 R W 0 P1CHATEN0 0 H0 R W 0x421c P1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 P1SEL7 0 H0 R W 6 P1SEL6 0 H0 R W 5 P1SEL5 0 H0 R W 4 P1SEL4 ...

Page 287: ...3 P2IEN5 0 H0 R W 12 P2IEN4 0 H0 R W 11 P2IEN3 0 H0 R W 10 P2IEN2 0 H0 R W 9 P2IEN1 0 H0 R W 8 P2IEN0 0 H0 R W 7 P2OEN7 0 H0 R W 6 P2OEN6 0 H0 R W 5 P2OEN5 0 H0 R W 4 P2OEN4 0 H0 R W 3 P2OEN3 0 H0 R W 2 P2OEN2 0 H0 R W 1 P2OEN1 0 H0 R W 0 P2OEN0 0 H0 R W 0x4224 P2RCTL P2 Port Pull up down Control Register 15 P2PDPU7 0 H0 R W 14 P2PDPU6 0 H0 R W 13 P2PDPU5 0 H0 R W 12 P2PDPU4 0 H0 R W 11 P2PDPU3 0 ...

Page 288: ... H0 R W 1 P2IE1 0 H0 R W 0 P2IE0 0 H0 R W 0x422a P2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 P2CHATEN7 0 H0 R W 6 P2CHATEN6 0 H0 R W 5 P2CHATEN5 0 H0 R W 4 P2CHATEN4 0 H0 R W 3 P2CHATEN3 0 H0 R W 2 P2CHATEN2 0 H0 R W 1 P2CHATEN1 0 H0 R W 0 P2CHATEN0 0 H0 R W 0x422c P2MODSEL P2 Port Mode Select Register 15 8 0x00 R 7 P2SEL7 0 H0 R W 6 P2SEL6 0 H0 R W 5 P2SEL5 0 H0 R W 4 P2SEL4 ...

Page 289: ...3 P3IEN5 0 H0 R W 12 P3IEN4 0 H0 R W 11 P3IEN3 0 H0 R W 10 P3IEN2 0 H0 R W 9 P3IEN1 0 H0 R W 8 P3IEN0 0 H0 R W 7 P3OEN7 0 H0 R W 6 P3OEN6 0 H0 R W 5 P3OEN5 0 H0 R W 4 P3OEN4 0 H0 R W 3 P3OEN3 0 H0 R W 2 P3OEN2 0 H0 R W 1 P3OEN1 0 H0 R W 0 P3OEN0 0 H0 R W 0x4234 P3RCTL P3 Port Pull up down Control Register 15 P3PDPU7 0 H0 R W 14 P3PDPU6 0 H0 R W 13 P3PDPU5 0 H0 R W 12 P3PDPU4 0 H0 R W 11 P3PDPU3 0 ...

Page 290: ... H0 R W 1 P3IE1 0 H0 R W 0 P3IE0 0 H0 R W 0x423a P3CHATEN P3 Port Chattering Filter Enable Register 15 8 0x00 R 7 P3CHATEN7 0 H0 R W 6 P3CHATEN6 0 H0 R W 5 P3CHATEN5 0 H0 R W 4 P3CHATEN4 0 H0 R W 3 P3CHATEN3 0 H0 R W 2 P3CHATEN2 0 H0 R W 1 P3CHATEN1 0 H0 R W 0 P3CHATEN0 0 H0 R W 0x423c P3MODSEL P3 Port Mode Select Register 15 8 0x00 R 7 P3SEL7 0 H0 R W 6 P3SEL6 0 H0 R W 5 P3SEL5 0 H0 R W 4 P3SEL4 ...

Page 291: ...H0 R W 9 P4PDPU1 0 H0 R W 8 P4PDPU0 0 H0 R W 7 3 0x00 R 2 P4REN2 0 H0 R W 1 P4REN1 0 H0 R W 0 P4REN0 0 H0 R W 0x4246 P4INTF P4 Port Interrupt Flag Register 15 8 0x00 R 7 3 0x00 R 2 P4IF2 0 H0 R W Cleared by writing 1 1 P4IF1 0 H0 R W 0 P4IF0 0 H0 R W 0x4248 P4INTCTL P4 Port Interrupt Control Register 15 11 0x00 R 10 P4EDGE2 0 H0 R W 9 P4EDGE1 0 H0 R W 8 P4EDGE0 0 H0 R W 7 3 0x00 R 2 P4IE2 0 H0 R W...

Page 292: ...EN3 0 H0 R W 2 PDOEN2 0 H0 R W 1 PDOEN1 0 H0 R W 0 PDOEN0 0 H0 R W 0x42d4 PDRCTL Pd Port Pull up down Control Register 15 13 0x0 R 12 PDPDPU4 0 H0 R W 11 PDPDPU3 0 H0 R W 10 reserved 0 H0 R W 9 PDPDPU1 0 H0 R W 8 PDPDPU0 0 H0 R W 7 5 0 R 4 PDREN4 0 H0 R W 3 PDREN3 0 H0 R W 2 reserved 0 H0 R W 1 PDREN1 0 H0 R W 0 PDREN0 0 H0 R W 0x42dc PDMODSEL Pd Port Mode Select Register 15 8 0x00 R 7 5 0 R 4 PDS...

Page 293: ...x4304 P0UPMUX2 P04 05 Universal Port Multiplexer Setting Register 15 13 P05PPFNC 2 0 0x0 H0 R W 12 11 P05PERICH 1 0 0x0 H0 R W 10 8 P05PERISEL 2 0 0x0 H0 R W 7 5 P04PPFNC 2 0 0x0 H0 R W 4 3 P04PERICH 1 0 0x0 H0 R W 2 0 P04PERISEL 2 0 0x0 H0 R W 0x4306 P0UPMUX3 P06 07 Universal Port Multiplexer Setting Register 15 13 P07PPFNC 2 0 0x0 H0 R W 12 11 P07PERICH 1 0 0x0 H0 R W 10 8 P07PERISEL 2 0 0x0 H0 ...

Page 294: ...0x0 H0 R W 7 5 P24PPFNC 2 0 0x0 H0 R W 4 3 P24PERICH 1 0 0x0 H0 R W 2 0 P24PERISEL 2 0 0x0 H0 R W 0x4316 P2UPMUX3 P26 27 Universal Port Multiplexer Setting Register 15 13 P27PPFNC 2 0 0x0 H0 R W 12 11 P27PERICH 1 0 0x0 H0 R W 10 8 P27PERISEL 2 0 0x0 H0 R W 7 5 P26PPFNC 2 0 0x0 H0 R W 4 3 P26PERICH 1 0 0x0 H0 R W 2 0 P26PERISEL 2 0 0x0 H0 R W 0x4318 P3UPMUX0 P30 31 Universal Port Multiplexer Settin...

Page 295: ...L UART3 Ch 0 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x4388 UA0TXD UART3 Ch 0 Trans mit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x438a UA0RXD UART3 Ch 0 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x438c UA0INTF UART3 Ch 0 Status and Interrupt Flag Register 15 10 0x00 R 9 RBSY 0 H0 S0 R 8 TBSY 0 H0 S0 R 7 0 R 6 TENDIF 0 H0 S0 R W Cleared by ...

Page 296: ...ffff H0 R W 0x43a8 T16_1TC T16 Ch 1 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x43aa T16_1INTF T16 Ch 1 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x43ac T16_1INTE T16 Ch 1 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x43b0 0x43ba Synchronous Serial Interface SPIA Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x...

Page 297: ... I2C Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x43c0 I2C0CLK I2C Ch 0 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x43c2 I2C0MOD I2C Ch 0 Mode Register 15 8 0x00 R 7 3 0x00 R 2 OADR10 0 H0 R W 1 GCEN 0 H0 R W 0 0 R 0x43c4 I2C0BR I2C Ch 0 Baud Rate Register 15 8 0x00 R 7 0 R 6 0 BRT 6 0 0x7f H0 ...

Page 298: ...r 15 8 0x00 R 7 BYTEENDIE 0 H0 R W 6 GCIE 0 H0 R W 5 NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x5000 0x501a 16 bit PWM Timer T16B Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x5000 T16B0CLK T16B Ch 0 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 0 R 2 0 CLKSRC 2 0 0x0 H0 R W 0x500...

Page 299: ...ister 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x5012 T16B0CCR0 T16B Ch 0 Compare Capture 0 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x5018 T16B0CCCTL1 T16B Ch 0 Compare Capture 1 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 1...

Page 300: ...I1 0 H0 R 2 CAPI0 0 H0 R 1 UP_DOWN 1 H0 R 0 BSY 0 H0 R 0x504a T16B1INTF T16B Ch 1 Interrupt Flag Register 15 8 0x00 R 7 6 0x0 R 5 CAPOW1IF 0 H0 R W Cleared by writing 1 4 CMPCAP1IF 0 H0 R W 3 CAPOW0IF 0 H0 R W 2 CMPCAP0IF 0 H0 R W 1 CNTMAXIF 0 H0 R W 0 CNTZEROIF 0 H0 R W 0x504c T16B1INTE T16B Ch 1 Interrupt Enable Register 15 8 0x00 R 7 6 0x0 R 5 CAPOW1IE 0 H0 R W 4 CMPCAP1IE 0 H0 R W 3 CAPOW0IE 0...

Page 301: ...Bit name Initial Reset R W Remarks 0x5200 UA1CLK UART3 Ch 1 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x5202 UA1MOD UART3 Ch 1 Mode Register 15 13 0x0 R 12 PECAR 0 H0 R W 11 CAREN 0 H0 R W 10 BRDIV 0 H0 R W 9 INVRX 0 H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN...

Page 302: ...0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x5210 UA1CAWF UART3 Ch 1 Carrier Waveform Register 15 8 0x00 R 7 0 CRPER 7 0 0x00 H0 R W 0x5260 0x526c 16 bit Timer T16 Ch 2 Address Register name Bit Bit name Initial Reset R W Remarks 0x5260 T16_2CLK T16 Ch 2 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 ...

Page 303: ...Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPI1RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPI1TXD register 0x527a SPI1INTE SPIA Ch 1 Interrupt Enable Register 15 8 0x00 R 7 4 0x0 R 3 OEIE 0 H0 R W 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x5300 0x530a Sound Generator SNDA...

Page 304: ...ng 1 to the REMDBCTL REMCRST bit 8 PRUN 0 H0 S0 R W 7 5 0x0 R 4 REMOINV 0 H0 R W 3 BUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W 0x5324 REMDBCNT REMC3 Data Bit Counter Register 15 0 DBCNT 15 0 0x0000 H0 S0 R Cleared by writing 1 to the REMDBCTL REMCRST bit 0x5326 REMAPLEN REMC3 Data Bit Active Pulse Length Register 15 0 APLEN 15 0 0x0000 H0 R W Writing enabled when REM DBCTL MOD...

Page 305: ... W 5 4 SMODE 1 0 0x0 H0 R W 3 1 0x0 R 0 MODEN 0 H0 R W 0x5444 RFC0TRG RFC Ch 0 Oscillation Trigger Register 15 8 0x00 R 7 3 0x00 R 2 SSENB 0 H0 R W 1 SSENA 0 H0 R W 0 SREF 0 H0 R W 0x5446 RFC0MCL RFC Ch 0 Measure ment Counter Low Register 15 0 MC 15 0 0x0000 H0 R W 0x5448 RFC0MCH RFC Ch 0 Measure ment Counter High Register 15 8 0x00 R 7 0 MC 23 16 0x00 H0 R W 0x544a RFC0TCL RFC Ch 0 Time Base Coun...

Page 306: ...1 Oscillation Trigger Register 15 8 0x00 R 7 3 0x00 R 2 SSENB 0 H0 R W 1 SSENA 0 H0 R W 0 SREF 0 H0 R W 0x5466 RFC1MCL RFC Ch 1 Measure ment Counter Low Register 15 0 MC 15 0 0x0000 H0 R W 0x5468 RFC1MCH RFC Ch 1 Measure ment Counter High Register 15 8 0x00 R 7 0 MC 23 16 0x00 H0 R W 0x546a RFC1TCL RFC Ch 1 Time Base Counter Low Register 15 0 TC 15 0 0x0000 H0 R W 0x546c RFC1TCH RFC Ch 1 Time Base...

Page 307: ...unter Data Register 15 0 TC 15 0 0xffff H0 R 0x548a T16_3INTF T16 Ch 3 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x548c T16_3INTE T16 Ch 3 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x54a0 0x54ba 12 bit A D Converter ADC12A Address Register name Bit Bit name Initial Reset R W Remarks M20 M23 M21 M24 M22 M25 24pin 32pin 0x54a2 ADC12_0C...

Page 308: ...OVIE 0 H0 R W 14 AD6OVIE 0 H0 R W 13 AD5OVIE 0 H0 R W 12 AD4OVIE 0 H0 R W 11 AD3OVIE 0 H0 R W 10 AD2OVIE 0 H0 R W 9 AD1OVIE 0 H0 R W 8 AD0OVIE 0 H0 R W 7 AD7CIE 0 H0 R W 6 AD6CIE 0 H0 R W 5 AD5CIE 0 H0 R W 4 AD4CIE 0 H0 R W 3 AD3CIE 0 H0 R W 2 AD2CIE 0 H0 R W 1 AD1CIE 0 H0 R W 0 AD0CIE 0 H0 R W 0x54ac ADC12_0AD0D ADC12A Ch 0 Result Register 0 15 0 AD0D 15 0 0x0000 H0 R 0x54ae ADC12_0AD1D ADC12A Ch...

Page 309: ...RS S1C17M20 M21 M22 M23 M24 M25 Seiko Epson Corporation AP A 33 TECHNICAL MANUAL Rev 1 0 0xffff90 Debugger DBG Address Register name Bit Bit name Initial Reset R W Remarks 0xffff90 DBRAM Debug RAM Base Register 31 24 0x00 R 23 0 DBRAM 23 0 0x00 07c0 H0 R ...

Page 310: ...REGMODE 1 0 bits to 0x3 economy mode or 0x0 automatic mode before executing the slp instruction CLGOSC IOSCSLPC OSC1SLPC OSC3SLPC EXOSCSLPC bits of the clock generator Setting the CLGOSC IOSCSLPC OSC1SLPC OSC3SLPC or EXOSCSLPC bit of the clock generator to 0 disables the oscillator circuit stop control when the slp instruction is executed To stop the oscillator circuits during SLEEP mode set these...

Page 311: ...current consumption Using lower OSC3 external gate and drain capacitances decreases current consumption Using a resonator with lower CL value decreases current consumption However these configurations may reduce the oscillation margin and increase the frequency error therefore be sure to perform matching evaluation using the actual printed circuit board B 2 Other Power Saving Methods Supply voltag...

Page 312: ...ing for adjacent circuit board layers Layers wired should be adequately shielded as shown to the right Fully ground adjacent layers where possible At minimum shield the area at least 5 mm around the above pins and wiring Even after implementing these precautions avoid configuring digital signal lines in parallel as described in 2 above Avoid crossing even on discrete layers except for lines carryi...

Page 313: ...pening the package If the IC chip must be stored before mounting take measures to ensure light shielding 5 Adequate evaluations are required to assess nonvolatile memory data retention characteristics before prod uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting processes Unused pins 1 I O port P pins Unused pins should be left open The con...

Page 314: ...mounting the product in addition to physical damage The fol lowing factors can give rise to these variations 1 Electromagnetically induced noise from industrial power supplies used in mounting reflow reworking after mounting and individual characteristic evaluation testing processes 2 Electromagnetically induced noise from a solder iron when soldering In particular during soldering take care to en...

Page 315: ... pins within the initialization routine when the debug functions are not used For details of the pin functions and the function switch control see the I O Ports chapter Note Do not perform the function switching shown above when the application is under development as the debug functions must be used The debugging cannot be performed after the pin function is switched The above processing must be ...

Page 316: ...c T16 ch1 long spia_0_handler 0x0c 0x30 SPIA ch0 long i2c_handler 0x0d 0x34 I2C long t16b_0_handler 0x0e 0x38 T16B ch0 long t16b_1_handler 0x0f 0x3c T16B ch1 long uart3_1_handler 0x10 0x40 UART3 ch1 long snda_handler 0x11 0x44 SNDA long remc3_handler 0x12 0x48 REMC3 long int13_handler 0x13 0x4c long rfc_0_handler 0x14 0x50 RFC ch0 long rfc_1_handler 0x15 0x54 RFC ch1 long t16_2_handler 0x16 0x58 T...

Page 317: ...ndler NMI nmi_handler 1 A rodata section is declared to locate the vector table in the vector section 2 Interrupt handler routine addresses are defined as vectors intXX_handler can be used for software interrupts 3 The program code is written in the text section 4 Sets the stack pointer 5 Sets the number of Flash memory read cycles See the Memory and Bus chapter ...

Page 318: ...REVISION HISTORY Revision History Code No Page Contents 413557000 All New establishment ...

Page 319: ...4677 SHENZHEN BRANCH Room 804 805 8 Floor Tower 2 Ali Center No 3331 Keyuan South RD Shenzhen bay Nanshan District Shenzhen 518054 CHINA Phone 86 10 3299 0588 Fax 86 10 3299 0560 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 65 65...

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