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17 12-BIT A/D CONVERTER (ADC12A)

S1C17M12/M13 TECHNICAL MANUAL

Seiko Epson Corporation

17-9

(Rev. 1.2)

Table 17.6.4 A/D Converter Operating Voltage Range Setting

ADC12_nCFG.VRANGE[1:0] bits

A/D converter operating voltage range

0x3

1.8 to 5.5 V

0x2

3.6 to 5.5 V

0x1

4.8 to 5.5 V

0x0

Conversion disabled

Notes: • A/D conversion will not be performed if the ADC12_nCFG.VRANGE[1:0] bits = 0x0. Set

these bits to a value other than 0x0 to perform A/D conversion.

• Be aware that ADC circuit current I

ADC

flows if the ADC12_nCFG.VRANGE[1:0] bits are set

to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1.

ADC12A Ch.

Interrupt Flag Register

Register name

Bit

Bit name

Initial

Reset

R/W

Remarks

ADC12_nINTF

15 AD7OVIF

R/W Cleared by writing 1.

14 AD6OVIF

R/W

13 AD5OVIF

R/W

12 AD4OVIF

R/W

11 AD3OVIF

R/W

10 AD2OVIF

R/W

AD1OVIF

R/W

AD0OVIF

R/W

AD7CIF

R/W

AD6CIF

R/W

AD5CIF

R/W

AD4CIF

R/W

AD3CIF

R/W

AD2CIF

R/W

AD1CIF

R/W

AD0CIF

R/W

Bits 15–8 AD

OVIF

Bits 7–0

CIF

These bits indicate the ADC12A interrupt cause occurrence status.

1 (R):

Cause of interrupt occurred

0 (R):

No cause of interrupt occurred

1 (W):

Clear flag

0 (W):

Ineffective

The following shows the correspondence between the bit and interrupt:

ADC12_

INTF.AD

OVIF bit: Analog input signal

A/D conversion result overwrite error interrupt

ADC12_

INTF.AD

CIF bit: Analog input signal

A/D conversion completion interrupt

Summary of Contents for S1C17M12

Page 1: ...Rev 1 2 CMOS 16 BIT SINGLE CHIP MICROCONTROLLER S1C17M12 M13 Technical Manual ...

Page 2: ...n does not guarantee that the information and the programs are always accurate and complete Epson assumes no responsibility for any damages which you incur due to misinformation in this document and the programs 6 No dismantling analysis reverse engineering modification alteration adaptation reproduction etc of Epson products is allowed 7 Epson products have been designed developed and manufacture...

Page 3: ...H0 H1 or S0 For more information on the reset groups refer to Initialization Conditions Reset Groups in the Power Supply Reset and Clocks chapter R W R Read only bit W Write only bit WP Write only bit with a write protection using the MSCPROT PROT 15 0 bits R W Read write bit R WP Read write bit with a write protection using the MSCPROT PROT 15 0 bits Control bit read write values This manual desc...

Page 4: ...w 2 4 2 3 2 Input Output Pins 2 5 2 3 3 Clock Sources 2 5 2 3 4 Operations 2 6 2 4 Operating Mode 2 9 2 4 1 Initial Boot Sequence 2 9 2 4 2 Transition between Operating Modes 2 10 2 5 Interrupts 2 11 2 6 Control Registers 2 11 PWG VD1 Regulator Control Register 2 11 CLG System Clock Control Register 2 11 CLG Oscillation Control Register 2 13 CLG OSC3 Control Register 2 13 CLG Interrupt Flag Regist...

Page 5: ...3 5 4 1 Peripheral Circuit Interrupt Control 5 3 5 4 2 ITC Interrupt Request Processing 5 3 5 4 3 Conditions to Accept Interrupt Requests by the CPU 5 4 5 5 NMI 5 4 5 6 Software Interrupts 5 4 5 7 Interrupt Processing by the CPU 5 4 5 8 Control Registers 5 5 MISC Vector Table Address Low Register 5 5 MISC Vector Table Address High Register 5 5 ITC Interrupt Level Setup Register x 5 5 6 I O Ports P...

Page 6: ...1 7 1 Overview 7 1 7 2 Peripheral Circuit I O Function Assignment 7 1 7 3 Control Registers 7 2 Pxy xz Universal Port Multiplexer Setting Register 7 2 8 Watchdog Timer WDT2 8 1 8 1 Overview 8 1 8 2 Clock Settings 8 1 8 2 1 WDT2 Operating Clock 8 1 8 2 2 Clock Supply in DEBUG Mode 8 1 8 3 Operations 8 2 8 3 1 WDT2 Control 8 2 8 3 2 Operations in HALT and SLEEP Modes 8 3 8 4 Control Registers 8 3 WD...

Page 7: ...n Control Register 10 5 T16 Ch n Reload Data Register 10 6 T16 Ch n Counter Data Register 10 6 T16 Ch n Interrupt Flag Register 10 6 T16 Ch n Interrupt Enable Register 10 7 11 UART UART3 11 1 11 1 Overview 11 1 11 2 Input Output Pins and External Connections 11 2 11 2 1 List of Input Output Pins 11 2 11 2 2 External Connections 11 2 11 2 3 Input Pin Pull Up Function 11 2 11 2 4 Output Pin Open Dra...

Page 8: ... 12 5 12 5 Operations 12 5 12 5 1 Initialization 12 5 12 5 2 Data Transmission in Master Mode 12 5 12 5 3 Data Reception in Master Mode 12 7 12 5 4 Terminating Data Transfer in Master Mode 12 8 12 5 5 Data Transfer in Slave Mode 12 8 12 5 6 Terminating Data Transfer in Slave Mode 12 10 12 6 Interrupts 12 10 12 7 Control Registers 12 11 SPIA Ch n Mode Register 12 11 SPIA Ch n Control Register 12 12...

Page 9: ...zation 14 4 14 4 2 Counter Block Operations 14 5 14 4 3 Comparator Capture Block Operations 14 8 14 4 4 TOUT Output Control 14 16 14 5 Interrupt 14 22 14 6 Control Registers 14 22 T16B Ch n Clock Control Register 14 22 T16B Ch n Counter Control Register 14 23 T16B Ch n Max Counter Data Register 14 24 T16B Ch n Timer Counter Data Register 14 24 T16B Ch n Counter Status Register 14 25 T16B Ch n Inte...

Page 10: ...ighting Cycle 16 3 16 4 Operations 16 3 16 4 1 Initialization 16 3 16 4 2 Display On Off 16 4 16 4 3 Common Mode 16 4 16 4 4 Number of Display Digits 16 4 16 4 5 Brightness Adjustment 16 4 16 4 6 Display Data Registers 16 5 16 4 7 Drive Waveform 16 5 16 5 Interrupt 16 6 16 6 Control Registers 16 6 LEDC Clock Control Register 16 6 LEDC Control Register 16 7 LEDC Lighting Period Setting Register 16 ...

Page 11: ...racteristics 19 10 19 12 12 bit A D Converter ADC12A Characteristics 19 11 20 Basic External Connection Diagram 20 1 21 Package 21 1 Appendix A List of Peripheral Circuit Control Registers AP A 1 0x4000 0x4008 Misc Registers MISC AP A 1 0x4020 Power Generator PWG AP A 1 0x4040 0x4050 Clock Generator CLG AP A 1 0x4080 0x4090 Interrupt Controller ITC AP A 2 0x40a0 0x40a4 Watchdog Timer WDT2 AP A 3 0...

Page 12: ...Appendix B Power Saving AP B 1 B 1 Operating Status Configuration Examples for Power Saving AP B 1 B 2 Other Power Saving Methods AP B 2 Appendix C Mounting Precautions AP C 1 Appendix D Measures Against Noise AP D 1 Appendix E Initialization Routine AP E 1 Revision History ...

Page 13: ... wake up from SLEEP state Operating clock frequency for the CPU and all peripheral circuits is selectable I O port PPORT Number of general purpose I O ports Input output port 38 bits max Output port 1 bit max Pins are shared with the peripheral I O Number of input interrupt ports 34 bits max Number of ports that support universal port multiplexer UPMUX 21 bits A peripheral circuit I O function sel...

Page 14: ...reset Reset when the power supply voltage drops Key entry reset Reset when the P00 to P01 P02 P03 keys are pressed simultaneously can be en abled disabled using a register Watchdog timer reset Reset when the watchdog timer overflows can be enabled disabled using a register Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level can be enabled disabled usi...

Page 15: ...2 Coprocessor bus Instruction bus 16 bit internal bus SDA0 SCL0 EXSVD0 1 P00 07 P10 17 P20 24 P40 47 P50 54 PD0 D1 PD3 D4 PD2 Interrupt controller ITC I O port PPORT Watchdog timer WDT2 I2C I2C 1 Ch Supply voltage detector SVD3 16 bit timer T16 4 Ch TOUT00 01 CAP00 01 EXCL00 01 16 bit PWM timer T16B 1 Ch SDI0 1 SDO0 1 SPICLK0 1 SPISS0 1 Synchronous serial interface SPIA 2 Ch USIN0 USOUT0 UART UART...

Page 16: ... UPMUX P23 UPMUX P22 UPMUX P21 UPMUX P20 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 V DD RESET 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 S1C17M12 VSS VD1 PD4 PD3 P17 P16 P15 P14 P13 P12 P11 P10 VSS VD1 PD4 OSC4 PD3 OSC3 P17 UPMUX P16 FOUT UPMUX P15 EXCL01 UPMUX P14 EXCL00 UPMUX P13 EXOSC UPMUX P12 UPMUX EXSVD1 P11 UPMUX EXSVD0 P10 UPMUX Pin name P40 P41 P42 P43 VSS2 P44 P45 P46...

Page 17: ... P23 UPMUX P22 UPMUX P21 UPMUX P20 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 V DD RESET 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 S1C17M13 VSS VD1 PD4 PD3 P17 P16 P15 P14 P13 P12 P11 P10 VSS VD1 PD4 OSC4 PD3 OSC3 P17 ADTRG0 UPMUX P16 FOUT UPMUX P15 EXCL01 UPMUX P14 EXCL00 UPMUX P13 EXOSC UPMUX P12 UPMUX EXSVD1 P11 UPMUX EXSVD0 P10 UPMUX VREFA0 Pin name P40 P41 P42 P43 VSS2 P44...

Page 18: ... PD2 PD1 PD0 V DD RESET V SS2 V PP P24 UPMUX P23 UPMUX P22 UPMUX P21 UPMUX P20 UPMUX DCLK PD2 DSIO PD1 DST2 PD0 V DD RESET VSS VD1 PD4 PD3 P17 P16 P15 P14 P13 P12 P11 P10 VSS VD1 PD4 OSC4 PD3 OSC3 P17 UPMUX P16 FOUT UPMUX P15 EXCL01 UPMUX P14 EXCL00 UPMUX P13 EXOSC UPMUX P12 UPMUX EXSVD1 P11 UPMUX EXSVD0 P10 UPMUX Die No CJxxxxxxx 1 1 1 1 1 Pad name P40 P41 P42 P43 VSS2 P44 P45 P46 P47 VSS2 P50 P5...

Page 19: ... COM0 P50 REMO COM0 P50 REMO COM0 P50 REMO COM0 P51 CLPLS COM1 P51 CLPLS COM1 P51 CLPLS COM1 P51 CLPLS COM1 Die No CJxxxxxxx 1 1 1 1 1 Figure 1 3 2 2 S1C17M13 Pad Configuration Diagram Chip 1 These pads have the same specification Select one pad to be used Pad opening X 68 µm Y 68 µm Chip thickness 400 µm Table 1 3 2 1 S1C17M12 M13 Pad Coordinates No X µm Y µm No X µm Y µm No X µm Y µm No X µm Y µ...

Page 20: ... input 7 P01 P01 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer ADIN06 A 12 bit A D converter Ch 0 analog signal input 6 P02 P02 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer ADIN05 A 12 bit A D converter Ch 0 analog signal input 5 P03 P03 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer ADIN04 A 12 bit A D converter Ch 0...

Page 21: ...vel high current drive output SEG1 O LED segment output P42 P42 I O Hi Z I O port Low level high current drive output SEG2 O LED segment output P43 P43 I O Hi Z I O port Low level high current drive output SEG3 O LED segment output P44 P44 I O Hi Z I O port Low level high current drive output SEG4 O LED segment output P45 P45 I O Hi Z I O port Low level high current drive output SEG5 O LED segment...

Page 22: ...e assigned I O Channel number n Function Synchronous serial interface SPIA SDIn I n 0 1 SPIA Ch n data input SDOn O SPIA Ch n data output SPICLKn I O SPIA Ch n clock input output SPISSn I SPIA Ch n slave select input I2C I2C SCLn I O n 0 I2C Ch n clock input output SDAn I O I2C Ch n data input output UART UART3 USINn I n 0 UART3 Ch n data input USOUTn O UART3 Ch n data output 16 bit PWM timer T16B...

Page 23: ...n modes normal mode and economy mode and setting the VD1 regulator into economy mode at light loads helps achieve low power operations Figure 2 1 1 1 shows the PWG configuration VDD VD1 VSS VSS2 CPW1 CPW3 VDD2 CPW2 PWG Internal circuits I O ports P50 54 VD1 regulator VD1 VD1ECO I O ports except for P40 47 P50 54 I O ports P40 47 Figure 2 1 1 1 PWG Configuration 2 1 2 Pins Table 2 1 2 1 lists the P...

Page 24: ...main features of SRC are outlined below Embedded reset hold circuit maintains reset state to boot the system safely while the internal power supply is un stable after power on or the oscillation frequency is unstable after the clock source is initiated Supports reset requests from multiple reset sources RESET pin POR and BOR Key entry reset Watchdog timer reset Supply voltage detector reset Periph...

Page 25: ...X RST RUN VDD VSS VRST VRST VRST VRST VRST X X X RST RST RST RST RUN RUN RUN Figure 2 2 3 1 Example of Internal Reset by POR and BOR For the POR and BOR electrical specifications refer to POR BOR characteristics in the Electrical Charac teristics chapter Key entry reset Inputting a low level signal of a certain period to the I O port pins configured to a reset input issues a reset re quest This fu...

Page 26: ...manages clock supply to the CPU and the peripheral circuits The main features of CLG are outlined below Supports multiple clock sources IOSC oscillator circuit that oscillates with a fast startup and no external parts required High speed OSC3 oscillator circuit in which the oscillator type can be specified from crystal ceramic oscilla tor an external resonator is required and internal oscillator E...

Page 27: ...OSC3 oscillator circuit output EXOSC I I EXOSC clock input FOUT O O L FOUT clock output Indicates the status when the pin is configured for CLG If the port is shared with the CLG input output function and other functions the CLG function must be assigned to the port For more information refer to the I O Ports chapter 2 3 3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features ...

Page 28: ... capacitor CGI3C Internal drain capacitor CDI3C Peripheral I O function 4 External drain capacitor CD3 Clock oscillator I O port Interrupt control circuit OSC3STAIE OSC3STAIF Figure 2 3 3 2 OSC3 Oscillator Circuit Configuration For the recommended parts and the oscillation characteristics refer to the Basic External Connection Dia gram chapter and OSC3 oscillator circuit characteristics in the Ele...

Page 29: ...waiting completion flag and starts clock supply to the internal circuits Note The oscillation stabilization waiting time is always expended at start of oscillation even if the os cillation stabilization waiting completion flag has not be cleared to 0 Oscillation start procedure for the IOSC oscillator circuit Follow the procedure shown below to start oscillation of the IOSC oscillator circuit 1 Wr...

Page 30: ...t executes the slp instruction Whether the clock sources being operated are stopped or not at this point can be selected in each source individually This allows the CPU to fast switch between SLEEP mode and RUN mode and the peripheral circuits to continue operating without disabling the clock in SLEEP mode The CLGOSC IOSCSLPC CLGOSC OSC3SLPC and CLGOSC EXOSCSLPC bits are used for this control Figu...

Page 31: ...ck source or its divided clock to outside the IC This al lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external ICs Follow the procedure shown below to start clock external output 1 Assign the FOUT function to the port Refer to the I O Ports chapter 2 Configure the following CLGFOUT register bits CLGFOUT FOUTSRC 1 0 bits Select clock source ...

Page 32: ...uit operations are required power consumption can be less than HALT mode The RAM retains data even in SLEEP mode Note The current consumption when a clock source is active in SLEEP mode by setting the CLGOSC IOSCSLPC OSC3SLPC EXOSCSLPC bit to 0 is equivalent to the value in HALT mode with the same clock source condition refer to Current Consumption Current consumption in HALT mode IHALT1 and IHALT...

Page 33: ...tion stabilization waiting operation has completed after the oscillation starts Writing 1 CLG provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapt...

Page 34: ...ratio for resetting the CLGSCLK CLKDIV 1 0 bits at wake up This setting is ineffective when the CLGSCLK WUPMD bit 0 Bits 11 10 Reserved Bits 9 8 WUPSRC 1 0 These bits select the SYSCLK clock source for resetting the CLGSCLK CLKSRC 1 0 bits at wake up When a currently stopped clock source is selected it will automatically start oscillating or clock input at wake up However this setting is ineffecti...

Page 35: ...SCSLPC bit EXOSC clock input CLGOSC OSC3SLPC bit OSC3 oscillator circuit CLGOSC IOSCSLPC bit IOSC oscillator circuit Bits 7 4 1 Reserved Bit 3 EXOSCEN Bit 2 OSC3EN Bit 0 IOSCEN These bits control the clock source operation 1 R W Start oscillating or clock input 0 R W Stop oscillating or clock input Each bit corresponds to the clock source as follows CLGOSC EXOSCEN bit EXOSC clock input CLGOSC OSC3...

Page 36: ...r Gain Setting CLGOSC3 OSC3INV 1 0 bits Inverter gain 0x3 Max 0x2 0x1 0x0 Min Bit 3 Reserved Bits 2 0 OSC3WT 2 0 These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit Table 2 6 7 OSC3 Oscillation Stabilization Waiting Time Setting CLGOSC3 OSC3WT 2 0 bits Oscillation stabilization waiting time 0x7 65 536 clocks 0x6 16 384 clocks 0x5 4 096 clocks 0x4 1 024 clocks ...

Page 37: ...ds to the interrupt as follows CLGINTE OSC3STAIE bit OSC3 oscillation stabilization waiting completion interrupt CLGINTE IOSCSTAIE bit IOSC oscillation stabilization waiting completion interrupt CLG FOUT Control Register Register name Bit Bit name Initial Reset R W Remarks CLGFOUT 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTSRC 1 0 0x0 H0 R W 1 0 R 0 FOUTEN 0 H0 R W Bits 15 7 Reserved Bit...

Page 38: ...NUAL Rev 1 2 Bit 0 FOUTEN This bit controls the FOUT clock external output 1 R W Enable external output 0 R W Disable external output Note Since the FOUT signal generated is out of sync with writings to the CLGFOUT FOUTEN bit a glitch may occur when the FOUT output is enabled or disabled ...

Page 39: ...nded up to 24 bits Supports reset NMI address misaligned debug and external interrupts Reads a vector from the vector table and branches to the interrupt handler routine directly Can generate software interrupts with a vector number specified all vector numbers specifiable HALT mode halt instruction and SLEEP mode slp instruction are provided as the standby function Incorporates a debugger with th...

Page 40: ...tten to PSR through the MSCPSR register 3 2 4 I O Area Reserved for the S1C17 Core The address range from 0xfffc00 to 0xffffff is the I O area reserved for the S1C17 core Do not access this area ex cept when it is required 3 3 Debugger 3 3 1 Debugging Functions The debugger provides the following functions Instruction break A debug interrupt is generated immediately before the set instruction addr...

Page 41: ...ak signal DST2 O O On chip debugger status output pin Outputs the processor status during debugging The debugger input output pins are shared with general purpose I O ports and are initially set as the debug pins If the debugging function is not used these pins can be switched to general purpose I O port pins For details refer to the I O Ports chapter Notes Do not drive the DCLK pin with a high le...

Page 42: ...can be disabled by entering the unprotecting password predefined to GNU17 IDE the security function will take effect again after a reset For setting the password refer to the S1C17 Fam ily C Compiler Package S5U1C17001C Manual Note Disable the Flash security function before debugging an IC with protected Flash via ICDmini The debugging functions may not run normally if the Flash security function ...

Page 43: ... 2 Debug RAM Base Register Register name Bit Bit name Initial Reset R W Remarks DBRAM 31 24 0x00 R 23 0 DBRAM 23 0 1 H0 R 1 Debugging work area start address Bits 31 24 Reserved Bits 23 0 DBRAM 23 0 The start address of the debugging work area 64 bytes can be read out with these bits ...

Page 44: ...00 8000 0x00 7fff Reserved 0x00 6000 0x00 5fff Peripheral circuit area 8K bytes Device size 16 bits 0x00 4000 0x00 3fff Reserved 0x00 0800 0x00 07ff 0x00 07c0 Debug RAM area 64 bytes 0x00 07bf RAM area 2K bytes Device size 32 bits 0x00 0000 Figure 4 1 1 Memory Map 4 2 Bus Access Cycle The CPU uses the system clock for bus access operations First Bus access cycle Device size and Access size are def...

Page 45: ...ata area bus cycles When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area When the CPU executes an instruction stored in the internal RAM area and accesses data in the internal RAM area 4 3 Flash Memory The Flash memory is used to store application programs and data Address 0x8000 in the Flash area is defined as the vector table base address by default t...

Page 46: ...his area from the application program This area can be used for applications of mass produced devices that do not need debugging The RAM size used by the application can be configured to equal or less than the implemented size using the MSCIRAMSZ IRAMSZ 2 0 bits For example this function can be used to prevent creating programs that seek to access areas outside the RAM area of the target model whe...

Page 47: ...nable Register 0x4204 P0RCTL P0 Port Pull up down Control Register 0x4206 P0INTF P0 Port Interrupt Flag Register 0x4208 P0INTCTL P0 Port Interrupt Control Register 0x420a P0CHATEN P0 Port Chattering Filter Enable Register 0x420c P0MODSEL P0 Port Mode Select Register 0x420e P0FNCSEL P0 Port Function Select Register 0x4210 P1DAT P1 Port Data Register 0x4212 P1IOEN P1 Port Enable Register 0x4214 P1RC...

Page 48: ...T3 Ch 0 Interrupt Enable Register 0x4390 UA0CAWF UART3 Ch 0 Carrier Waveform Register 16 bit timer T16 Ch 1 0x43a0 T16_1CLK T16 Ch 1 Clock Control Register 0x43a2 T16_1MOD T16 Ch 1 Mode Register 0x43a4 T16_1CTL T16 Ch 1 Control Register 0x43a6 T16_1TR T16 Ch 1 Reload Data Register 0x43a8 T16_1TC T16 Ch 1 Counter Data Register 0x43aa T16_1INTF T16 Ch 1 Interrupt Flag Register 0x43ac T16_1INTE T16 C...

Page 49: ... COM3 2 Data Register 0x5414 LEDCDAT4 LEDC COM4 Data Register 16 bit timer T16 Ch 3 0x5480 T16_3CLK T16 Ch 3 Clock Control Register 0x5482 T16_3MOD T16 Ch 3 Mode Register 0x5484 T16_3CTL T16 Ch 3 Control Register 0x5486 T16_3TR T16 Ch 3 Reload Data Register 0x5488 T16_3TC T16 Ch 3 Counter Data Register 0x548a T16_3INTF T16 Ch 3 Interrupt Flag Register 0x548c T16_3INTE T16 Ch 3 Interrupt Enable Reg...

Page 50: ...ays set to 0 7 3 0x04 R 2 0 IRAMSZ 2 0 0x2 H0 R WP Bits 15 3 Reserved Bits 2 0 IRAMSZ 2 0 These bits set the internal RAM size that can be used Table 4 7 1 Internal RAM Size Selections MSCIRAMSZ IRAMSZ 2 0 bits Internal RAM size 0x7 0x3 Reserved 0x2 2KB 0x1 1KB 0x0 512B FLASHC Flash Read Cycle Register Register name Bit Bit name Initial Reset R W Remarks FLASHCWAIT 15 9 0x00 R 8 reserved 0 H0 R WP...

Page 51: ...al Debug interrupt HALT SLEEP cancelation signal Interrupt request NMI ILVx 2 0 Interrupt control circuit ILVy 2 0 Interrupt request Peripheral circuit Peripheral circuit Internal data bus Figure 5 1 1 ITC Configuration 5 2 Vector Table The vector table contains the vectors to the interrupt handler routines handler routine start address that will be read by the CPU to execute the handler when an i...

Page 52: ...h 0 interrupt Capture overwrite Compare capture Counter MAX Counter zero 15 0x0f TTBR 0x3c 16 bit timer Ch 2 interrupt Underﬂow 16 0x10 TTBR 0x40 16 bit timer Ch 3 interrupt Underﬂow 17 0x11 TTBR 0x44 IR remote controller interrupt Compare AP Compare DB 18 0x12 TTBR 0x48 12 bit A D converter interrupt Analog input signal m A D conversion completion Analog input signal m A D conversion result overw...

Page 53: ...or specific information on causes of interrupts interrupt flags and interrupt enable bits refer to the respective pe ripheral circuit descriptions Note To prevent occurrence of unnecessary interrupts the corresponding interrupt flag should be cleared before setting the interrupt enable bit to 1 interrupt enabled and before terminating the interrupt handler routine 5 4 2 ITC Interrupt Request Proce...

Page 54: ... non maskable interrupt The processor performs the same interrupt processing operation as that of the hardware interrupt 5 7 Interrupt Processing by the CPU The CPU samples interrupt requests for each cycle On accepting an interrupt request the CPU switches to inter rupt processing immediately after execution of the current instruction has been completed Interrupt processing involves the following...

Page 55: ...1 2 0 0x0 H0 R W 7 3 0x00 R 2 0 ILVy0 2 0 0x0 H0 R W Bits 15 11 Reserved Bits 7 3 Reserved Bits 10 8 ILVy1 2 0 y1 2x 1 Bits 2 0 ILVy0 2 0 y0 2x These bits set the interrupt level of each interrupt Table 5 8 1 Interrupt Level and Priority Settings ITCLVx ILVy 2 0 bits Interrupt level Priority 0x7 7 High 0x6 6 0x1 1 0x0 0 Low The following shows the ITCLVx register configuration in this IC Table 5 8...

Page 56: ...C Interrupt Level Setup Register 5 15 11 0x00 R 10 8 ILV11 2 0 0x0 H0 R W 16 bit timer Ch 2 interrupt ILVT16_2 7 3 0x00 R 2 0 ILV10 2 0 0x0 H0 R W 16 bit PWM timer Ch 0 interrupt ILVT16B_0 ITCLV6 ITC Interrupt Level Setup Register 6 15 11 0x00 R 10 8 ILV13 2 0 0x0 H0 R W IR remote controller interrupt ILVREMC2_0 7 3 0x00 R 2 0 ILV12 2 0 0x0 H0 R W 16 bit timer Ch 3 interrupt ILVT16_3 ITCLV7 ITC In...

Page 57: ...M13 Item S1C17M12 S1C17M13 Port groups included P0 7 0 P1 7 0 P2 4 0 P4 7 0 P5 4 0 Pd 4 0 Ports with general purpose I O function GPIO P0 7 0 P1 7 0 P2 4 0 P4 7 0 P5 4 0 Pd 4 0 Pd2 output only Ports with interrupt function P0 7 0 P1 7 0 P2 4 0 P4 7 0 P5 4 0 Ports with low level high current drive output P4 7 0 Ports with high level high current drive output P5 4 0 Ports for debug function Pd 2 0 K...

Page 58: ...Fail Safe Type I O Cell The over voltage tolerant fail safe type I O cell allows interfacing without passing unnecessary current even if a voltage exceeding VDD is applied to the port Also unnecessary current is not consumed when the port is externally biased without supplying VDD However be sure to avoid applying a voltage exceeding the recommended maxi mum operating power supply voltage to the p...

Page 59: ...ction Clock frequency setting 4 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection Settings in Step 3 determine the input sampling time of the chattering filter 6 3 2 Clock Supply in SLEEP Mode When using the chattering filter function during SLEEP mode the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC x...

Page 60: ...unction Configuration of this IC For the specific information on the peripheral I O functions refer to the respective peripheral circuit chapter Initial settings when using a port as a general purpose output port only for the ports with GPIO function When using the Pxy port pin as a general purpose output pin perform the following software initial settings 1 Set the PxIOEN PxOENy bit to 1 Enable o...

Page 61: ...s placed into floating status 2 Use of the pull up or pull down function is recommended as undesired current will flow if the port input is set to floating status Note If the PxMODSEL PxSELy bit for the port without a GPIO function is set to 0 the port goes into initial status refer to Initial Settings The GPIO control bits are configured to a read only bit al ways read out as 0 6 4 2 Port Input O...

Page 62: ... only when low level signals longer than the time configured are input enable the chattering filter function for all the ports used for key entry reset The pins configured for key entry reset can also be used as general purpose input pins 6 5 Interrupts When the GPIO function is selected for the port with an interrupt function the port input interrupt function can be used Table 6 5 1 Port Input In...

Page 63: ...ort pin Low level The port pin status can be read out when input is enabled PxIOEN PxIENy bit 1 When input is disabled PxIOEN PxIENy bit 0 these bits are always read as 0 When the port is used for a peripheral I O function the input value cannot be read out from these bits Px Port Enable Register Register name Bit Bit name Initial Reset R W Remarks PxIOEN 15 8 PxIEN 7 0 0x00 H0 R W 7 0 PxOEN 7 0 0...

Page 64: ...g 1 1 This register is effective when the GPIO function is selected 2 The bit configuration differs depending on the port group Bits 15 8 Reserved Bits 7 0 PxIF 7 0 These bits indicate the port input interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective Px Port Interrupt Control Register Register name Bit Bit name Initia...

Page 65: ...Register name Bit Bit name Initial Reset R W Remarks PxFNCSEL 15 14 Px7MUX 1 0 0x0 H0 R W 13 12 Px6MUX 1 0 0x0 H0 R W 11 10 Px5MUX 1 0 0x0 H0 R W 9 8 Px4MUX 1 0 0x0 H0 R W 7 6 Px3MUX 1 0 0x0 H0 R W 5 4 Px2MUX 1 0 0x0 H0 R W 3 2 Px1MUX 1 0 0x0 H0 R W 1 0 Px0MUX 1 0 0x0 H0 R W 1 The bit configuration differs depending on the port group 2 The initial value may be changed by the port Bits 15 14 Px7MUX...

Page 66: ...when P0 1 0 inputs all low 0x0 Disable Bits 1 0 CLKSRC 1 0 These bits select the clock source of PPORT chattering filter The PPORT operating clock should be configured by selecting the clock source using the PCLK CLKSRC 1 0 bits and the clock division ratio using the PCLK CLKDIV 3 0 bits as shown in Table 6 6 3 These settings determine the input sampling time of the chattering filter Table 6 6 3 C...

Page 67: ...6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R 1 Only the bits corresponding to the port groups that support interrupts are provided Bits 15 13 Reserved Bits 12 0 PxINT These bits indicate that Px port group includes a port that has generated an interrupt 1 R A port generated an interrupt 0 R No port generated an interrupt The PINTFGRP PxINT b...

Page 68: ...upt Control Register 15 8 P0EDGE 7 0 0x00 H0 R W 7 0 P0IE 7 0 0x00 H0 R W P0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P0CHATEN 7 0 0x00 H0 R W P0MODSEL P0 Port Mode Select Register 15 8 0x00 R 7 0 P0SEL 7 0 0x00 H0 R W P0FNCSEL P0 Port Function Select Register 15 14 P07MUX 1 0 0x0 H0 R W 13 12 P06MUX 1 0 0x0 H0 R W 11 10 P05MUX 1 0 0x0 H0 R W 9 8 P04MUX 1 0 0x0 H0 R W 7 6 P0...

Page 69: ...attering Filter Enable Register 15 8 0x00 R 7 0 P1CHATEN 7 0 0x00 H0 R W P1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 0 P1SEL 7 0 0x00 H0 R W P1FNCSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R W 13 12 P16MUX 1 0 0x0 H0 R W 11 10 P15MUX 1 0 0x0 H0 R W 9 8 P14MUX 1 0 0x0 H0 R W 7 6 P13MUX 1 0 0x0 H0 R W 5 4 P12MUX 1 0 0x0 H0 R W 3 2 P11MUX 1 0 0x0 H0 R W 1 0 P10MUX 1 0 0x0 H0...

Page 70: ...4 0 P2IF 4 0 0x00 H0 R W Cleared by writing 1 P2INTCTL P2 Port Interrupt Control Register 15 13 0x0 R 12 8 P2EDGE 4 0 0x00 H0 R W 7 5 0x0 R 4 0 P2IE 4 0 0x00 H0 R W P2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 5 0x0 R 4 0 P2CHATEN 4 0 0x00 H0 R W P2MODSEL P2 Port Mode Select Register 15 8 0x00 R 7 5 0x0 R 4 0 P2SEL 4 0 0x00 H0 R W P2FNCSEL P2 Port Function Select Register 15 10...

Page 71: ...l Register 15 8 P4EDGE 7 0 0x00 H0 R W 7 0 P4IE 7 0 0x00 H0 R W P4CHATEN P4 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P4CHATEN 7 0 0x00 H0 R W P4MODSEL P4 Port Mode Select Register 15 8 0x00 R 7 0 P4SEL 7 0 0x00 H0 R W P4FNCSEL P4 Port Function Select Register 15 14 P47MUX 1 0 0x0 H0 R W 13 12 P46MUX 1 0 0x0 H0 R W 11 10 P45MUX 1 0 0x0 H0 R W 9 8 P44MUX 1 0 0x0 H0 R W 7 6 P43MUX 1 0 0...

Page 72: ... 5 0x0 R 4 0 P5IF 4 0 0x00 H0 R W Cleared by writing 1 P5INTCTL P5 Port Interrupt Control Register 15 13 0x0 R 12 8 P5EDGE 4 0 0x00 H0 R W 7 5 0x0 R 4 0 P5IE 4 0 0x00 H0 R W P5CHATEN P5 Port Chattering Filter Enable Register 15 8 0x00 R 7 5 0x0 R 4 0 P5CHATEN 4 0 0x00 H0 R W P5MODSEL P5 Port Mode Select Register 15 8 0x00 R 7 5 0x0 R 4 0 P5SEL 4 0 0x00 H0 R W P5FNCSEL P5 Port Function Select Regis...

Page 73: ...0 R W 9 8 PDIEN 1 0 0x0 H0 R W 7 5 0x0 R 4 0 PDOEN 4 0 0x00 H0 R W PDRCTL Pd Port Pull up down Control Register 15 13 0x0 R 12 11 PDPDPU 4 3 0x0 H0 R W 10 reserved 0 H0 R W 9 8 PDPDPU 1 0 0x0 H0 R W 7 5 0x0 R 4 3 PDREN 4 3 0x0 H0 R W 2 reserved 0 H0 R W 1 0 PDREN 1 0 0x0 H0 R W PDINTF PDINTCTL PDCHATEN 15 0 0x0000 R PDMODSEL Pd Port Mode Select Register 15 8 0x00 R 7 5 0x0 R 4 0 PDSEL 4 0 0x07 H0 ...

Page 74: ...n Use with Port Groups Register name Bit Bit name Initial Reset R W Remarks PCLK P Port Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 KRSTCFG 1 0 0x0 H0 R WP 1 0 CLKSRC 1 0 0x0 H0 R WP PINTFGRP P Port Interrupt Flag Group Register 15 8 0x00 R 7 6 0x0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R ...

Page 75: ...ERISEL 2 0 Output data selector Peripheral circuit I O port Pxy Internal data bus Figure 7 1 1 UPMUX Configuration 7 2 Peripheral Circuit I O Function Assignment An I O function of a peripheral circuit supported may be assigned to peripheral I O function 1 of an I O port listed above The following shows the procedure to assign a peripheral I O function and enable it in the I O port 1 Configure the...

Page 76: ...ircuit channel number See Table 7 3 1 Bits 10 8 PxzPERISEL 2 0 Bits 2 0 PxyPERISEL 2 0 These bits specify a peripheral circuit See Table 7 3 1 Table 7 3 1 Peripheral I O Function Selections PxUPMUXn PxyPPFNC 2 0 bits Peripheral I O function PxUPMUXn PxyPERISEL 2 0 bits Peripheral circuit 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 None I2C SPIA UART3 T16B Reserved Reserved Reserved PxUPMUXn PxyPERICH 1 0 bits...

Page 77: ...e supplied to WDT2 from the clock generator The CLK_WDT2 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following WDTCLK register bits WDTCLK CLKSRC 1 0 bits Clock source ...

Page 78: ...t be reset periodi cally via software while WDT2 is running 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Write 1 to the WDTCTL WDTCNTRST bit Reset WDT2 counter 3 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection A location should be provided for periodically processing this routine Process this routine within the tWDT cycle After resetti...

Page 79: ...after clearing SLEEP mode reset WDT2 before executing the slp instruction WDT2 should also be stopped as required us ing the WDTCTL WDTRUN 3 0 bits 8 4 Control Registers WDT2 Clock Control Register Register name Bit Bit name Initial Reset R W Remarks WDTCLK 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP Bits 15 9 Reserved Bit 8 DBRUN This bi...

Page 80: ...TATNMI This bit indicates that a counter compare match and NMI have occurred 1 R NMI counter compare match occurred 0 R NMI not occurred When the NMI generation function of WDT2 is used read this bit in the NMI handler routine to con firm that WDT2 was the source of the NMI The WDTCTL STATNMI bit set to 1 is cleared to 0 by writing 1 to the WDTCTL WDTCNTRST bit Bits 7 5 Reserved Bit 4 WDTCNTRST Th...

Page 81: ...AL Seiko Epson Corporation 8 5 Rev 1 2 Bits 9 0 CMP 9 0 These bits set the NMI reset generation cycle The value set in this register is compared with the 10 bit counter value while WDT2 is running and an NMI or reset is generated when they are matched ...

Page 82: ...nterrupt Supports intermittent operations Three detection cycles are selectable Low power supply voltage detection count function to generate an inter rupt reset when low power supply voltage is successively detected the number of times specified Continuous operation is also possible Figure 9 1 1 shows the configuration of SVD3 Table 9 1 1 SVD3 Configuration of S1C17M12 M13 Item S1C17M12 S1C17M12 ...

Page 83: ...al Characteristics chapter 9 3 Clock Settings 9 3 1 SVD3 Operating Clock When using SVD3 the SVD3 operating clock CLK_SVD3 must be supplied to SVD3 from the clock generator The CLK_SVD3 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Gen...

Page 84: ...upt Write 1 to the SVDINTF SVDIF bit Clear interrupt flag Set the SVDINTE SVDIE bit to 1 Enable SVD3 interrupt 5 Set the SVDCTL MODEN bit to 1 Enable SVD3 detection 6 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection Terminating detection Follow the procedure shown below to stop SVD3 operation 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2...

Page 85: ... be generated when SVD3 has successively detected low power supply voltage the number of times speci fied by the SVDCTL SVDSC 1 0 bits 1 When the SVDCTL SVDMD 1 0 bits 0x0 continuous operation mode VSVD VSVD VDD SVDCTL MODEN SVD3 operating status SVDINTF SVDDT Low power supply voltage detection interrupt DET 2 When the SVDCTL SVDMD 1 0 bits 0x0 intermittent operation mode VSVD Level set using the ...

Page 86: ...et state is can celed After that SVD3 resumes operating in the operation mode set previously via the initialization routine During reset state the SVD3 control bits are set as shown in Table 9 5 2 1 Table 9 5 2 1 SVD3 Control Bits During Reset State Control register Control bit Setting SVDCLK DBRUN Reset to the initial values CLKDIV 2 0 CLKSRC 1 0 SVDCTL VDSEL The set value is retained SVDSC 1 0 C...

Page 87: ...13 SVDSC 1 0 These bits set the condition to generate an interrupt reset number of successive low voltage detec tions in intermittent operation mode SVDCTL SVDMD 1 0 bits 0x1 to 0x3 Table 9 6 2 Interrupt Reset Generating Condition in Intermittent Operation Mode SVDCTL SVDSC 1 0 bits Interrupt reset generating condition 0x3 Low power supply voltage is successively detected eight times 0x2 Low power...

Page 88: ...Stop detection operations After this bit has been altered wait until the value written is read out from this bit without subsequent operations being performed Notes Writing 0 to the SVDCTL MODEN bit resets the SVD3 hardware However the register values set and the interrupt flag are not cleared The SVDCTL MODEN bit is actually set to 0 after this processing has finished If 1 is written to the SVDCT...

Page 89: ... after 1 is written to the SVDCTL MODEN bit SVD3 Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SVDINTE 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0 H0 R W Bits 15 1 Reserved Bit 0 SVDIE This bit enables low power supply voltage detection interrupts 1 R W Enable interrupts 0 R W Disable interrupts Notes If the SVDCTL SVDRE 3 0 bits are set to 0xa no low power supply voltage det...

Page 90: ... the counter underflow signal Ch 1 Synchronous serial interface Ch 0 master clock Ch 2 Synchronous serial interface Ch 1 master clock Ch 3 12 bit A D converter trigger signal T16 Ch n To interrupt controller To peripheral circuit Underflow PRESET Timer control circuit Interrupt control circuit PRUN TRMD CLKSRC 1 0 CLKDIV 3 0 Clock generator UFIE UFIF DBRUN MODEN CLK_T16_n Timer counter TC 15 0 Rel...

Page 91: ...ly during DEBUG mode should be controlled using the T16_nCLK DBRUN bit The CLK_T16_n supply to T16 Ch n is suspended when the CPU enters DEBUG mode if the T16_nCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_T16_n supply resumes Although T16 Ch n stops operat ing when the CLK_T16_n supply is suspended the counter and registers retain the status before DEBUG mode was entered If the T16...

Page 92: ...ing clock frequency Hz 10 4 3 Operations in Repeat Mode T16 Ch n enters repeat mode by setting the T16_nMOD TRMD bit to 0 In repeat mode the count operation starts by writing 1 to the T16_nCTL PRUN bit and continues until 0 is written A counter underflow presets the T16_nTR register value to the counter so underflow occurs periodically Select this mode to generate periodic underflow interrupts or ...

Page 93: ...ondition Clear condition Underﬂow T16_nINTF UFIF When the counter underﬂows Writing 1 T16 provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter 1...

Page 94: ...ot be selected as the clock source Note 2 When the T16_nCLK CLKSRC 1 0 bits are set to 0x3 EXCLm is selected for the channel with an event counter function or EXOSC is selected for other channels T16 Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks T16_nMOD 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W Bits 15 1 Reserved Bit 0 TRMD This bit selects the T16 operation mode 1 R W One ...

Page 95: ...erating clock 0 R W Disable Stop supplying operating clock T16 Ch n Reload Data Register Register name Bit Bit name Initial Reset R W Remarks T16_nTR 15 0 TR 15 0 0xffff H0 R W Bits 15 0 TR 15 0 These bits are used to set the initial value to be preset to the counter The value set to this register will be preset to the counter when 1 is written to the T16_nCTL PRESET bit or when the counter underf...

Page 96: ...it Bit name Initial Reset R W Remarks T16_nINTE 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W Bits 15 1 Reserved Bit 0 UFIE This bit enables T16 Ch n underflow interrupts 1 R W Enable interrupts 0 R W Disable interrupts Note To prevent generating unnecessary interrupts the corresponding interrupt flag should be cleared before enabling interrupts ...

Page 97: ...nsmit buffer empty end of transmission parity error framing error and overrun error interrupts Input pin can be pulled up with an internal resistor The output pin is configurable as an open drain output Provides the carrier modulation output function Figure 11 1 1 shows the UART3 configuration Table 11 1 1 UART3 Channel Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 Number of channels 1 chan...

Page 98: ...1 2 4 Output Pin Open Drain Output Function The USOUTn pin supports the open drain output function Default configuration is a push pull output and it is switched to an open drain output by setting the UAnMOD OUTMD bit to 1 11 2 5 Input Output Signal Inverting Function The UART3 can invert the signal polarities of the USINn pin input and the USOUTn pin output by setting the UAnMOD INVRX bit and the...

Page 99: ...he UAnMOD BRDIV UAnBR BRT 7 0 and UAnBR FMD 3 0 bit settings Use the following equations to calculate the setting values for obtaining the desired transfer rate CLK_UART2 CLK_UART2 bps BRT BRDIV FMD 1 Eq 11 1 BRT 1 bps FMD BRDIV Where bps Transfer rate bit s CLK_UART3 UART3 operating clock frequency Hz BRDIV Baud rate division ratio 1 16 or 1 4 Selected by the UAnMOD BRDIV bit BRT UAnBR BRT 7 0 se...

Page 100: ...TX bit Enable disable USOUTn output signal inversion UAnMOD PUEN bit Enable disable USINn pin pull up UAnMOD OUTMD bit Enable disable USOUTn pin open drain output UAnMOD IRMD bit Enable disable IrDA interface UAnMOD CHLN bit Set data length 7 or 8 bits UAnMOD PREN bit Enable disable parity function UAnMOD PRMD bit Select parity mode even or odd UAnMOD STPB bit Set stop bit length 1 or 2 bits UAnMO...

Page 101: ... transmit busy The shift register data bits are then output successively from the LSB Following output of MSB the parity bit if parity is en abled and the stop bit are output Even if transmit data is being output from the USOUTn pin the next transmit data can be written to the UAnTXD register after making sure the UAnINTF TBEIF bit is set to 1 If no transmit data remains in the UAnTXD register aft...

Page 102: ...oads the received data into the receive shift register The UAnINTF RBSY bit is set to 1 when the start bit is detected The UAnINTF RBSY bit is cleared to 0 and the receive shift register data is transferred to the receive data buf fer at the stop bit receive timing The receive data buffer consists of a 2 byte FIFO and receives data until it becomes full When the receive data buffer receives the fi...

Page 103: ... converted into 3 16 by the RZI modulator in SIR method Modulator input shift register output Modulator output USOUTn T1 T1 3 16 T1 3 16 Figure 11 5 4 2 IrDA Transmission Signal Waveform The received IrDA signal is input to the RZI demodulator and the low pulse width is converted into the normal width before input to the receive shift register Demodulator input USINn Demodulator output shift regis...

Page 104: ...is still transferred to the receive data buffer and the UAnINTF FEIF bit framing error interrupt flag is set to 1 when the data becomes ready to read from the UAnRXD register Note Framing error parity error interrupt flag set timings These interrupt flags will be set after the data that encountered an error is transferred to the re ceive data buffer Note however that the set timing depends on the ...

Page 105: ... second received data byte is loaded to the receive data buffer in which the first byte is already received Reading received data or software reset Receive buffer one byte full UAnINTF RB1FIF When the first received data byte is load ed to the emptied receive data buffer Reading data to empty the receive data buffer or software reset Transmit buffer empty UAnINTF TBEIF When transmit data written t...

Page 106: ... INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W Bits 15 13 Reserved Bit 12 PECAR This bit selects the carrier modulation period 1 R W Carrier modulation during H data period 0 R W Carrier modulation during L data period Bit 11 CAREN This bit enables the carrier modulation function 1 R W Enable carrier modulation...

Page 107: ... bit selects either odd parity or even parity when using the parity function 1 R W Odd parity 0 R W Even parity Bit 0 STPB This bit sets the stop bit length 1 R W 2 bits 0 R W 1 bit Notes The UAnMOD register settings can be altered only when the UAnCTL MODEN bit 0 Do not set both the UAnMOD IRMD and UAnMOD CAREN bits simultaneously UART3 Ch n Baud Rate Register Register name Bit Bit name Initial R...

Page 108: ...ed 0 R W Disable UART3 operations The operating clock is stopped Note If the UAnCTL MODEN bit is altered from 1 to 0 while sending receiving data the data being sent received cannot be guaranteed When setting the UAnCTL MODEN bit to 1 again after that be sure to write 1 to the UAnCTL SFTRST bit as well UART3 Ch n Transmit Data Register Register name Bit Bit name Initial Reset R W Remarks UAnTXD 15...

Page 109: ...atus See Figure 11 5 3 1 1 R During receiving 0 R Idle Bit 8 TBSY This bit indicates the sending status See Figure 11 5 2 1 1 R During sending 0 R Idle Bit 7 Reserved Bit 6 TENDIF Bit 5 FEIF Bit 4 PEIF Bit 3 OEIF Bit 2 RB2FIF Bit 1 RB1FIF Bit 0 TBEIF These bits indicate the UART3 interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W...

Page 110: ...nterrupts The following shows the correspondence between the bit and interrupt UAnINTE TENDIE bit End of transmission interrupt UAnINTE FEIE bit Framing error interrupt UAnINTE PEIE bit Parity error interrupt UAnINTE OEIE bit Overrun error interrupt UAnINTE RB2FIE bit Receive buffer two bytes full interrupt UAnINTE RB1FIE bit Receive buffer one byte full interrupt UAnINTE TBEIE bit Transmit buffer...

Page 111: ... being operated with the external input clock SPICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by an SPIA interrupt Input pins can be pulled up down with an internal resistor Figure 12 1 1 shows the SPIA configuration Table 12 1 1 SPIA Channel Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 Number of channels 2 channels Ch 0 and Ch 1 Internal clock input Ch ...

Page 112: ...ons the SPIA input output function must be assigned to the port before activating SPIA For more information refer to the I O Ports chapter 12 2 2 External Connections SPIA operates in master mode or slave mode Figures 12 2 2 1 and 12 2 2 2 show connection diagrams between SPIA in each mode and external SPI devices Px1 Px2 Px3 SDIn SDOn SPICLKn SPISS SDO SDI SPICLK SPISS SDO SDI SPICLK SPISS SDO SD...

Page 113: ... SPICLKn and SPISSn pins in slave mode have a pull up or pull down function as shown in Table 12 2 4 1 This function is enabled by setting the SPInMOD PUEN bit to 1 Table 12 2 4 1 Pull Up or Pull Down of Input Pins Pin Master mode Slave mode SDIn Pull up Pull up SPICLKn SPInMOD CPOL bit 1 Pull up SPInMOD CPOL bit 0 Pull down SPISSn Pull up 12 3 Clock Settings 12 3 1 SPIA Operating Clock Operating ...

Page 114: ...16_mCLK DB RUN bit The CLK_T16_m supply to SPIA Ch n is suspended when the CPU enters DEBUG mode if the T16_mCLK DB RUN bit 0 After the CPU returns to normal mode the CLK_T16_m supply resumes Although SPIA Ch n stops operating when the CLK_T16_m supply is suspended the output pins and registers retain the status before DEBUG mode was entered If the T16_mCLK DBRUN bit 1 the CLK_T16_m supply is not ...

Page 115: ...gister bits SPInMOD PUEN bit Enable input pin pull up down SPInMOD NOCLKDIV bit Select master mode operating clock SPInMOD LSBFST bit Select MSB first LSB first SPInMOD CPHA bit Select clock phase SPInMOD CPOL bit Select clock polarity SPInMOD MST bit Select master slave mode 3 Assign the SPIA Ch n input output function to the ports Refer to the I O Ports chapter 4 Set the following SPInCTL regist...

Page 116: ...the clock is being output from the SPICLKn pin the next transmit data can be written to the SPInTXD register after making sure the SPInINTF TBEIF bit is set to 1 If transmit data has not been written to the SPInTXD register after the last clock is output from the SPICLKn pin the clock output halts and the SPInINTF TENDIF bit is set to 1 At the same time SPIA issues an end of transmission interrupt...

Page 117: ...ng operations when transmit data may be dummy data if data transmission is not required is written to the SPInTXD register The SPICLKn pin outputs clocks of the number of the bits specified by the SPInMOD CHLN 3 0 bits The transmit data bits are output in sequence from the SDOn pin in sync with these clocks and the receive data bits input from the SDIn pin are shifted into the shift register When ...

Page 118: ...rom a general purpose port Assert the slave select signal output from a general purpose port Figure 12 5 3 2 Data Reception Flowcharts in Master Mode 12 5 4 Terminating Data Transfer in Master Mode A procedure to terminate data transfer in master mode is shown below 1 Wait for an end of transmission interrupt SPInINTF TENDIF bit 1 2 Set the SPInCTL MODEN bit to 0 to disable the SPIA Ch n operation...

Page 119: ...mode starts data transfer when SPICLKn is input from the external SPI master after the SPISSn signal is asserted Writing transmit data is not a trigger to start data transfer Therefore it is not necessary to write dummy data to the transmit data buffer when performing data reception only Data transmission reception can be performed even in SLEEP mode it makes it possible to wake the CPU up using a...

Page 120: ...nsmission SPInINTF TENDIF When the SPInINTF TBEIF bit 1 after data of the specified bit length defined by the SPInMOD CHLN 3 0 bits has been sent Writing 1 Receive buffer full SPInINTF RBFIF When data of the specified bit length is received and the received data is transferred from the shift register to the received data buffer Reading the SPIn RXD register Transmit buffer empty SPInINTF TBEIF Whe...

Page 121: ...PInMOD register 1 2 3 7 8 CPHA bit 1 0 CPOL bit 1 0 Writing data to the SPInTXD register Figure 12 6 1 SPInINTF BSY and SPInINTF TENDIF Bit Set Timings when SPInMOD CHLN 3 0 bits 0x7 12 7 Control Registers SPIA Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks SPInMOD 15 12 0x0 R 11 8 CHLN 3 0 0x7 H0 R W 7 6 0x0 R 5 PUEN 0 H0 R W 4 NOCLKDIV 0 H0 R W 3 LSBFST 0 H0 R W 2 CPHA 0...

Page 122: ...his setting is ineffective in slave mode 1 R W SPICLKn frequency CLK_SPIAn frequency 16 bit timer operating clock frequency 0 R W SPICLKn frequency 16 bit timer output frequency 2 For more information refer to SPIA Operating Clock Bit 3 LSBFST This bit configures the data format input output permutation 1 R W LSB first 0 R W MSB first Bit 2 CPHA Bit 1 CPOL These bits set the SPI clock phase and po...

Page 123: ...ode writing to these bits starts data transfer Transmit data can be written when the SPInINTF TBEIF bit 1 regardless of whether data is being output from the SDOn pin or not Note that the upper data bits that exceed the data bit length configured by the SPInMOD CHLN 3 0 bits will not be output from the SDOn pin Note Be sure to avoid writing to the SPInTXD register when the SPInINTF TBEIF bit 0 Oth...

Page 124: ... bit Overrun error interrupt SPInINTF TENDIF bit End of transmission interrupt SPInINTF RBFIF bit Receive buffer full interrupt SPInINTF TBEIF bit Transmit buffer empty interrupt SPIA Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SPInINTE 15 8 0x00 R 7 4 0x0 R 3 OEIE 0 H0 R W 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W Bits 15 4 Reserved Bit 3 OEIE Bit...

Page 125: ...ding function Can generate receive buffer full transmit buffer empty and other interrupts The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns Figure 13 1 1 shows the I2C configuration Table 13 1 1 I2C Channel Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 Number of channels 1 channel Ch 0 I2C Ch n Interrupt control circuit B...

Page 126: ... lines must be pulled up with an external resistor When the I2C is set into master mode one or more slave devices that have a unique address may be connected to the I2C bus When the I2C is set into slave mode one or more master and slave devices that have a unique address may be connected to the I2C bus SCLn VDD SDAn S1C17 Serial data SDA Serial clock SCL I2C bus External I2C device External I2C d...

Page 127: ... master mode the CLK_I2Cn supply during DEBUG mode should be controlled using the I2CnCLK DBRUN bit The CLK_I2Cn supply to the I2C Ch n is suspended when the CPU enters DEBUG mode if the I2CnCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_I2Cn supply resumes Although the I2C Ch n stops oper ating when the CLK_I2Cn supply is suspended the output pin and registers retain the status befo...

Page 128: ...ter mode 1 Configure the operating clock and the baud rate generator using the I2CnCLK and I2CnBR registers 2 Assign the I2C Ch n input output function to the ports Refer to the I O Ports chapter 3 Set the following bits when using the interrupt Write 1 to the interrupt flags in the I2CnINTF register Clear interrupt flags Set the interrupt enable bits in the I2CnINTE register to 1 Enable interrupt...

Page 129: ...ndition when the I2CnCTL TXSTART bit is set to 1 When the generating operation has completed the I2C Ch n clears the I2CnCTL TXSTART bit to 0 and sets both the I2CnINTF STARTIF and I2CnINTF TBEIF bits to 1 Sending slave address and data If the I2CnINTF TBEIF bit 1 a slave address or data can be written to the I2CnTXD register The I2C Ch n pulls down SCL to low and enters standby state until data i...

Page 130: ... by the external slave Standby state SCL low TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A S TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A TBEIF 1 TBEIF 1 NACKIF 1 NACKIF 1 NACKIF 1 Figure 13 4 2 1 Example of Data Sending Operations in Master Mode Data transmission End Write slave address and WRITE 0 to the I2CnTXD registe...

Page 131: ...CK bit to send a NACK after the last data is received and then go to Step 7 ii When the last data is received read the received data from the I2CnRXD register and set the I2CnCTL TXSTOP to 1 to generate a STOP condition Then go to Step 9 7 Read the received data from the I2CnRXD register 8 Repeat Steps 5 to 7 until the end of data reception 9 Wait for a STOP condition interrupt I2CnINTF STOPIF bit...

Page 132: ...CK A NACK Saddr R Slave address R 1 Data n 8 bit data Hardware bit operations Operations by the external slave Standby state SCL low RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 Figure 13 4 3 1 Example of Data Receiving Operations in Master Mode Data reception Write 1 to the I2CnCTL TXNACK bit YES NO One byte reception End Write slave address and READ 1 to the I2CnTXD register Write 1 to the...

Page 133: ...ndition by setting the I2CnCTL TXSTART bit to 1 2 Wait for a transmit buffer empty interrupt I2CnINTF TBEIF bit 1 or a START condition interrupt I2C nINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 3 Write the first address to the I2CnTXD TXD 7 1 bits and 0 that represents WRITE as the data transfer di rection to the I2CnTXD TXD0 bit 4 Wait for a tra...

Page 134: ... sending procedure in slave mode and the I2C Ch n operations are shown below Figures 13 4 5 1 and 13 4 5 2 show an operation example and a flowchart respectively Data sending procedure 1 Wait for a START condition interrupt I2CnINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 2 Check to see if the I2CnINTF TR bit 1 transmission mode Start a data recei...

Page 135: ...ring data transmission If the I2CnINTF TBEIF bit is still set to 1 when the data transmission from the shift register has completed the I2C Ch n pulls down SCL to low sets the I2C bus into clock stretching state until transmit data is written to the I2CnTXD register If the next transmit data already exists in the I2CnTXD register or data has been written after the above the I2C Ch n sends the subs...

Page 136: ... STOPIF bit 1 or a START condition interrupt I2CnINTF STARTIF bit 1 i Go to Step 10 when a STOP condition interrupt has occurred ii Go to Step 3 when a START condition interrupt has occurred 10 Clear the I2CnINTF STOPIF bit and then terminate data receiving operations Data receiving operations START condition detection and slave address check It is the same as the data transmission in slave mode H...

Page 137: ...ata transmission in slave mode S P Sr A STARTIF 1 BSY 0 STOPIF 1 Saddr W A Data 1 A Data 2 A Data N A RXD 7 0 Data 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 P Sr A Data N TXNACK 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 I2C bus Clock stretching by I2C Software bit operations Operations by the external master S STAR...

Page 138: ...g mode A 1stAddr W A 2ndAddr A 1stAddr W A 2ndAddr At start of data transmission At start of data reception S STARTIF 1 STARTIF 1 A Data 1 A Data 2 I2C bus Clock stretching by I2C I2C bus Clock stretching by I2C Software bit operations Operations by the external master S START condition Sr Repeated START condition P STOP condition A ACK A NACK 1stAddr W 1st address W 0 1stAddr R 1st address R 1 2n...

Page 139: ...rformed The table below lists the hardware error detection conditions and the notification method Table 13 4 9 1 Hardware Error Detection Function No Error detecting period timing I2C bus line monitored and error condition Notification method 1 While the I2C Ch n controls SDA to high for sending address data or a NACK SDA low I2CnINTF ERRIF 1 2 Master mode only When 1 is written to the I2CnCTL TX ...

Page 140: ...on is issued Slave mode When an address match is detected including general call Writing 1 software reset Error detection I2CnINTF ERRIF Refer to Error Detection Writing 1 software reset Receive buﬀer full I2CnINTF RBFIF When received data is loaded to the receive data buﬀer Reading received data to empty the receive data buﬀer software reset Transmit buﬀer empty I2CnINTF TBEIF Master mode When a ...

Page 141: ...1 0 0x0 H0 R W Bits 15 9 Reserved Bit 8 DBRUN This bit sets whether the I2C operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the I2C operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the I2C Table 13 6 1 Clo...

Page 142: ...gister name Bit Bit name Initial Reset R W Remarks I2CnBR 15 8 0x00 R 7 0 R 6 0 BRT 6 0 0x7f H0 R W Bits 15 7 Reserved Bits 6 0 BRT 6 0 These bits set the I2C Ch n transfer rate for master mode For more information refer to Baud Rate Generator Notes The I2CnBR register settings can be altered only when the I2CnCTL MODEN bit 0 Be sure to avoid setting the I2CnBR register to 0 I2C Ch n Own Address R...

Page 143: ... STOP condition 0 R STOP condition has been generated This bit is automatically cleared when the bus free time tBUF defined in the I2C Specifications has elapsed after the STOP condition has been generated Bit 2 TXSTART This bit issues a START condition in master mode This bit is ineffective in slave mode 1 W Issue a START condition 0 W Ineffective 1 R On standby or during generating a START condi...

Page 144: ...mit data cannot be guaranteed I2C Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks I2CnRXD 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R Bits 15 8 Reserved Bits 7 0 RXD 7 0 The receive data buffer can be read through these bits I2C Ch n Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks I2CnINTF 15 13 0x0 R 12 SDALOW 0 H0 R 11 SCLLOW 0 H0 R 1...

Page 145: ...W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt I2CnINTF BYTEENDIF bit End of transfer interrupt I2CnINTF GCIF bit General call address reception interrupt I2CnINTF NACKIF bit NACK reception interrupt I2CnINTF STOPIF bit STOP condition interrupt I2CnINTF STARTIF bit START condition interrupt I2CnINTF ERRIF bit Error detection interrupt I2CnINTF RBF...

Page 146: ...pts The following shows the correspondence between the bit and interrupt I2CnINTE BYTEENDIE bit End of transfer interrupt I2CnINTE GCIE bit General call address reception interrupt I2CnINTE NACKIE bit NACK reception interrupt I2CnINTE STOPIE bit STOP condition interrupt I2CnINTE STARTIE bit START condition interrupt I2CnINTE ERRIE bit Error detection interrupt I2CnINTE RBFIE bit Receive buffer ful...

Page 147: ...hannel The comparator compares the counter value with the values specified via software to generate interrupt sig nals and a PWM waveform Can be used as an interval timer PWM waveform generator and external event counter The capture circuit captures counter values using external software trigger signals and generates interrupts Can be used to measure external event periods cycles Figure 14 1 1 sho...

Page 148: ...ata bus TOUT control circuit 1 TOUT00 TOUT control circuit 0 TOUTMT TOUTO TOUTMD 2 0 TOUTINV TOUTMT TOUTO TOUTMD 2 0 TOUTINV Interrupt control circuit CAPOWmIE CMPCAPmIE CAPOW0IE CMPCAP0IE CNTMAXIE CNTZEROIE CAPI1 CAPOWmIF CMPCAPmIF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF UP_DOWN BSY MATCH signal MATCH signal ZERO MAX signal CAP02 03 TOUT02 03 CAP04 05 TOUT04 05 CAPn0 1 TOUTn0 1 CAPn2 3 TOUTn2 3 CAP...

Page 149: ...at those before entering SLEEP mode After the CPU returns to normal mode CLK_T16Bn is supplied and the T16B operation resumes 14 3 3 Clock Supply in DEBUG Mode The CLK_T16Bn supply during DEBUG mode should be controlled using the T16BnCLK DBRUN bit The CLK_T16Bn supply to T16B Ch n is suspended when the CPU enters DEBUG mode if the T16BnCLK DB RUN bit 0 After the CPU returns to normal mode the CLK...

Page 150: ...bits when using the interrupt Write 1 to the interrupt flags in the T16BnINTF register Clear interrupt flags Set the interrupt enable bits in the T16BnINTE register to 1 Enable interrupts 7 Set the following T16BnCTL register bits T16BnCTL CNTMD 1 0 bits Select count up down operation T16BnCTL ONEST bit Select one shot repeat operation Set the T16BnCTL PRESET bit to 1 Reset counter Set the T16BnCT...

Page 151: ...ritten after the counter has been reset to the previously set MAX value Counter reset Setting the T16BnCTL PRESET bit to 1 resets the counter This clears the counter to 0x0000 in up or up down mode or presets the MAX value to the counter in down mode The counter is also cleared to 0x0000 when the counter value exceeds the MAX value during count up operation Counting start To start counting set the...

Page 152: ...tions in repeat down count and one shot down count modes In these modes the counter operates as a down counter and counts from the MAX value or current value to 0x0000 In repeat down count mode the counter returns to the MAX value if a counter underflow occurs and continues counting until the T16BnCTL RUN bit is set to 0 If the MAX value is altered during counting the counter keeps counting down t...

Page 153: ...e current counter value during count up operation the counter keeps counting up to the new MAX value If the MAX value is altered to a value smaller than the current counter value the counter is cleared to 0x0000 and continues counting up to the new MAX value If the MAX value is altered during count down operation the counter keeps counting down to 0x0000 and then starts counting up to the new MAX ...

Page 154: ... T16BnCCRm register functions as the compare data register used for setting a comparison value in this mode The TOUTnm CAPnm pin is config ured to the TOUTnm pin When the counter reaches the value set in the T16BnCCRm register during counting the comparator asserts the MATCH signal and sets the T16BnINTF COMPCAPmIF bit compare interrupt flag to 1 When the counter reaches the MAX value in comparato...

Page 155: ... setting value 0 to 65 535 MAX T16BnMC register setting value 0 to 65 535 fCLK_T16B Count clock frequency Hz The comparator MATCH signal and counter MAX ZERO signals are also used to generate a timer output wave form TOUT Refer to TOUT Output Control for more information Compare buffer The comparator loads the comparison value which has been written to the T16BnCCRm register to the compare buffer ...

Page 156: ...0000 1 3 T16BnCCCTLm CBUFMD 2 0 bits 0x2 Count cycle RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTMAXIF 1 CNTMAXIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Compare period Counter Time Compare buffer value MAX value T16BnMC register 0xffff 0x0000 1 4 T16BnCCCTLm CBUFMD 2 0 bits 0x3 Count cycle RUN 1 Data W CC 15 0 Data W CC 15...

Page 157: ...C 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16BnMC register Count cycle Compare period 2 1 T16BnCCCTLm CBUFMD 2 0 bits 0x0 2 Repeat down count mode Software operation Hardware operation 2 2 T16BnCCCTLm CBUFMD 2 0 bits 0x1 0xffff 0x0000 RUN 1 Data W CC 15 0 Data...

Page 158: ...d 2 4 T16BnCCCTLm CBUFMD 2 0 bits 0x3 0xffff 0x0000 RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16BnMC register Count cycle Compare period 2 5 T16BnCCCTLm CBUFMD 2 0 bits 0x4 0xffff 0x0000 RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1...

Page 159: ...p 3 2 T16BnCCCTLm CBUFMD 2 0 bits 0x1 CNTZEROIF 1 0xffff 0x0000 RUN 1 Data W MC 15 0 Data W CC 15 0 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTZEROIF 1 CNTMAXIF 1 PRESET 1 Counter Time Count cycle Compare buffer value MAX value T16BnMC register Compare period during counting down Compare period during counting up 3 3 T16BnCCCTLm CBUFMD 2 0 b...

Page 160: ...e 14 4 3 2 Compare Buffer Operations Operations in capture mode The capture mode captures the counter value when an external event such as a key entry occurs at the speci fied edge of the external input software trigger signal In this mode the T16BnCCRm register functions as the capture register from which the captured data is read Furthermore the TOUTnm CAPnm pin is configured to the CAPnm pin Th...

Page 161: ...f invalid data reading by capturing counter data simultaneously with the counter being counted up down Set the T16BnCCCTLm SCS bit to 1 to set the capture circuit to synchronous capture mode This mode captures counter data by synchronizing the capture signal with the counter clock On the other hand asynchronous capture mode can capture counter data by detecting a trigger pulse even if the pulse is...

Page 162: ...1 TOUT Output Circuits Circuits 0 and 1 Each timer channel includes two four or six TOUT output circuits and their signal generation and output can be controlled individually TOUT generation mode The T16BnCCCTLm TOUTMD 2 0 bits are used to set how the TOUT signal waveform is changed by the MATCH and MAX ZERO signals Furthermore when the T16BnCCCTLm TOUTMT bit is set to 1 the TOUT circuit uses the ...

Page 163: ...ode 0x7 MAX value 5 Compare buffer value 2 T16BnCCCTLm TOUTINV bit 0 1 Repeat up count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value 4 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 RUN PRESET Count clock T16BnTC TC 15 0 MATCH signal ZERO signal T16BnCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode ...

Page 164: ... Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16BnCCCTLm TOUTINV bit 0 3 Repeat up down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value 1 0 2 3 4 5 4 3 2 1 0 1 2 3 4 5 Figure 14 4 4 2 TOUT Output Waveform T16BnCCCTLm TOUTMT bit 0 ...

Page 165: ...Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 1 Repeat up count mode indicates the T16BnCCCTLm T...

Page 166: ...TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 2 Repeat down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value 4 5...

Page 167: ...t mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 1 0 2 3 4 5 4 3 2 1 0 1 2 3 4 5 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16BnCCCTLm TOUTINV bit 0 3 Repeat up down count mode indicates the T16BnCCCTLm TOUTMD 2 0 bit setting value Figure 14 4 4...

Page 168: ...ter zero T16BnINTF CNTZEROIF When the counter reaches 0x0000 Writing 1 T16B provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter 14 6 Control Re...

Page 169: ... in this IC cannot be selected as the clock source T16B Ch n Counter Control Register Register name Bit Bit name Initial Reset R W Remarks T16BnCTL 15 9 0x00 R 8 MAXBSY 0 H0 R 7 6 0x0 R 5 4 CNTMD 1 0 0x0 H0 R W 3 ONEST 0 H0 R W 2 RUN 0 H0 R W 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W Bits 15 9 Reserved Bit 8 MAXBSY This bit indicates whether data can be written to the T16BnMC register or not 1 R Busy sta...

Page 170: ...ich has been set to the T16BnMC register is preset to the counter However the T16BnCTL MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance Bit 0 MODEN This bit enables the T16B Ch n operations 1 R W Enable Start supplying operating clock 0 R W Disable Stop supplying operating clock Note The counter reset operation using the T16BnCTL PRESET bit and the counting star...

Page 171: ... indicate the signal level currently input to the CAPnm pin 1 R Input signal High level 0 R Input signal Low level The following shows the correspondence between the bit and the CAPnm pin T16BnCS CAPI5 bit CAPn5 pin T16BnCS CAPI4 bit CAPn4 pin T16BnCS CAPI3 bit CAPn3 pin T16BnCS CAPI2 bit CAPn2 pin T16BnCS CAPI1 bit CAPn1 pin T16BnCS CAPI0 bit CAPn0 pin Note The configuration of the T16BnCS CAPIm ...

Page 172: ...use of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt T16BnINTF CAPOW5IF bit Capture 5 overwrite interrupt T16BnINTF CMPCAP5IF bit Compare capture 5 interrupt T16BnINTF CAPOW4IF bit Capture 4 overwrite interrupt T16BnINTF CMPCAP4IF bit Compare capture 4 interrupt T16BnINTF CAPOW3IF bit Capture 3 overwrite interrupt T16BnINTF C...

Page 173: ... and interrupt T16BnINTE CAPOW5IE bit Capture 5 overwrite interrupt T16BnINTE CMPCAP5IE bit Compare capture 5 interrupt T16BnINTE CAPOW4IE bit Capture 4 overwrite interrupt T16BnINTE CMPCAP4IE bit Compare capture 4 interrupt T16BnINTE CAPOW3IE bit Capture 3 overwrite interrupt T16BnINTE CMPCAP3IE bit Compare capture 3 interrupt T16BnINTE CAPOW2IE bit Capture 2 overwrite interrupt T16BnINTE CMPCAP2...

Page 174: ...omparison value set previously Also the counter is reset to 0x0000 simultaneously Down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to the MAX value simultaneously Up down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to 0x0000 simultaneously 0x3 Up mode When the counter reverts to 0x0000...

Page 175: ...e and is ineffective in capture mode Bits 4 2 TOUTMD 2 0 These bits configure how the TOUTnm signal waveform is changed by the comparator MATCH and counter MAX ZERO signals The T16BnCCCTLm TOUTMD 2 0 bits are control bits for comparator mode and are ineffective in capture mode Table 14 6 5 TOUT Generation Mode T16BnCCCTLm TOUTMD 2 0 bits TOUT generation mode and operations T16BnCCCTLm TOUTMT bit C...

Page 176: ...signal is inverted by the MATCHm signal and it be comes inactive by the MATCHm 1 signal TOUTnm 1 The signal is inverted by the MATCHm 1 signal and it be comes inactive by the MATCHm signal 0x1 Set mode 0 All count modes TOUTnm The signal becomes active by the MATCH signal 1 All count modes TOUTnm The signal becomes active by the MATCHm or MATCHm 1 signal TOUTnm 1 The signal becomes active by the M...

Page 177: ...n example Figure 15 1 1 shows the REMC2 configuration Table 15 1 1 REMC2 Channel Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 Number of channels 1 transmitter channel REMC2 Carrier signal generator Data signal generator DBCNT 15 0 CLKSRC 1 0 CLKDIV 3 0 Clock generator DBRUN MODEN DBLENBSY CLK_REMC2 REMO Interrupt control circuit CRPER 7 0 CRDTY 7 0 CARREN PRESET PRUN DBLEN 15 0 APLEN 15 0 ...

Page 178: ... SLEEP mode the REMC2 operating clock CLK_REMC2 must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_REMC2 clock source If the CLGOSC xxxxSLPC bit for the CLK_REMC2 clock source is 1 the CLK_REMC2 clock source is deacti vated during SLEEP mode and REMC2 stops with the register settings maintained at those before entering SLEEP mode After the CPU ret...

Page 179: ...rnal counters Set the REMDBCTL PRUN bit to 1 Start counting Continuous data transmission control The following shows a procedure to send data continuously after starting data transmission after Step 3 above 1 Set the duty and cycle for the subsequent data to the REMAPLEN APLEN 15 0 and REMDBLEN DBLEN 15 0 bits respectively before a compare DB interrupt REMINTF DBIF bit 1 occurs It is not necessary...

Page 180: ... frequency and duty ratio can be calculated by the equations shown below fCLK_REMC2 CRDTY 1 Carrier frequency Duty ratio Eq 15 1 CRPER 1 CRPER 1 Where fCLK_REMC2 CLK_REMC2 frequency Hz CRPER REMCARR CRPER 7 0 bit setting value 1 255 CRDTY REMCARR CRDTY 7 0 bit setting value 0 254 REMCARR CRDTY 7 0 bits REMCARR CRPER 7 0 bits The 8 bit counter for carrier generation is reset by the REMDBCTL PRESET ...

Page 181: ...EMAPLEN APLEN 15 0 bits REMDBLEN DBLEN 15 0 bits The 16 bit counter for data signal generation is reset by the REMDBCTL PRESET bit and is started stopped by the REMDBCTL PRUN bit When the counter value is matched with the REMAPLEN APLEN 15 0 bits compare AP the data signal waveform is inverted When the counter value is matched with the REMDBLEN DBLEN 15 0 bits compare DB the data signal waveform i...

Page 182: ...buffer and the 16 bit counter value is compared with the compare buffers The comparison values are loaded into the compare buffers when the 16 bit counter is matched with the REM DBLEN buffer when the count for the data length has completed Therefore the next transmit data can be set during the current data transmission When the compare buffers are enabled the buffer status flags REMINTF APLENBSY ...

Page 183: ...15 0 REMDBLEN DBLEN 15 0 REMCARR CRPER 7 0 REMCARR CRDTY 7 0 Figure 15 6 2 Example of Generated Drive Waveform The REMO and CLPLS signals are output from the respective pins while the REMDBCTL PRUN bit 1 The dif ference between the setting values of the REMDBLEN DBLEN 15 0 bits and REMAPLEN APLEN 15 0 bits becomes the CLPLS pulse width high period 15 7 Control Registers REMC2 Clock Control Registe...

Page 184: ... the REMDBCTL MODEN bit 0 REMC2 Data Bit Counter Control Register Register name Bit Bit name Initial Reset R W Remarks REMDBCTL 15 10 0x00 R 9 PRESET 0 H0 S0 R W Cleared by writing 1 to the REMDBCTL REMCRST bit 8 PRUN 0 H0 S0 R W 7 5 0x0 R 4 REMOINV 0 H0 R W 3 BUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W Bits 15 10 Reserved Bit 9 PRESET This bit resets the internal counters 16 ...

Page 185: ... mode 0 R W Repeat mode For more information refer to REMO Output Waveform Data signal Bit 1 REMCRST This bit issues software reset to the REMC2 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R Software reset has finished During normal operation Setting this bit resets the REMC2 internal counters and interrupt flags This bit is automatically cleared after the reset proc...

Page 186: ...r for data signal generation 0x0000 and ends when the counter exceeds the REMDBLEN DBLEN 15 0 bit setting value See Figure 15 4 3 3 Before this register can be rewritten the REMDBCTL MODEN bit must be set to 1 REMC2 Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks REMINTF 15 11 0x00 R 10 DBCNTRUN 0 H0 S0 R Cleared by writing 1 to the REMDBCTL REMCRST bit 9 DB...

Page 187: ... APIE These bits enable REMC2 interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt REMINTE DBIE bit Compare DB interrupt REMINTE APIE bit Compare AP interrupt REMC2 Carrier Waveform Register Register name Bit Bit name Initial Reset R W Remarks REMCARR 15 8 CRDTY 7 0 0x00 H0 R W 7 0 CRPER 7 0 0x00 H0 R W Bits 15 8 CRDTY 7 0...

Page 188: ...egister name Bit Bit name Initial Reset R W Remarks REMCCTL 15 8 0x00 R 7 1 0x00 R 0 CARREN 0 H0 R W Bits 15 1 Reserved Bit 0 CARREN This bit enables carrier modulation 1 R W Enable carrier modulation 0 R W Disable carrier modulation output data signal only Note When carrier modulation is disabled the REMDBCTL REMOINV bit should be set to 0 ...

Page 189: ... changing the common signal on time Allows software to select anode common or cathode common Allows software to configure the COM SEG pin status at off time specified level output Hi Z Can generate interrupts in the common signal cycles Figure 16 1 1 shows the LEDC configuration Table 16 1 1 LEDC Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 LED module supported Maximum of five digits of se...

Page 190: ...a b c d e f g dp S1C17 LEDC a g d dp b f c e Figure 16 2 2 1 Connections between LEDC and Seven Segment LED Modules The resistance value of R current limiting resistor should be determined after being evaluated using the actual tar get system 16 3 Clock Settings 16 3 1 LEDC Operating Clock When using LEDC the LEDC operating clock CLK_LEDC must be supplied to the LEDC from the clock generator The C...

Page 191: ...ch LED module each digit LICLKDIV 1 8 LP Eq 16 1 fCLK_LEDC LC LP NDIGITS 1 Eq 16 2 Where LP Lighting period of each COM digit s LC Lighting cycle of each COM digit s fCLK_LEDC LEDC operating clock frequency Hz LICLKDIV LEDCLPSET LICLKDIV 7 0 setting value 0 to 255 NDIGITS LEDCCTL NDIGITS 2 0 setting value 0 to 7 The maximum value depends on the model Example LEDCCLK CLKSRC 1 0 bits 0x2 OSC3 16 MHz...

Page 192: ...t using the LEDCCTL CMOFFMOD bit and the LEDCCTL SGOFFMOD bit respectively Table 16 4 3 1 Settings of Common Mode and Driver State at COM SEG Off Time LEDCCTL COMMOD bit LEDCCTL CMOFFMOD bit LEDCCTL SGOFFMOD bit Common mode Driver state at COM off time Driver state at SEG off time 1 1 1 Cathode common COM Hi Z SEG Hi Z 0 SEG L 0 1 COM H SEG Hi Z 0 SEG L 0 1 1 Anode common COM Hi Z SEG Hi Z 0 SEG H...

Page 193: ... a g d dp b f c e a g d dp b f c e a g d dp b f c e COM4 dp 0 g 0 f 0 e 0 d 0 c 1 b 1 a 0 COM3 dp 0 g 1 f 0 e 1 d 1 c 0 b 1 a 1 COM2 dp 1 g 1 f 0 e 0 d 1 c 1 b 1 a 1 COM1 dp 0 g 1 f 1 e 0 d 0 c 1 b 1 a 0 COM0 dp 0 g 1 f 1 e 0 d 1 c 1 b 0 a 1 Figure 16 4 6 1 Correspondence between Display Data and LED Segments 16 4 7 Drive Waveform Figure 16 4 7 1 shows a drive waveform example to display the patte...

Page 194: ...on 16 6 Control Registers LEDC Clock Control Register Register name Bit Bit name Initial Reset R W Remarks LEDCCLK 15 9 0x00 R 8 DBRUN 1 H0 R W 7 0 R 6 4 CLKDIV 2 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W Bits 15 9 Reserved Bit 8 DBRUN This bit sets whether the LEDC operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bit ...

Page 195: ...mation refer to Brightness Adjustment Bit 8 COMMOD This bit sets the common mode 1 R W Cathode common 0 R W Anode common Bits 7 6 Reserved Bit 5 SGOFFMOD This bit configures the driver state at the SEG off time 1 R W SEG pin Hi Z 0 R W SEG pin H anode common SEG pin L cathode common Bit 4 CMOFFMOD This bit configures the driver state at the COM off time 1 R W COM pin Hi Z 0 R W COM pin L anode com...

Page 196: ...occurred 1 W Clear flag 0 W Ineffective LEDC Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks LEDCINTE 15 8 0x00 R 7 1 0x00 R 0 COM0LTIE 0 H0 R W Bits 15 1 Reserved Bit 0 FRMIE This bit enables the COM0 lighting interrupt 1 R W Enable interrupt 0 R W Disable interrupt LEDC COMxy Data Registers Register name Bit Bit name Initial Reset R W Remarks LEDCDATxy 15 8 COMy 7 ...

Page 197: ...C12A Configuration of S1C17M12 M13 Item S1C17M12 S1C17M13 Number of channels 1 channel Ch 0 Number of analog signal inputs per channel Ch 0 8 inputs ADIN00 ADIN07 16 bit timer used as conversion clock and trigger sources Ch 0 16 bit timer Ch 3 VREFA pin external reference voltage input Available ADC12A Ch n Trigger select circuit Successive approximation control circuit CNVTRG 1 0 CNVMD MODEN ADST...

Page 198: ... converter Sensor 3 3 V Figure 17 2 2 1 Connections between ADC12A and External Devices 17 3 Clock Settings 17 3 1 ADC12A Operating Clock The 16 bit timer Ch k operating clock CLK_T16_k is also used as the ADC12A operating clock For more informa tion on the CLK_T16_k settings and clock supply in SLEEP and DEBUG modes refer to Clock Settings in the 16 bit Timers chapter Note When the CLK_T16_k supp...

Page 199: ... CNVMD bit Set conversion mode ADC12_nTRG STMD bit Set data storing mode ADC12_nTRG STAAIN 2 0 bits Set analog input pin to be A D converted first ADC12_nTRG ENDAIN 2 0 bits Set analog input pin to be A D converted last 5 Set the ADC12_nCFG VRANGE 1 0 bits Set operating voltage range according to VDD 6 Set the following bits when using the interrupt Write 1 to the interrupt flags in the ADC12_nINT...

Page 200: ...IF bit 1 analog input signal m A D conversion result overwrite error inter rupt clear the ADC12_nINTF ADmOVIF bit and terminate as an error or retry A D conversion 3 Read the A D conversion result of the analog input m ADC12_nADmD ADmD 15 0 bits The 12 bit conversion results are located at the low order 12 bits or high order 12 bits within the ADC12_ nADmD ADmD 15 0 bits according to the ADC12_nTR...

Page 201: ... 2 0 A D conversion operations ADC12_nAD2D AD2D 15 0 ADC12_nAD3D AD3D 15 0 ADC12_nAD4D AD4D 15 0 ADC12_nINTF AD2CIF ADC12_nINTF AD3CIF ADC12_nINTF AD4CIF ADINn2 ADINn2 Sampling A D converting Conversion ADINn3 ADINn3 Sampling Conversion ADINn4 ADINn4 Sampling Conversion Cleared Cleared Cleared ADINn2 conversion result 0x2 ADINn2 0x3 ADINn3 0x4 ADINn4 0x5 ADINn5 ADINn3 conversion result ADINn4 conv...

Page 202: ...e interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter 17 6 Control Registers ADC12A Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks ADC12_nCTL 15 0 R 14 12 ADSTAT 2 0 0x0 H0 R 11 0 R 10 BSYSTAT 0 H0 R 9 8 0x0 R 7 2 0x00 ...

Page 203: ...n Bit 0 MODEN This bit enables the ADC12A operations 1 R W Enable ADC12A operations The operating clock is supplied 0 R W Disable ADC12A operations The operating clock is stopped Note After 0 is written to the ADC12_nCTL MODEN bit the ADC12A executes a terminate processing Before the clock source is deactivated read the ADC12_nCTL MODEN bit to make sure that it is set to 0 ADC12A Ch n Trigger Anal...

Page 204: ...uous conversion mode 0 R W One time conversion mode Bits 5 4 CNVTRG 1 0 These bits select a trigger source to start A D conversion Table 17 6 2 Trigger Source Selection ADC12_nTRG CNVTRG 1 0 bits Trigger source 0x3 ADTRGn pin external trigger 0x2 Reserved 0x1 16 bit timer Ch k underflow 0x0 ADC12_nCTL ADST bit software trigger Bit 3 Reserved Bits 2 0 SMPCLK 2 0 These bits set the analog input sign...

Page 205: ... Register name Bit Bit name Initial Reset R W Remarks ADC12_nINTF 15 AD7OVIF 0 H0 R W Cleared by writing 1 14 AD6OVIF 0 H0 R W 13 AD5OVIF 0 H0 R W 12 AD4OVIF 0 H0 R W 11 AD3OVIF 0 H0 R W 10 AD2OVIF 0 H0 R W 9 AD1OVIF 0 H0 R W 8 AD0OVIF 0 H0 R W 7 AD7CIF 0 H0 R W 6 AD6CIF 0 H0 R W 5 AD5CIF 0 H0 R W 4 AD4CIF 0 H0 R W 3 AD3CIF 0 H0 R W 2 AD2CIF 0 H0 R W 1 AD1CIF 0 H0 R W 0 AD0CIF 0 H0 R W Bits 15 8 A...

Page 206: ...E 0 H0 R W 2 AD2CIE 0 H0 R W 1 AD1CIE 0 H0 R W 0 AD0CIE 0 H0 R W Bits 15 8 ADmOVIE Bits 7 0 ADmCIE These bits enable ADC12A interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt ADC12_nINTE ADmOVIE bit Analog input signal m A D conversion result overwrite error interrupt ADC12_nINTE ADmCIE bit Analog input signal m A D conv...

Page 207: ... 0 Operation result register 1 Mode setting Selector Argument 2 Argument 1 Coprocessor output Flag output Operation result COPRO2 Figure 18 1 1 COPRO2 Configuration 18 2 Operation Mode and Output Mode COPRO2 operates according to the operation mode specified by the application program As listed in Table 18 2 1 COPRO2 supports 11 operations The multiplication division and MAC results are 32 bit dat...

Page 208: ...hout computation 0x4 0x7 Reserved 0x4 Unsigned multiplication mode Performs unsigned multiplication 0x5 Signed multiplication mode Performs signed multiplication 0x6 Unsigned MAC mode Performs unsigned MAC operation 0x7 Signed MAC mode Performs signed MAC operation 0x8 Unsigned division mode Performs unsigned division 0x9 Signed division mode Performs signed division 0xa Initialize mode 3 Loads th...

Page 209: ...ng shows a procedure to perform a division 1 Set the mode to 0x02 initialize mode 2 2 Set the 32 bit dividend B to the operation result register 0 using a ld cf instruction 3 Set the mode to 0x08 unsigned division 16 low order bits output mode 0 or 0x09 signed division 16 low order bits output mode 0 4 Send the 32 bit divisor C to COPRO2 using a ld ca instruction 5 Read the one half result 16 low ...

Page 210: ...ent psr CVZN 0b0000 The operation result regis ters 0 and 1 keep the op eration results until they are rewritten by other opera tion COPRO2 does not support 0 0 division ext imm9 ld ca rd imm7 res0 31 0 rd imm7 16 res0 31 0 Quotient res1 31 0 Remainder rd res0 15 0 Quotient 0x18 or 0x19 ld ca rd rs res0 31 0 rd rs res0 31 0 Quotient res1 31 0 Remainder rd res0 31 16 Quotient ext imm9 ld ca rd imm7...

Page 211: ...ts A 32 bits The following shows a procedure to perform a MAC operation 1 Set the initial value A to the operation result register 0 To clear the operation result registers A 0 Set the mode to 0x00 initialize mode 0 It is not necessary to send 0x00 to COPRO2 with another instruc tion To load a 16 bit value to the operation result register 0 Set the operation mode to 0x01 initialize mode 1 and then...

Page 212: ...ng value Instruction Operations Flags Remarks 0x06 or 0x07 ld ca rd rs res0 31 0 rd rs res0 31 0 rd res0 15 0 psr CVZN 0b0100 if an overflow has oc curred Otherwise psr CVZN 0b0000 The operation result register 0 keeps the operation result until it is rewritten by other operation Overflow can be de tected only in signed MAC mode it does not occur in unsigned MAC mode ext imm9 ld ca rd imm7 res0 31...

Page 213: ...r when the ld ca or ld cf instruction is executed in an operation mode other than operation result read mode 18 6 Reading Operation Results The ld ca instruction cannot load a 32 bit operation result to a CPU register so a multiplication division or MAC operation returns the one half 16 bits according to the output mode result A 15 0 or A 31 16 and the flag status to the CPU registers Another one ...

Page 214: ...gramming 2 4 5 5 V VDD2 1 8 5 5 V Flash programming voltage VPP 7 3 7 5 7 7 V OSC3 oscillator oscillation frequency fOSC3 Crystal ceramic oscillator 1 16 8 MHz EXOSC external clock frequency fEXOSC When supplied from an external oscillator 0 016 16 8 MHz Bypass capacitor between VSS and VDD CPW1 3 3 µF Bypass capacitor between VSS2 and VDD2 CPW2 3 3 µF Capacitor between VSS and VD1 CPW3 1 µF Gate ...

Page 215: ... bits 0x2 CLGOSC3 OSC3INV 1 0 bits 0x0 CG3 CD3 100 pF ceramic resonator CSBLA_J manufactured by Murata Manufacturing Co Ltd 1 MHz 2 OSC3 oscillator CLGOSC3 OSC3MD 1 0 bits 0x0 CLGOSC3 OSC3FQ 1 0 bits 0x3 3 The current consumption values were measured when a test program consisting of 60 5 ALU instructions 17 branch instruc tions 12 RAM read instructions and 10 5 RAM write instructions was executed...

Page 216: ...Typ Max Unit High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV Input pull up resistance RIN 100 230 500 kW Pin capacitance CIN 15 pF Reset Low pulse width tSR 5 µs RESET tSR VT VT POR BOR characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS VSS2 0 V Ta 40 to 85 C Item...

Page 217: ...ion Ta Min Typ Max Unit Internal oscillator oscillation start time tsta3I CLGOSC3 OSC3MD 1 0 bits 0x0 3 µs Internal oscillator oscillation frequency fOSC3I CLGOSC3 OSC3MD 1 0 bits 0x0 CLGOSC3 OSC3FQ 1 0 bits 0x3 25 C 15 76 16 00 16 25 MHz 10 to 60 C 15 68 16 00 16 32 MHz 40 to 85 C 15 60 16 00 16 40 MHz CLGOSC3 OSC3MD 1 0 bits 0x0 CLGOSC3 OSC3FQ 1 0 bits 0x2 25 C 11 73 12 10 12 47 MHz 40 to 85 C 1...

Page 218: ...tics programming count 2 Assumed that Erasing Programming as count of 1 The count includes programming in the factory for shipment with ROM data programmed 19 7 Input Output Port PPORT Characteristics Unless otherwise specified VDD VDD2 1 8 to 5 5 V VSS VSS2 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit High level Schmitt input threshold voltage VT P00 07 P10 17 P20 24 P40 47 PD0 D1 PD3...

Page 219: ... 4 0 6 0 8 1 0 0 1 0 3 0 5 0 7 0 9 VDD VOH V I OH1 mA VDD 1 8 V VDD 3 6 V VDD 5 5 V 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 10 8 6 4 2 0 I OL1 mA VOL V VDD 5 5 V VDD 3 6 V VDD 1 8 V High level output current characteristic Low level output current characteristic P50 54 P50 54 Ta 85 C Max value Ta 85 C Min value 0 0 0 10 20 30 40 50 60 0 2 0 4 0 6 0 8 1 0 0 1 0 3 0 5 0 7 0 9 VDD2 VOH V I OH2 mA...

Page 220: ...SVDC 4 0 bits 0x1a 963 1 041 1 119 kW SVDCTL SVDC 4 0 bits 0x1b 982 1 063 1 145 kW SVDCTL SVDC 4 0 bits 0x1c 1 001 1 086 1 171 kW SVDCTL SVDC 4 0 bits 0x1d 1 022 1 110 1 198 kW SVDCTL SVDC 4 0 bits 0x1e 1 054 1 129 1 204 kW SVDCTL SVDC 4 0 bits 0x1f 1 072 1 154 1 237 kW EXSVD detection voltage VSVD_EXT SVDCTL SVDC 4 0 bits 0x0 1 17 1 2 1 23 V SVDCTL SVDC 4 0 bits 0x1 1 27 1 3 1 33 V SVDCTL SVDC 4 ...

Page 221: ...TL SVDC 4 0 bits 0x16 3 90 4 0 4 10 V SVDCTL SVDC 4 0 bits 0x17 4 00 4 1 4 20 V SVDCTL SVDC 4 0 bits 0x18 4 10 4 2 4 31 V SVDCTL SVDC 4 0 bits 0x19 4 19 4 3 4 41 V SVDCTL SVDC 4 0 bits 0x1a 4 39 4 5 4 61 V SVDCTL SVDC 4 0 bits 0x1b 4 49 4 6 4 72 V SVDCTL SVDC 4 0 bits 0x1c 4 58 4 7 4 82 V SVDCTL SVDC 4 0 bits 0x1d 4 68 4 8 4 92 V SVDCTL SVDC 4 0 bits 0x1e 4 78 4 9 5 02 V SVDCTL SVDC 4 0 bits 0x1f ...

Page 222: ...wise specified VDD 1 8 to 5 5 V VSS VSS2 0 V Ta 40 to 85 C Item Symbol Condition VDD Min Typ Max Unit SPICLKn cycle time tSCYC 4 5 to 5 5 V 250 ns 1 8 to 4 5 V 500 ns SPICLKn High pulse width tSCKH 4 5 to 5 5 V 100 ns 1 8 to 4 5 V 200 ns SPICLKn Low pulse width tSCKL 4 5 to 5 5 V 100 ns 1 8 to 4 5 V 200 ns SDIn setup time tSDS 4 5 to 5 5 V 50 ns 1 8 to 4 5 V 80 ns SDIn hold time tSDH 4 5 to 5 5 V ...

Page 223: ... START condition tHD STA 4 0 0 6 µs SCLn Low pulse width tLOW 4 7 1 3 µs SCLn High pulse width tHIGH 4 0 0 6 µs Repeated START condition setup time tSU STA 4 7 0 6 µs Data hold time tHD DAT 0 0 µs Data setup time tSU DAT 250 100 ns SDAn SCLn rise time tr 1 000 300 ns SDAn SCLn fall time tf 300 300 ns STOP condition setup time tSU STO 4 0 0 6 µs Bus free time tBUF 4 7 1 3 µs After this period the f...

Page 224: ... input capacitance CADIN 30 pF A D converter circuit current IADC ADC12_nCFG VRANGE 1 0 bits 0x3 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 3 6 V 380 670 µA ADC12_nCFG VRANGE 1 0 bits 0x2 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 4 8 V 230 390 µA ADC12_nCFG VRANGE 1 0 bits 0x1 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 5 5 V 210 350 µA 1 The Max value is the value when the A D conversion cl...

Page 225: ...C3 crystal ceramic oscillator is selected 3 Available only in the S1C17M13 Do not mount components if unnecessary Sample external components Symbol Name Recommended components X tal3 Crystal resonator CA 301 4 MHz manufactured by Seiko Epson Corporation Ceramic Ceramic resonator CSBLA_J 1 MHz manufactured by Murata Manufacturing Co Ltd CG3 OSC3 gate capacitor Ceramic capacitor CD3 OSC3 drain capac...

Page 226: ...iko Epson Corporation 21 1 Rev 1 2 21 Package TQFP12 48PIN P TQFP048 0707 0 50 Unit mm 7 9 25 36 7 9 13 24 INDEX 0 17min 0 27max 12 1 48 37 1 0 1 1 2 max 1 0 3min 0 7max 0 min 10 max 0 09min 0 2max 0 5 Figure 21 1 QFP12 48PIN Package Dimensions ...

Page 227: ...R 23 16 0x00 H0 R WP 0x4008 MSCPSR MISC PSR Register 15 8 0x00 R 7 5 PSRIL 2 0 0x0 H0 R 4 PSRIE 0 H0 R 3 PSRC 0 H0 R 2 PSRV 0 H0 R 1 PSRZ 0 H0 R 0 PSRN 0 H0 R 0x4020 Power Generator PWG Address Register name Bit Bit name Initial Reset R W Remarks 0x4020 PWGVD1CTL PWG VD1 Regulator Control Register 15 8 0x00 R 7 2 0x00 R 1 0 REGMODE 1 0 0x0 H0 R WP 0x4040 0x4050 Clock Generator CLG Address Register...

Page 228: ...emarks 0x4080 ITCLV0 ITC Interrupt Level Setup Register 0 15 11 0x00 R 10 8 ILV1 2 0 0x0 H0 R W Port interrupt ILVPPORT 7 3 0x00 R 2 0 ILV0 2 0 0x0 H0 R W Supply voltage detector interrupt ILVSVD3 0x4082 ITCLV1 ITC Interrupt Level Setup Register 1 15 11 0x00 R 10 8 ILV3 2 0 0x0 H0 R W Clock generator interrupt ILVCLG 7 0 0x00 R 0x4084 ITCLV2 ITC Interrupt Level Setup Register 2 15 11 0x00 R 10 8 I...

Page 229: ...W Remarks 0x40a0 WDTCLK WDT2 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP 0x40a2 WDTCTL WDT2 Control Register 15 11 0x00 R 10 9 MOD 1 0 0x0 H0 R WP 8 STATNMI 0 H0 R 7 5 0x0 R 4 WDTCNTRST 0 H0 WP Always read as 0 3 0 WDTRUN 3 0 0xa H0 R WP 0x40a4 WDTCMP WDT2 Counter Com pare Match Register 15 10 0x00 R 9 0 CMP 9 0 0x3...

Page 230: ... 15 0 0xffff H0 R 0x416a T16_0INTF T16 Ch 0 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x416c T16_0INTE T16 Ch 0 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x41b0 Flash Controller FLASHC Address Register name Bit Bit name Initial Reset R W Remarks 0x41b0 FLASHCWAIT FLASHC Flash Read Cycle Register 15 9 0x00 R 8 reserved 0 H0 R WP Alway...

Page 231: ...0x4216 P1INTF P1 Port Interrupt Flag Register 15 8 0x00 R 7 0 P1IF 7 0 0x00 H0 R W Cleared by writing 1 0x4218 P1INTCTL P1 Port Interrupt Control Register 15 8 P1EDGE 7 0 0x00 H0 R W 7 0 P1IE 7 0 0x00 H0 R W 0x421a P1CHATEN P1 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P1CHATEN 7 0 0x00 H0 R W 0x421c P1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 0 P1SEL 7 0 0x00 H0 R W 0x421e P1F...

Page 232: ...TL P4 Port Pull up down Control Register 15 8 P4PDPU 7 0 0x00 H0 R W 7 0 P4REN 7 0 0x00 H0 R W 0x4246 P4INTF P4 Port Interrupt Flag Register 15 8 0x00 R 7 0 P4IF 7 0 0x00 H0 R W Cleared by writing 1 0x4248 P4INTCTL P4 Port Interrupt Control Register 15 8 P4EDGE 7 0 0x00 H0 R W 7 0 P4IE 7 0 0x00 H0 R W 0x424a P4CHATEN P4 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P4CHATEN 7 0 0x00 H0 R ...

Page 233: ... 0x0 H0 R W 1 0 P50MUX 1 0 0x0 H0 R W 0x42d0 PDDAT Pd Port Data Register 15 13 0x0 R 12 8 PDOUT 4 0 0x00 H0 R W 7 5 0x0 R 4 3 PDIN 4 3 x H0 R 2 0 R 1 0 PDIN 1 0 x H0 R 0x42d2 PDIOEN Pd Port Enable Register 15 13 0x0 R 12 11 PDIEN 4 3 0x0 H0 R W 10 reserved 0 H0 R W 9 8 PDIEN 1 0 0x0 H0 R W 7 5 0x0 R 4 0 PDOEN 4 0 0x00 H0 R W 0x42d4 PDRCTL Pd Port Pull up down Control Register 15 13 0x0 R 12 11 PDP...

Page 234: ...plexer Setting Register 15 13 P05PPFNC 2 0 0x0 H0 R W 12 11 P05PERICH 1 0 0x0 H0 R W 10 8 P05PERISEL 2 0 0x0 H0 R W 7 5 P04PPFNC 2 0 0x0 H0 R W 4 3 P04PERICH 1 0 0x0 H0 R W 2 0 P04PERISEL 2 0 0x0 H0 R W 0x4306 P0UPMUX3 P06 07 Universal Port Multiplexer Setting Register 15 13 P07PPFNC 2 0 0x0 H0 R W 12 11 P07PERICH 1 0 0x0 H0 R W 10 8 P07PERISEL 2 0 0x0 H0 R W 7 5 P06PPFNC 2 0 0x0 H0 R W 4 3 P06PER...

Page 235: ...W 7 5 P22PPFNC 2 0 0x0 H0 R W 4 3 P22PERICH 1 0 0x0 H0 R W 2 0 P22PERISEL 2 0 0x0 H0 R W 0x4314 P2UPMUX2 P24 Universal Port Multiplexer Setting Register 15 8 0x00 R 7 5 P24PPFNC 2 0 0x0 H0 R W 4 3 P24PERICH 1 0 0x0 H0 R W 2 0 P24PERISEL 2 0 0x0 H0 R W 0x4380 0x4390 UART UART3 Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x4380 UA0CLK UART3 Ch 0 Clock Control Register 15 9 0x00...

Page 236: ...0 H0 R W 5 FEIE 0 H0 R W 4 PEIE 0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x4390 UA0CAWF UART3 Ch 0 Carrier Waveform Register 15 8 0x00 R 7 0 CRPER 7 0 0x00 H0 R W 0x43a0 0x43ac 16 bit Timer T16 Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x43a0 T16_1CLK T16 Ch 1 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W ...

Page 237: ...PIA Ch 0 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPI0RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPI0TXD register 0x43ba SPI0INTE SPIA Ch 0 Interrupt Enable Register 15 8 0x00 R 7 4 0x0 R 3 OEIE 0 H0 R W 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x43c0 0x4...

Page 238: ... 0 H0 S0 R W Cleared by writing 1 6 GCIF 0 H0 S0 R W 5 NACKIF 0 H0 S0 R W 4 STOPIF 0 H0 S0 R W 3 STARTIF 0 H0 S0 R W 2 ERRIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the I2C0RXD register 0 TBEIF 0 H0 S0 R Cleared by writing to the I2C0TXD register 0x43d2 I2C0INTE I2C Ch 0 Interrupt Enable Register 15 8 0x00 R 7 BYTEENDIE 0 H0 R W 6 GCIE 0 H0 R W 5 NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTI...

Page 239: ...x500c T16B0INTE T16B Ch 0 Interrupt Enable Register 15 8 0x00 R 7 6 0x0 R 5 CAPOW1IE 0 H0 R W 4 CMPCAP1IE 0 H0 R W 3 CAPOW0IE 0 H0 R W 2 CMPCAP0IE 0 H0 R W 1 CNTMAXIE 0 H0 R W 0 CNTZEROIE 0 H0 R W 0x5010 T16B0CCCTL0 T16B Ch 0 Compare Capture 0 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4...

Page 240: ...R W 0x5268 T16_2TC T16 Ch 2 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x526a T16_2INTF T16 Ch 2 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x526c T16_2INTE T16 Ch 2 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x5270 0x527a Synchronous Serial Interface SPIA Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x5270 SPI...

Page 241: ... R 9 PRESET 0 H0 S0 R W Cleared by writing 1 to the REMDBCTL REMCRST bit 8 PRUN 0 H0 S0 R W 7 5 0x0 R 4 REMOINV 0 H0 R W 3 BUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W 0x5324 REMDBCNT REMC2 Data Bit Counter Register 15 0 DBCNT 15 0 0x0000 H0 S0 R Cleared by writing 1 to the REMDBCTL REMCRST bit 0x5326 REMAPLEN REMC2 Data Bit Active Pulse Length Register 15 0 APLEN 15 0 0x0000 H...

Page 242: ...x0 R １ DSPON 0 H0 R W 0 MODEN 0 H0 R W 0x5404 LEDCLPSET LEDC Lighting Pe riod Setting Register 15 8 0x00 R 7 0 LICLKDIV 7 0 0xff H0 R W 0x5406 LEDCINTF LEDC Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 CM0LTIF 0 H0 R W Cleared by writing 1 0x5408 LEDCINTE LEDC Interrupt En able Register 15 8 0x00 R 7 1 0x00 R 0 CM0LTIE 0 H0 R W 0x5410 LEDCDAT10 LEDC COM1 0 Data Register 15 8 COM1 7 0 0x00 H0 R...

Page 243: ...name Bit Bit name Initial Reset R W Remarks 0x54a2 ADC12_0CTL ADC12A Ch 0 Control Register 15 0 R 14 12 ADSTAT 2 0 0x0 H0 R 11 0 R 10 BSYSTAT 0 H0 R 9 8 0x0 R 7 2 0x00 R 1 ADST 0 H0 R W 0 MODEN 0 H0 R W 0x54a4 ADC12_0TRG ADC12A Ch 0 Trigger Analog Input Select Register 15 14 0x0 R 13 11 ENDAIN 2 0 0x0 H0 R W 10 8 STAAIN 2 0 0x0 H0 R W 7 STMD 0 H0 R W 6 CNVMD 0 H0 R W 5 4 CNVTRG 1 0 0x0 H0 R W 3 0 ...

Page 244: ...0AD0D ADC12A Ch 0 Result Register 0 15 0 AD0D 15 0 0x0000 H0 R 0x54ae ADC12_0AD1D ADC12A Ch 0 Result Register 1 15 0 AD1D 15 0 0x0000 H0 R 0x54b0 ADC12_0AD2D ADC12A Ch 0 Result Register 2 15 0 AD2D 15 0 0x0000 H0 R 0x54b2 ADC12_0AD3D ADC12A Ch 0 Result Register 3 15 0 AD3D 15 0 0x0000 H0 R 0x54b4 ADC12_0AD4D ADC12A Ch 0 Result Register 4 15 0 AD4D 15 0 0x0000 H0 R 0x54b6 ADC12_0AD5D ADC12A Ch 0 Re...

Page 245: ...teristics Set the PWGVD1CTL REGMODE 1 0 bits to 0x3 economy mode or 0x0 automatic mode before executing the slp instruction CLGOSC IOSCSLPC OSC3SLPC EXOSCSLPC bits of the clock generator Setting the CLGOSC IOSCSLPC OSC3SLPC or EXOSCSLPC bit of the clock generator to 0 disables the oscillator circuit stop control when the slp instruction is executed To stop the oscillator circuits during SLEEP mode...

Page 246: ...2 Other Power Saving Methods Supply voltage detector configuration Continuous operation mode SVDCTL SVDMD 1 0 bits 0x0 always detects the power supply voltage therefore it increases current consumption Set the supply voltage detector to intermittent operation mode or turn it on only when required ...

Page 247: ...hield the area at least 5 mm around the above pins and wiring Even after implementing these precautions avoid configuring digital signal lines in parallel as described in 2 above Avoid crossing even on discrete layers except for lines carrying signals with low switching frequencies 4 After implementing these precautions check the FOUT pin output clock waveform by running the actual application pro...

Page 248: ...he product is subjected to heat stress exceeding regular reflow conditions during mounting processes Unused pins 1 I O port P pins Unused pins should be left open The control registers should be fixed at the initial status 2 OSC3 OSC4 and EXOSC pins If the OSC3 crystal ceramic oscillator circuit or EXOSC input circuit is not used the pin should be config ured as a general purpose I O port The cont...

Page 249: ...BUG mode To prevent unexpected transitions to DEBUG mode caused by extraneous noise switch the DCLK DST2 and DSIO pins to general purpose I O port pins within the initialization routine when the debug functions are not used For details of the pin functions and the function switch control see the I O Ports chapter Note Do not perform the function switching shown above when the application is under ...

Page 250: ...b 0x2c T16 ch1 long spia_0_handler 0x0c 0x30 SPIA ch0 long i2c_0_handler 0x0d 0x34 I2C ch0 long t16b_0_handler 0x0e 0x38 T16B ch0 long t16_2_handler 0x0f 0x3c T16 ch2 long t16_3_handler 0x10 0x40 T16 ch3 long remc2_handler 0x11 0x44 REMC2 long adc12a_0_handler 0x12 0x48 ADC12A long ledc_handler 0x13 0x4c LEDC long spia_1_handler 0x14 0x50 SPIA ch1 long int15_handler 0x15 0x54 long int16_handler 0x...

Page 251: ...I nmi_handler 1 A rodata section is declared to locate the vector table in the vector section 2 Interrupt handler routine addresses are defined as vectors intXX_handler can be used for software interrupts 3 The program code is written in the text section 4 Sets the stack pointer 5 Sets the number of Flash memory read cycles See the Memory and Bus chapter ...

Page 252: ...ximum Ratings Modified the characteristics table VI RESET was added to the condition 19 1 19 2 Recommended Operating Conditions Added VSS VSS2 0 V 1 and the following annotations 1 The potential variation of the VSS voltage should be suppressed to within 0 3 V on the basis of the ground potential of the MCU mounting board while the Flash is being programmed as it affects the Flash memory character...

Page 253: ...21 5330 4888 Fax 86 21 5423 4677 Shenzhen Branch Room 804 805 8 Floor Tower 2 Ali Center No 3331 Keyuan South RD Shenzhen bay Nanshan District Shenzhen 518054 China Phone 86 755 3299 0588 Fax 86 755 3299 0560 Epson Taiwan Technology Trading Ltd 15F No 100 Songren Rd Sinyi Dist Taipei City 110 Taiwan Phone 886 2 8786 6688 Epson Singapore Pte Ltd 438B Alexandra Road Block B Alexandra TechnoPark 04 0...

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Summary of Contents for S1C17M12

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