Epson FX-1050+, Technical Manual

Page: 192 / 225

REV.-A
●
CPU Timing
Refer to Figures A-3
through
A-5 for CPU timing diagrams.
Three oscillations define one state. The OP code fetch requires four states; during TI to program
memory is read; instructions are interpreted during Address bus lines 15-8 are output from to
Address but lines 7-O are used in the multiplex mode; the address is latched during T1 at
the ALE signal. Since the memory addressed is enabled after disengaging the driver is output
from fetched at and processed internally at The ALE and RD signals are executed from
the OP code fetch for these two signals is performed at The WR signal is output from the
middle of T 1 to the beginning of The address and ALE timing is the same as that for memory read;
however following address output are not disabled, and write data is output at
at the beginning of and the end of
NOTE: When are set to the multiplexed address/data-bus to the address bus
the and WR signals in the machine cycle are HIGH when memory is not being accessed.
CLOCK
ALE
/
-8
-O)
Y
ADDRESS
x
-o
-O)
x
A D D R E S S - - - <
OP CODE
Figure A-3. OP Code Fetch Timing
T1 T2 T3
CLOCK
AB15 -8
ADDRESS
-o
-O)
A D D R E S S --<
READ DATA
Figure A-4. Memory Read Timing
CLOCK
AB15 -8
-0)
x
ADDRESS
-0
-0)
ADDRESS
x
x
WRITE DATA
Figure A-5. Memory Write Timing
A-6