2: Programmer’s Model
2-10
EPSON
ARM720T CORE CPU MANUAL
2.8
Exceptions
Exceptions arise whenever the normal flow of a program has to be halted temporarily, for
example to service an interrupt from a peripheral. Before an exception can be handled, the
current processor state is preserved so that the original program can resume when the handler
routine has finished.
Several exceptions can arise at the same time. If this happens, they are dealt with in a fixed
Exception behavior is described in the following sections:
•
Action on entering an exception
•
Action on leaving an exception
•
Exception entry and exit summary
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2.8.1
Action on entering an exception
When handling an exception, the ARM720T processor behaves as follows:
1
It preserves the address of the next instruction in the appropriate LR.
a.
If the exception has been entered from ARM state, the address of the next
instruction is copied into the LR (that is, current PC+4 or PC+8 depending on
the exception). See Table 2-3 on page 2-11 for details).
b.
If the exception has been entered from Thumb state, the value written into the
LR is the current PC, offset by a value so that the program resumes from the
correct place on return from the exception. This means that the exception
handler does not have to determine which state the exception was entered
from.
For example, in the case of SWI:
MOVS PC, r14_svc
always returns to the next instruction regardless of whether the SWI was executed
in ARM or Thumb state.
2
It copies the CPSR into the appropriate SPSR.
3
It forces the CPSR mode bits to a value that depends on the exception.
4
It forces the PC to fetch the next instruction from the relevant exception vector.
It can also set the interrupt disable flags to prevent otherwise unmanageable nestings of
exceptions.
If the processor is in Thumb state when an exception occurs, it automatically switches into
ARM state when the PC is loaded with the exception vector address.
Summary of Contents for ARM720T Core cpu
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Page 13: ...Preface ...
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Page 19: ...1 Introduction ...
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Page 39: ...2 Programmer s Model ...
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Page 59: ...3 Configuration ...
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Page 71: ...4 Instruction and Data Cache ...
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Page 75: ...5 Write Buffer ...
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Page 119: ...8 Coprocessor Interface ...
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Page 131: ...9 Debugging Your System ...
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Page 199: ...Appendix A Signal Descriptions ...
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Page 209: ...Glossary ...
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