A: Signal Descriptions
ARM720T CORE CPU MANUAL
EPSON
A-7
A.6
ATPG test signals
ATPG test signals used by the ARM720T processor are shown in Table A-6.
A.7
Miscellaneous signals
Miscellaneous signals used by the ARM720T processor are shown in Table A-7.
Table A-6 ATPG test signal descriptions
Name
Type
Description
TESTENABLE
Input
This signal ensures the clocks are free-running during scan
test.
TESTENABLE
must be:
•
tied HIGH throughout the duration of scan testing
•
tied LOW during functional mode.
SCANENABLE
Input
This signal enables serial shifting of vectors through the scan
chains. You must control this signal using the I/O pins. It must
be tied LOW during functional mode.
SCANIN0
-
SCANIN6
Inputs
Processor core scan chain inputs.
SCANOUT0
-
SCANOUT6
Outputs
Processor core scan chain outputs.
HCLK
Input
System clock. All signals are related to the rising edge of
HCLK
.
HCLKEN
Input
Synchronous enable for AHB transfers. When HIGH,
indicates that the next rising edge of
HCLK
is also a rising
edge for the AHB system that the ARM720T processor is
embedded in. Must be tied HIGH in systems where the AMBA
bus and the core are intended to be the same frequency.
DBGTCKEN
Input
Synchronous enable for debug logic. Must be tied HIGH
during scan test.
HRESETn
Input
This is the active LOW reset signal for the system and bus.
DBGnTRST
Input
This is the active LOW reset signal for the internal state. This
signal is a level-sensitive asynchronous reset input.
Table A-7 Miscellaneous signal descriptions
Name
Type
Description
BIGENDOUT
Output Big-endian
format.
When this signal is HIGH, the processor treats bytes in memory as being in
big-endian format. When it is LOW, memory is treated as little-endian.
nFIQ
Input
ARM fast interrupt request signal.
nIRQ
Input
ARM interrupt request signal.
VINITHI
Input
Determines the state of the V bit in CP15 register c1 at reset. When HIGH, the
V bit is set coming out of rest. When LOW, the V bit is clear coming out of
reset.
Summary of Contents for ARM720T Core cpu
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Page 13: ...Preface ...
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Page 19: ...1 Introduction ...
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Page 39: ...2 Programmer s Model ...
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Page 59: ...3 Configuration ...
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Page 71: ...4 Instruction and Data Cache ...
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Page 75: ...5 Write Buffer ...
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Page 79: ...6 The Bus Interface ...
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Page 95: ...7 Memory Management Unit ...
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Page 119: ...8 Coprocessor Interface ...
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Page 131: ...9 Debugging Your System ...
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Page 177: ...10 ETM Interface ...
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Page 183: ...11 Test Support ...
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Page 199: ...Appendix A Signal Descriptions ...
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Page 209: ...Glossary ...
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Page 217: ...Index ...
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