
4-6 CHAPTER 4
4-3 CHIPSET FEATURES SETUP
Choose the "
CHIPSET FEATURES SETUP
" in the
CMOS SETUP UTILITY
menu to display following menu.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Figure 4-4 CHIPSET FEATURES SETUP
C8000 - CBFFF Shadow :
CC000 - CFFFF Shadow:
D0000 - D3FFF Shadow:
D4000 - D7FFF Shadow:
D8000 - DBFFF Shadow:
DC000 - DFFFF Shadow:
These categories determine whether optional ROM will be copied to RAM by 16K
byte or 32K byte per/unit and the size depends on chipset.
Enabled
:
Optional shadow is enabled.
Disabled
:
Optional shadow is disabled.
Auto Configuration:
This Category allows you to set the DRAM timing. The
default value is Enabled. When disabled this field. You can select the different
DRAM's timing that supports by chipset below item.
Note:
When you insert slower memery modules in the system and set a faster
timing. Maybe the system will hang up.
Esc : Quit : Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F7 : Load Setup Defaults
F6 : Load Bios Defaults
Auto Configuration
: Enabled
8 Bit I/O Recovery Time
: 1
16 Bit I/O Recovery Time
: 1
DRAM Speed Selection
: 60ns
Memory Hole AT 15M-16M
: Disabled
DRAM RAS# Precharge Time
: 3
MA Additional Wait state
: Disabled
RAS# To Cas# Delay
: Enabled
DAM Read Burst (B/E/F)
: 2/2/3
DRAM Write Burst (B/E/F)
: 2/2/3
ISA Bus Clock
: PCICLK/4
DRAM Refresh Queue
: Enabled
DRAM RAS Only Refresh
: Disabled
ECC Checking / Generation
: Enabled
Fast Dram Refresh
: Disabled
Read-Around-Write
: Enabled
PCI Burst Write Combine
: Enabled
PCI-To-DRAM Pipeline
: Enabled
CPU-To-PCI Write Post
: Disabled
CPU-To-PCI IDE Posting
: Enabled
System BIOS Cacheable
: Enabled
Video RAM Cacheable
: Disabled