
BIOS
Page 4-11
PCI1/2 Master 0 WS Write
When Enabled, Writes to the PCI bus are commanded with zero wait states.
Options: Enabled, Disabled.
PCI1/2 Post Write
Enables CPU to PCI bus POST write.
Options: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.2.
Options: Enabled, Disabled.
4-4 Integrated Peripherals
Figure 5: Integrated Peripherals
OnChip SATA Boot ROM / Silicon Image Boot ROM
(Optional)
/ OnChip Lan Boot
ROM / Marvell Lan Boot ROM
(Optional)
Enables/disable the onboard SATA/Silicon Image/LAN Boot LAN.
Options: Enabled, Disabled.
Summary of Contents for EP-8HDA5I
Page 6: ...vi Page Left Blank...
Page 11: ...Introduction Page 1 5 1 3 System Block Diagram...
Page 12: ...Introduction Page 1 6...
Page 32: ...Installation Page 3 16...
Page 60: ...BIOS Page 4 28...