EPOX EP-3S1A, User Manual

Page: 44 / 84

BIOS EP-3S1A
Page 4-12
CPU Latency Timer
Enabled: The processor cycle will be deferred immediately after the GMCH
receives another ADS#.
Disabled: The processor cycle will only be deferred after for 31 clocks and
another ADS# has arrived.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transac-
tions cycles. Select
Enabled to support compliance with PCI specification
version 2.1.
The Choice: Enabled, Disabled.
On-Chip Video Window Size
The amount of system memory that the 815 series AGP is allowed to share. The
default is 64.
32: 32MB of systems memory accessable by the 815 series AGP.
64: 64MB of systems memory accessable by the 815 series AGP.
AGP Graphics Aperture Size (MB)
The amount of system memory that the AGP card is allowed to share. The default
is 64.
32: 32MB of systems memory accessable by the AGP card.
64: 64MB of systems memory accessable by the AGP card.
Display Cache Frequency
If your insert AGP In-Line Memory Module (AIMM). This function setting
AIMM frequency. The default is 100MHz.
System Memory Frequency
Setting the SDRAM frequency. The default is Auto.
The choice: 100Mhz, 133MHz, Auto.
Onboard Display Cache Setting
Setting the onboard display cache timing.
CAS # Latency
Select the local memory clock periods.
The Choice: 2, 3