EPOX EP-3C1A, Manual

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Installation EP-3C1A
Page 3-7
l a t o T
y r o m e M
1 M M I D
) 1 / 0 k n a B (
) 1 / 0 s w o R (
2 M M I D
) 3 / 2 k n a B (
) 3 / 2 s w o R (
3 M M I D
) 2 / 3 k n a B (
) 2 / 3 s w o R (
B M 6 5 2 =
m u m i x a M
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) S S r o S D (
e n o N e n o N
B M 2 1 5 =
m u m i x a M
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) S S r o S D (
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) S S r o S D (
e n o N
B M 8 6 7 =
m u m i x a M
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) S S r o S D (
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) y l n O S S (
* M A R D S / O D E
, B M 4 6 , B M 2 3 , B M 6 1 , B M 8
1 x B M 6 5 2 , B M 8 2 1
* ) y l n O S S (
* SDRAM only supports 8, 16, 32, 64, 128, 256MB DIMM modules.
* Using non-compliant memory with higher bus speed (over clocking) may severely
compromise the integrity of the system.
* “DS” : Double Side Memory Module
* “SS” : Single Side Memory Module
Section 3-3
System Memory Configuration
Memory Layout
The EP-3C1A supports (3) 168-pin DIMMs (Dual In-line Memory Module). Sockets
are available for 3.3Volt (power level) Synchronous Dynamic Random Access
Memory (SDRAM) of 8, 16, 32, 64, 128MB or 256MB.
• This board supports SPD DIMMs Modules only.
• This board supports 64Mbit and 128Mbit SDRAM technologies.
The registered DIMM Supports 32Mx4 128Mbit Memory Modules only.
• We recommend using at least 125MHz (-8ns) SDRAM DIMM at the 100MHz
(or higher) FSB as timing becomes more critical at these higher speeds.
• DIMM SDRAM may be 83MHz (-12ns), 100MHz (-10ns) or 125MHz (-8ns)
bus speed.
Figure 6 and Table 1 show several possible memory configurations using
Figure 6
Table 1
DIMM 1 (M1)
DIMM 2 (M2)
DIMM 3 (M3)
Bank 0/1
Bank 2/3
Bank 3/2
-Synchronous
-SDRAM DIMM