© Enterpoint Ltd. – Polmaddie6 Manual – Issue 2.2 05/05/2017
10
FPGA
The main device on the Polmaddie6 is the Altera Max10 10M08SAE144C8G FPGA. Device
documentation can be obtained from:
http://www.altera.co.uk/literature/lit-max-10.jsp
Oscillator
The oscillator on Polmaddie6 is a 3.3V, 25MHz ASEM oscillator. This clock signal is routed
through the MAX V CPLD to the FPGA on
Pin 88
, which is a clock input.
Figure 5 – Polmaddie6 Oscillator
