EDM01-09v7 DAG 3.8S Card User Guide
©2005
3
Version 9: May 2006
1.3 DAG 3.8S Card Architecture
Description
Serial SONET/SDH optical data is received by two optical interfaces, and
passed through demultiplexors.
The network data feeds immediately into two physical layer FPGAs. The
SONET/SDH payload data is then sent to the main FPGA.
This FPGA contains the DUCK timestamp engine, packet record
processor, and PCI-X interface logic.
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are stored in an external FIFO
before transmission to the host.
Figure 1-2. DAG 3.8S Card Major Components and Data Flow.
1.4 DAG 3.8S Card Extended Functions
Description
The functionality of the DAG 3.8S can can be extended in many ways.
The framers are normally set up to map STM-1, STS-3c, STM-4c and
STS-12c payloads, but other mappings are possible.
The DAG 3.8S card is equipped with a coprocessor connector which can
be used with the optional Endace DAG Coprocessor as a data processing
tool.
Summary of Contents for DAG 3.8S
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