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EDM01-09v7 DAG 3.8S Card User Guide

©2005

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Version 9: May 2006

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Summary of Contents for DAG 3.8S

Page 1: ......

Page 2: ...839 0540 Fax 64 7 839 0543 Americas Endace USA Ltd Suite 220 11495 Sunset Hill Road Reston Virginia 20190 United States of America Phone 1 703 382 0155 Fax 1 703 382 0155 Europe Middle East Africa End...

Page 3: ...nd Materials The product that this manual pertains to may include extra components and materials that are not essential to its basic operation but are necessary to ensure compliance to the product sta...

Page 4: ...Interpreting DAG 3 8S Card LED Status 13 4 2 DAG 3 8S Card Configuration 15 4 3 Configuration in WYSYCC Style 17 4 4 DAG 3 8S Card Configuration Options 18 4 5 Verify DAG 3 8S Card Configuration 22 4...

Page 5: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 ii Version 9 May 2006...

Page 6: ...l Purpose Description The purpose of this DAG 3 8S Card User Manual is to describe Installing DAG 3 8S Card Setting Optical Power Confidence Testing Running Data Capture Software Synchronizing Clock T...

Page 7: ...tions for OC3c or OC12c ATM or Packet over SONET PoS networks The DAG3 8S card has two transceivers which can be operated simultaneously allowing a single card to monitor one or both directions of a f...

Page 8: ...face logic Because of component close association packets or cells are time stamped accurately Time stamped packet records are stored in an external FIFO before transmission to the host Figure 1 2 DAG...

Page 9: ...with the optional Endace DAG Coprocessor The ATM AAL5 Reassembler specifications are Supports up to 65 535 simultaneously active VCI VPI s Supports simultaneous reassembly of up to 65 536 AAL5 frames...

Page 10: ...ystem is included on the Endace Software Install CD Endace currently supports Windows XP Windows Server 2000 Windows Server 2003 FreeBSD RHEL 3 0 and Debian Linux operating systems Different system Fo...

Page 11: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 6 Version 9 May 2006...

Page 12: ...sert DAG 3 8S Card into PC DAG 3 8S Card Port Connectors 2 1 Installation of Operating System and Endace Software Description If the DAG device driver is not installed before proceeding with the next...

Page 13: ...synchronization input CAUTION This socket should never be connected to an Ethernet network or telepphone line 2 4 DAG 3 8S Card Pluggable Optical Transceivers Description Some newer versions of the D...

Page 14: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 9 Version 9 May 2006 Figure 2 1 Pluggable Optical Transceivers...

Page 15: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 10 Version 9 May 2006...

Page 16: ...26 20 HFCT 5208EM SMF 155 622 7 28 20 In this chapter This chapter covers the following sections of information DAG 3 8S Card Optical Power Input Splitter Losses 3 1 DAG 3 8S Card Optical Power Input...

Page 17: ...0 splitter will have an insertion loss of between 3 dB and 4 dB on each output 90 10 splitter will have losses of about 10 dB in the high loss output and 2 dB in the low loss output Single mode fibre...

Page 18: ...information Interpreting DAG 3 8S Card LED Status DAG 3 8S Card Configuration Configuration in WYSYCC Style DAG 3 8S Card Configuration Options Verify DAG 3 8S Card Configuration General Purpose Count...

Page 19: ...3 Port A Signal Detect valid optical signal seen by the optical receiver LED 4 Port A Link Error LED 5 Port B Signal Detect valid optical signal seen by the optical receiver LED 6 Port B Link Error LE...

Page 20: ...AG 3 8S card capture session Step 1 Check Receiver Ports Optical Signal Levels The card supports 1300 nanometer singlemode and multimode fibre attachments with optical signal strength between 0 dBm an...

Page 21: ...st Available PCI X FPGA Image dag endace dagrom rvp d dag0 f xilinx edag38spci_terf_v2_9 2v1000fg456 2005 10 19 15 04 34 user Step 5 Load Latest Available PHY FPGA Image dag endace dagld x d dag0 xili...

Page 22: ...ve sonetB noscramble slave atmA ascramble atmB ascramble packetA drop 0 packetB drop 0 pcix 66MHz 64 bit buf 128MiB rxstreams 1 txstreams 1 mem 112 16 Step 2 Other Options For other options removing o...

Page 23: ...crc No PoS CRC checking crc16 PoS CRC16 checks enabled crc32 PoS CRC32 checks enabled no pmin Dis enable discard of packets smaller than a predefined minimum size no pmax Dis enable discard of packets...

Page 24: ...to be recognized bip3 bip2 bip1 Bit interleaved parity byte error These bits indicate a problem as reported by SONET B3 B2 and B1 overhead octets If any of these bits are set the card connection to t...

Page 25: ...rhead octet Typical settings are 13 ATM 16 PPP w SPE scrambling CF PPP wo SPE scrambling Changing values for this field indicate a SONET level error lcd Loss of cell delineation If set the ATM state m...

Page 26: ...An example Port A statistics for an ATM cell stream at OC12c is los bip3 bip2 bip1 lop oof lof los label lcd Sync A 0 0 0 0 0 0 0 0 13 0 1 A 0 0 0 0 0 0 0 0 13 0 1 A 0 0 0 0 0 0 0 0 13 0 1 A 0 0 0 0 0...

Page 27: ...If network is PoS the label should be 16 for PPP or cf for HDLC lcd will be 1 sync will be zero It is still necessary to set the card mode correctly using dagthree in order to capture data 4 5 Verify...

Page 28: ...figuration problems The following items are countable 0 sonet_bip1 1 sonet_bip2 2 sonet_bip3 3 atm_bad_hec 4 atm_cor_hec 5 atm_rcv_idle 6 atm_rcv_cell 7 pos_bad_crc 8 pos_min_err 9 pos_max_crc 10 pos_...

Page 29: ...data information is received This typically indicates incorrect scrambling settings While a default is provided that matches typical link settings the actual configuration varies from network to netwo...

Page 30: ...ration 3 Host PC operating system version 4 DAG software version package in use 5 Any compiler errors or warnings when building DAG driver or tools 6 For Linux and FreeBSD messages generated when DAG...

Page 31: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 26 Version 9 May 2006...

Page 32: ...card s physical layer is then set and checked Process Starting a data capture session is described in the following process Process Description Slen parameter default setting Parameters are set with d...

Page 33: ...e d dag0 novarlen slen 48 Disabling individual ports The A and B ports can be individually enabled and disabled for capture using dagthree dagthree d dag0 disableb Starting capture session Once the ca...

Page 34: ...any arriving packets subsequently are discarded by the DAG card Any loss can be detected in band by observing the Loss Counter lctr field of the Extensible Record Format ERF The Endace ERF is explain...

Page 35: ...y protocols It will only transmit packets explicitly provided by the user This capability allows the DAG card to be used as a simple traffic load generator The DAG can also be used to retransmit previ...

Page 36: ...d traffic while transmitting Capture programs such as dagsnap dagconvert and dagbits can be used while dagflood is sending packets Configuring DAG card for transmission To configure a DAG card for tra...

Page 37: ...d for both transmitting and receiving the rxtx option can be used This allocates 16MB of memory to each transmit stream and divides the remaining memory between the receive streams Alternatively the m...

Page 38: ...e UTC Accurate time reference can be obtained from an external clock by connecting to the DAG card using the synchronization connector or the host PCs clock can be used in software as a reference sour...

Page 39: ...shold health threshold in ns default 596 Option default RS422 in none out none None in none out rs422in RS422 input hostin Host input unused overin Internal input synchronize to host clock auxin Aux i...

Page 40: ...clock If a PC is running NTP to synchronize its own clock then the DUCK clock is less smooth because the PC clock is adjusted in small jumps However overall the DUCK clock does not drift away from UTC...

Page 41: ...is configured as the clock master for the other Locking cards together Although the master card s clock will drift against UTC the cards are locked together The cards are locked together by connectin...

Page 42: ...88424ns crystal Actual 49999354Hz Synthesized 16777216Hz input Total 87464 Bad 0 Singles Missed 0 Longest Sequence Missed 0 start Wed Apr 27 14 27 41 2005 host Thu Apr 28 14 59 14 2005 dag Thu Apr 28...

Page 43: ...st Sequence Missed 1 start Thu Apr 28 14 55 20 2005 host Thu Apr 28 14 59 06 2005 dag Thu Apr 28 14 59 06 2005 Connecting time distribution server The TDS 2 module connects to any DAG card with a stan...

Page 44: ...ure 6 1 RJ45 Plug and Socket Connector Pin outs Out pin connections Normally the GPS input should be connected to the A channel input pins 3 and 6 The DAG can also output a synchronization pulse used...

Page 45: ...EDM01 09v7 DAG 3 8S Card User Guide 2005 40 Version 9 May 2006...

Page 46: ...s a byte stream no byte re ordering is applied timestamp timestamp type 1 flags rlen lctr wlen HDLC Header rlen 20 bytes of packet Table 7 1 Type 1 PoS HDLC Variable Length Record Data format The foll...

Page 47: ...er PCI bus to storage Lctr loss counter A 16 bit counter recording the number of packets lost since the previous record Records can be lost between the DAG card and memory hole due to overloading on P...

Page 48: ...th a single 64 bit subtraction It is not necessary to check for overflows between the two halves of the structure as is needed when comparing Unix time structures which are also available to Windows u...

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