2.19.3
External Connectivity
The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module
Pin Connection Guidelines [11] for details regarding the connection of Ethernet signals.
2.19.4
MDIO Address
The MDIO interface is shared between the two Gigabit Ethernet PHYs - these can be configured using the
corresponding address. The MDIO address assigned to PHY 0 is 3 and to PHY 1 is 7.
The MDIO signals are mapped to MIO pins 76-77 and they are routed directly to PHY 1 and via a level shifter
to PHY 0.
2.19.5
PHY Configuration
The configuration of the Ethernet PHYs is bootstrapped when the PHYs are released from reset. Make sure all
I/Os on the RGMII interface are initialized and all pull-up or pull-down resistors are disabled at that moment.
The bootstrap options of the Ethernet PHYs are set as indicated in Table 31.
Pin
Signal Value
Description
MODE[3-0]
1110
RGMII mode: advertise all capabilities (10/100/1000, half/full duplex) ex-
cept 1000Base-T half duplex.
PHYAD[2-0]
011
PHY0: MDIO address 3
111
PHY1: MDIO address 7
Clk125_EN
0
125 MHz clock output disabled
LED_MODE
1
Single LED mode
LED1/LED2
1
Active-low LEDs
Table 31: Gigabit Ethernet PHYs Configuration - Bootstraps
For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed 2
MHz.
2.19.6
RGMII Delays Configuration
The two Ethernet PHYs are connected directly to hard MAC controllers present in the MPSoC device. In
order to achieve the best sampling eye for the RX and TX data, it is recommended to adjust the pad skew
delays as specified in Table 32. These values have been successfully tested on Enclustra side.
The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY; please refer
to the PHY datasheet for details.
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Version 13, 15.08.2019
