PHY Register Name
Register Value [binary]
Delay Value
RXD0-RXD3
0111
0 ps
RX_DV
0111
0 ps
RX_CLK
01111
0 ps
TXD0-TXD3
0111
0 ps
TX_EN
0111
0 ps
GTX_CLK
11110
900 ps
Table 32: Gigabit Ethernet PHYs Configuration - RGMII Delays
2.20
USB 2.0
Two USB 2.0 PHYs are available on the XU1 SoC module, both connected to the PS to I/O bank
502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host.
2.20.1
USB PHY Type
Table 33 describes the equipped USB PHYs device type on the XU1 SoC module.
PHY Type
Manufacturer
Type
USB3320C
Microchip
USB 2.0 PHY
Table 33: USB 2.0 PHY Type
2.20.2
Signal Description
The ULPI interface for the PHY 0 is connected to MIO pins 52-63 for use with the integrated USB controller.
The ULPI interface for the PHY 1 is connected to MIO pins 64-75. The MIO signals are shared between
Ethernet PHY 1 and USB PHY 1, therefore only one of them can be used. By default the Ethernet connection
is enabled. Please refer to Section 2.19.2 for details on how to select Ethernet or USB mode.
Warning!
USB 1 interface is not available when Gigabit Ethernet 1 interface is active.
Warning!
When generating the FSBL in certain SDK versions the power management of the USB interface is not
properly implemented, causing the USB interface not to work as expected. A patch to psu_init.c file
fixing this issue (required for SDK 2017.4) is available from Enclustra upon request.
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Version 13, 15.08.2019
