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Hardware Preparation and Installation

MVME6100 Single Board Computer Installation and Use (6806800D58E

)

The MVME6100 is factory tested and shipped with the configuration described in the following
sections.

Figure 1-1

Component Layout

4296 0604

10/100/1000

ABT/RST

LAN 1

LAN 2

J42

J30

J19

J13

J14

J11

J12

J23

J24

J21

J22

PCI MEZZANINE CARD

U12

10/100/1000

J93

J29

PMC

IPMC

U32

1 2 3 4 5 6 7 8

Summary of Contents for MVME6100 Series

Page 1: ...Embedded Computing for Business Critical ContinuityTM MVME6100 Single Board Computer Installation and Use P N 6806800D58E March 2009 ...

Page 2: ...his document and to make changes from time to time in the content hereof without obligation of Emerson to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to a Emerson website The text itself may not be published commercially in print or electronic form edited translated or o...

Page 3: ...4 Front Rear Ethernet and Transition Module Options Header J30 23 1 4 5 SROM Configuration Switch S3 24 1 4 6 Flash Boot Bank Select Configuration Switch S4 26 1 5 Installing the Blade 27 1 6 Connecting to Peripherals 27 1 7 Completing the Installation 28 2 Startup and Operation 29 2 1 Introduction 29 2 2 Applying Power 29 2 3 Switches and Indicators 29 3 MOTLoad Firmware 31 3 1 Overview 31 3 2 Im...

Page 4: ...3 9 Firmware Scan for Boot Image 50 3 10 Boot Images 52 3 10 1 Checksum Algorithm 52 3 10 2 Image Flags 53 3 10 3 User Images 54 3 10 4 Alternate Boot Data Structure 55 3 10 5 Alternate Boot Images and Safe Start 55 3 10 6 Boot Image Firmware Scan 56 3 11 Startup Sequence 57 4 Functional Description 59 4 1 Overview 59 4 2 Features 59 4 3 Block Diagram 61 4 4 Processor 61 4 5 L3 Cache 62 4 6 System...

Page 5: ...71 4 15 Reset Control Logic 71 4 16 Debug Support 71 4 17 Processor JTAG COP Headers 72 5 Pin Assignments 73 5 1 Overview 73 5 2 Connectors 73 5 2 1 PMC Expansion Connector J4 74 5 2 2 Gigabit Ethernet Connectors J9 J93 77 5 2 3 PCI Mezzanine Card PMC Connectors J11 J14 J21 J24 77 5 2 4 COM1 Connector J19 88 5 2 5 VMEbus P1 Connector 89 5 2 6 VMEBus P2 Connector PMC Mode 90 5 2 7 VMEbus P2 Connect...

Page 6: ...lated Documentation 103 C 1 Emerson Network Power Embedded Computing Documents 103 C 2 Manufacturers Documents 103 C 3 Related Specifications 105 B Thermal Validation 107 B 1 Overview 107 B 2 Thermally Significant Components 107 B 3 Component Temperature Measurement 110 B 3 1 Preparation 110 B 3 2 Measuring Junction Temperature 111 B 3 3 Measuring Case Temperature 111 B 3 4 Measuring Local Air Tem...

Page 7: ...ssignments 83 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments 84 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments 85 Table 5 10 PMC Slot 2 Connector J24 Pin Assignments 87 Table 5 11 COM1 Connector J19 Pin Assignments 88 Table 5 12 VMEbus P1 Connector Pin Assignments 89 Table 5 13 VMEbus P2 Connector Pin Assignments PMC Mode 90 Table 5 14 VME P2 Connector Pinouts with IPMC712 93 Table 5 15 VM...

Page 8: ...MVME6100 Single Board Computer Installation and Use 6806800D58E 8 List of Tables Table B 1 Thermally Significant Components 108 ...

Page 9: ...igure 1 3 PMC IPMC Header Settings 22 Figure 1 4 Front Rear Ethernet Option Settings 24 Figure 4 1 MVME6100 Block Diagram 61 Figure B 1 Thermally Significant Components Primary Side 109 Figure B 2 Thermally Significant Components Secondary Side 110 Figure B 3 Mounting a Thermocouple Under a Heatsink 112 Figure B 4 Measuring Local Air Temperature 113 ...

Page 10: ...MVME6100 Single Board Computer Installation and Use 6806800D58E 10 List of Figures ...

Page 11: ...5 Pin Assignments provides pin assignments for various headers and connectors on the MMVE6100 single board computer Appendix A Specifications provides power requirements and environmental specifications Appendix B Thermal Validation provides information to conduct thermal evaluations and identifies thermally significant components along with their maximum allowable operating temperatures Appendix ...

Page 12: ...E61006E 0171 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash Scanbe handles MVME61006E 0173 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash IEEE handles Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Usedfor...

Page 13: ...xample command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attent...

Page 14: ... how you used it Part Number Date Changes 6806800D58E March 2009 Added csUserAltBoot command to Table MOTLoad Commands on page 33 editorial changes 6806800D58D April 2008 Updated to Emerson publications style 6806800D58C January 2008 Updated to remove two incorrect sources of reset See Reset Control Logic on page 71 Table 5 13 on page 90 was updated toindicatebothpossibleusesofpinsC1 C2 C3 C4 Z25 ...

Page 15: ...e MVME6100 contains two IEEE1386 1 PCI PCI X capable mezzanine card slots The PMC slots are 64 bit capable and support both front and rear I O All I O pins of PMC slot 1 and 46 I O pins of PMC slot 2 are routed to the 5 row DIN P2 connector I O pins 1 through 64 from J14 of PMC slot 1 are routed to row C and row A of P2 I O pins 1 through 46 from J24 of PMC slot 2 are routed to row D and row Z of ...

Page 16: ...r IPMC mode is done by the jumper blocks J10 J15 J18 and J25 J28 see Table 1 2 on page 19 IPMC mode is selected when an IPMC712 or IPMC761 module is used If an IPMC is used J30 should be configured for the appropriate transition module seeJ30configurationoptionsasillustratedin Front RearEthernetandTransitionModule Options Header J30 on page 23 The IPMC712 and IPMC761 use AD11 as the IDSEL line for...

Page 17: ...uidelines Unpack the equipment from the shipping carton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of equipment Table 1 1 Startup Overview What you need to do Refer to Unpack the hardware Unpacking Guidelines on page 17 Configure the hardware by setting jumpers on the board Configuring the Hardware on page 18 Install the MVM...

Page 18: ...scharge can damage circuits Emerson strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to electrostatic discharge ESD After removing the component from its protective wrapper or from the system place the component flat on a ...

Page 19: ...in brackets For pin assignments on the MVME6100 refer to Chapter 5 Pin Assignments Items in brackets are factory default settings Table 1 2 Jumper and Switch Settings Jumper S witch Function Settings J7 SCON Header No jumper installed 1 2 2 3 Auto SCON Always SCON No SCON J10 J15 J18 J25 J28 PMC IPMC Selection Headers Jumper installed 1 2 2 3 PMC I O IPMC I O for IPMC7xx support default J30 Front ...

Page 20: ...dandshippedwiththeconfigurationdescribedinthefollowing sections Figure 1 1 Component Layout 4296 0604 10 100 1000 DEBUG ABT RST LAN 1 LAN 2 J42 J8 J30 J3 J19 J13 J14 J11 J12 J23 J24 J21 J22 P1 P2 PCI MEZZANINE CARD PCI MEZZANINE CARD J4 U12 10 100 1000 J93 J9 J29 J7 PMC IPMC U32 S2 1 2 3 4 5 6 7 8 1 2 3 4 1 2 3 4 5 6 7 8 S4 S1 S3 ...

Page 21: ...ys enabled A jumper installed across pins 2 and 3 configures for SCON disabled No jumper installed configures for auto SCON 1 4 2 PMC IPMC Selection Headers J10 J15 J18 J25 J28 Nine 3 pin planar headers are for PMC IPMC mode I O selection for PMC slot 1 These nine headers can also be combined into one single header block where a block shunt can be used as a jumper Figure 1 2 SCON Header Settings J...

Page 22: ... if the keying pins are not installed the PMC sites will not function Note that setting the PMC I O voltage to 5 0V forces the PMC sites to operate in PCI mode instead of PCI X mode The VIO keying pins are the silver colored pins located either in the middle of each set of four PMC site connectors or just in front of those connectors They serve two functions on the MVME6100 both as jumpers to sele...

Page 23: ... have keying holes in both locations that is they will fit on the MVME6100 s PMC site with the key in either location For these PMC cards it is recommendedsettingtheMVME6100 skeyingpins tothe3 3VVIOsignalingposition toallow the maximum PCIbus clock speed 1 4 4 Front Rear Ethernet and Transition Module Options Header J30 A 40 pin planar header allows for selecting P2 options Jumpers installed acros...

Page 24: ...n SMT switch S3 enables disables the MV64360 SROM initialization and all I2 C EEPROM write protection The SROM Init switch is OFF to disable the MV64360 device initialization via the I2C SROM The switch is ON to enable this sequence Figure 1 4 Front Rear Ethernet Option Settings 4294 0 1 11 21 31 10 20 30 40 Front Ethernet Default 1 11 21 31 10 20 30 40 Rear Ethernet 1 11 21 31 1 2 3 4 Non Specifi...

Page 25: ...is installed in a 3 row backplane The following is the pinout Setting the individual position to ON forces the corresponding signal to zero If the board is installed in a 5 row backplane the geographical address is defined by the backplane and positions 3 8 of S3 should be set to OFF The default setting is OFF Table 1 3 SROM Configuration Switch S3 Position 2 1 FUNCTION SROM WP SROM_INIT DEFAULT O...

Page 26: ...f Bank B Boot block The Bank A WP switch is OFF to indicate that the entire Flash Bank A is write protected The switch is ON to indicate no write protection of Bank A Boot block When the Boot Bank Sel Switch is ON the board boots from Bank B when OFF the board boots from Bank A Default is ON boot from Bank B When the Safe Start switch is set OFF normal boot sequence should be followed by MOTLoad W...

Page 27: ...ejectors are in the outward position 5 Slide the MVME6100 into the chassis until resistance is felt 6 Simultaneously move the injector ejector levers in an inward direction 7 Verify that the MVME6100 is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers 8 Connect the appropriate cables to the MVME6100 To remove the board from the chass...

Page 28: ...ware is installed and the power peripheral cables connected are appropriate for your system configuration Replace the chassis or system cover reconnect the system to the AC or DC power source and turn the equipment power on Table 1 5 MVME6100 Connectors Connector Function J3 IPMC761 712 connector J4 PMC expansion connector J9 J93 Gigabit Ethernet connectors J11 J12 J13 J14 PCI mezzanine card PMC s...

Page 29: ...ors The MVME6100 board provides a single pushbutton switch that provides both abort and reset ABT RST functions When the switch is depressed for less than three seconds an abort interrupt is generated to the processor If the switch is held for more than three seconds a board hard reset is generated The board hard reset will reset the MPC7457 MV64360 Tsi148 VME Bridge ASIC PCI6520 PMC1 2 slots both...

Page 30: ...ter Installation and Use 6806800D58E 30 The following table describes these indicators Table 2 1 Front Panel LED Status Indicators Function Label Color Description CPU Bus Activity CPU Green CPU bus is busy Board Fail BDFAIL Yellow Board has a failure ...

Page 31: ...mentation and Memory Requirements The implementation of MOTLoad and its memory requirements are product specific The MVME6100single boardcomputer SBC isofferedwithawiderangeofmemory forexample DRAM external cache flash Typically the smallest amount of on board DRAM that an Emerson SBC has is 32 MB Each supported product line has its own unique MOTLoad binary image s Currently the largest MOTLoad c...

Page 32: ...ts operate automatically without any user interaction There are a few tests where the functionality being validated requires user interaction that is switch tests interactive plug in hardware modules etc Most MOTLoad test results error data status data are logged not printed All MOTLoad tests commands have complete and separate descriptions refer to the MOTLoad Firmware Package User s Manual for t...

Page 33: ...s and test status are obtained through the testStatus errorDisplay and taskActive commands Refer to the appropriate command description page in the MOTLoad Firmware Package User s Manual for more information 3 3 3 Command List The following table provides a list of all current MOTLoad commands Products supported by MOTLoad may or may not employ the full command set Typing help at the MOTLoad comma...

Page 34: ... Table s cm Turns on Concurrent Mode csb csh csw Calculates a Checksum Specified by Command line Options csUserAltBoot Checksums user boot images specified in the alternete boot image header at the beginning of files to be programmed into flash memory devShow Display Show Device Node Table diskBoot Disk Boot Direct Access Mass Storage Device downLoad Down Load S Record from Host ds One Line Instru...

Page 35: ...s Dump NVRAM Header Data gevEdit Global Environment Variable Edit gevInit Global Environment Variable Area Initialize NVRAM Header gevList Global Environment Variable Labels Names Listing gevShow Global Environment Variable Show gn Go Execute User Program to Next Instruction go Go Execute User Program gt Go Execute User Program to Temporary Break Point hbd Display History Buffer hbx Execute Histor...

Page 36: ... Turns off Concurrent Mode pciDataRd Read PCI Device Configuration Header Register pciDataWr Write PCI Device Configuration Header Register pciDump Dump PCI Device Configuration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Network Host portSet Port Set portShow Display Port Device Configuration Data rd User ...

Page 37: ... RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RAM Random Data Patterns testRtcAlarm RTC Alarm testRtcReset RTC Reset testRtcRollOver RTC Rollover...

Page 38: ...n key to signify the end of input MOTLoad then performs the specified action An example of a MOTLoad command line promptis shown below The MOTLoad promptchanges according towhatproduct it is used on for example MVME5500 MVME6100 Example testSuite Execute Test Suite testSuiteMake Make Create Test Suite testWatchdogTimer Tests the Accuracy of the Watchdog Timer Device tftpGet TFTP Get tftpPut TFTP P...

Page 39: ...mand string had been entered This feature is a user input shortcut that minimizestherequiredamountofcommandlineinput MOTLoad isaneverchangingfirmware package so user input shortcuts may change as command additions are made Example MVME6100 version Copyright Motorola Inc 1999 2002 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 1 Motorola MVME6100 Example MVME6100 ver Copyright Motorola ...

Page 40: ...All commands command options and device tree strings are case sensitive Example MVME6100 flashProgram d dev flash0 n00100000 For more information on MOTLoad operation and function refer to the MOTLoad Firmware Package User s Manual 3 4 2 Command Line Help Each MOTLoad firmware package has an extensive product specific help facility that can be accessed through the help command The user can enter h...

Page 41: ...the firmware command utility vmeCfg 3 5 1 Default VME Settings As shipped from the factory the MVME6100 has the following VME configuration programmed via Global Environment Variables GEVs for the Tsi148 VME controller The firmware allows certain VME settings to be changed in order for the user to customize the environment The following is a description of the default VME settings that are changea...

Page 42: ...ibute Register 00000000 CRG Base Address Upper Register 00000000 CRG Base Address Lower Register 00000000 MVME6100 The CRG Attribute Register is set to the default RESET condition z MVME6100 vmeCfg s i0 Displaying the selected Default VME Setting interpreted as follows Inbound Image 0 Attribute Register 000227AF Inbound Image 0 Starting Address Upper Register 00000000 Inbound Image 0 Starting Addr...

Page 43: ...slation Offset Upper Register 00000000 Outbound Image 1 Translation Offset Lower Register 70000000 Outbound Image 1 2eSST Broadcast Select Register 00000000 MVME6100 Outbound window 1 OTAT1 is enabled 2eSST timing at SST320 transfer mode of 2eSST A32 D32 Supervisory access The window accepts transfers on the PCI X Local Bus from 0x91000000 0xAFFF0000 and translates them onto the VMEbus using an of...

Page 44: ...ddress Lower Register B3FF0000 Outbound Image 3 Ending Address Upper Register 00000000 Outbound Image 3 Ending Address Lower Register B3FF0000 Outbound Image 3 Translation Offset Upper Register 00000000 Outbound Image 3 Translation Offset Lower Register 4C000000 Outbound Image 3 2eSST Broadcast Select Register 00000000 MVME6100 Outbound window 3 OTAT3 is enabled 2eSST timing at SST320 transfer mod...

Page 45: ... Register Control Status Register Settings The CR CSR base address is initialized to the appropriate setting based on the Geographical address that is the VME slot number See the VME64 Specification and the VME64 Extensions for details As a result a 512K byte CR CSR area can be accessed from the VMEbus using the CR CSR AM code 3 5 3 Displaying VME Settings To display the changeable VME setting typ...

Page 46: ...are prompt z vmeCfg e m Edits Master Enable state z vmeCfg e i 0 7 Edits selected Inbound Window state z vmeCfg e o 0 7 Edits selected Outbound Window state z vmeCfg e r184 Edits PCI Miscellaneous Register state z vmeCfg e r188 Edits Special PCI Target Image Register state z vmeCfg e r400 Edits Master Control Register state z vmeCfg e r404 Edits Miscellaneous Control Register state z vmeCfg e r40C...

Page 47: ...bound Window state z vmeCfg d r184 Deletes PCI Miscellaneous Register state z vmeCfg d r188 Deletes Special PCI Target Image Register state z vmeCfg d r400 Deletes Master Control Register state z vmeCfg d r404 Deletes Miscellaneous Control Register state z vmeCfg d r40C Deletes User AM Codes Register state z vmeCfg d rF70 Deletes VMEbus Register Access Image Control Register state 3 5 6 Restoring ...

Page 48: ... the target CR CSR slave addresses configured by MOTLoad are assigned according to the installation slot in the backplane as indicated by the VME64 Specification For reference the following values are provided For further details on CR CSR space please refer to the VME64 Specification listed in Appendix C Related Documentation The MVME6100 uses a Discovery II for its VME bridge The offsets of the ...

Page 49: ...ng to support reads and writes of address 0x002ff348 in VME CR CSR space 0x280000 0x7f348 3 7 Alternate Boot Images and Safe Start Some later versions of MOTLoad support Alternate Boot Images and a Safe Start recovery procedure If Safe Start is available on the MVME6100 Alternate Boot Images are supported With Alternate Boot Image support the bootloadercode in the boot block examines the upper 8MB...

Page 50: ...age The scan is performed by examining each 1MB boundary for a defined set of flags that identify the image as being Power On SelfTest POST USER or MCG MOTLoad is an MCG image POST is a user developed Power On Self Test that would perform a set of diagnostics and then return to the bootloader image User would be a boot image such as the VxWorks bootrom which would perform board initialization A bo...

Page 51: ...e is provided to enable recovery in cases when the programmed Alternate Boot Image is no longer desired The following output is an example of an interactive Safe Start ABCDEInteractive Boot Mode Entered boot Interactive boot commands d show directory of alternate boot images c continue with normal startup q quit without executing any alternate boot image r address execute specified or default alte...

Page 52: ...he checksum calculation The calculation assumes the location to be zero The algorithm is implemented using the following code Unsigned int checksum Unsigned int startPtr starting address Unsigned int endPtr ending address unsigned int checksum 0 while startPtr endPtr checksum startPtr Name Type Size Notes UserDefined unsigned integer 8 User defined ImageKey 1 unsigned integer 1 0x414c5420 ImageKey...

Page 53: ...e z IMAGE_MCG If set this flag defines the image as being an Alternate MOTLoad as opposed to USER image This bit should not be set by developers of alternate boot images z IMAGE_POST If set this flag defines the image as being a power on self test image This bit flag is used to indicate that the image is a diagnostic and should be run prior to running either USER or MCG boot images POST images are...

Page 54: ... and is mapped starting at CPU address 0 z If RAM ECC or parity is supported RAM has been scrubbed of ECC or parity errors z The active Flash bank boot is mapped from the upper end of the address space z If specified by COPY_TO_RAM the image has been copied to RAM at the address specified by ImageRamAddress z CPU register R1 the stack pointer has been initialized to a value near the end of RAM z C...

Page 55: ...e board to whatever state the image may further require for its execution POST images are expected but not required to return to the boot loader Upon return the boot loader proceeds with the scan for an executable alternate boot image POST images that return control to the boot loader must ensure that upon return the state of the board is consistent with the state that the board was in at POST ent...

Page 56: ...s of the same type control is passed to the first image encountered in the scan SafeStart whetherinvokedbyhittingESContheconsolewithinthefirstfivesecondsfollowing power on reset or by setting the Safe Start jumper interrupts the scan process The user may then display the available boot images and select the desired image The feature is provided to enable recovery incaseswhenthe programmed Alternat...

Page 57: ...sh bank possibly interactively for a valid USER boot image If found the USER boot image executes A return to the boot block code is not anticipated z If a valid USER boot image is not found search the active flash bank possibly interactively for a valid Alternate MOTLoad boot image anticipated to be an upgrade of alternate MOTLoad firmware If found the image is executed A return to the boot block ...

Page 58: ...MOTLoad Firmware MVME6100 Single Board Computer Installation and Use 6806800D58E 58 ...

Page 59: ...d by processor Up to 2MB using DDR SRAM Flash Two banks A B of soldered Intel StrataFlash devices 8 to 64MB supported on each bank Boot bank is switch selectable between banks Bank A has combination of software and hardware write protect scheme Bank B top 1MB block can be write protected through software hardware write protect control System Memory Two banks on board for up to 1Gb using 256Mb or 5...

Page 60: ... PCI or 66 100 MHz PCI X VME Interface Tsi148 VME 2eSST ASIC provides z Eight programmable VMEbus map decoders z A16 A24 A32 and A64 address z 8 bit 16 bit and 32 bit single cycle data transfers z 8 bit 16 bit 32 bit and 64 bit block transfers z Supports SCT BLT MBLT 2eVME and 2eSST protocols z 8 entry command and 4KB data write post buffer z 4KB read ahead buffer PMCspan Support One PMCspan slot ...

Page 61: ...C7457 has integrated L1 and L2 caches as the factory build configuration and supports an L3 cache interface with on chip tags to support up to 2MB of off chip cache 2 5V signal levels are used on the processor bus Figure 4 1 MVME6100 Block Diagram 64 bit 33 66 100 MHz PCI X L3 Cache 2MB MPC7457 1 267 GHz 211 MHz DDR 133 MHz Processor Bus 133 MHz Memory Bus RTC NVRAM VME TSI148 Soldered Flash Bank ...

Page 62: ...he L3CR register Refer to the PowerPC Apollo Microprocessor Implementation Definition Book IV listed in Appendix C Related Documentation 4 6 System Controller The MV64360 is an integrated system controller for high performance embedded control applications The following features of the MV64360 are supported by the MVME6100 The MV64360 has a five bus architecture comprised of z A 72 bit interface t...

Page 63: ...n the CPU interface z Four for SDRAM chip selects z Five for device chip selects z Five for the PCI_0 interface four memory one I O z Five for the PCI_1 interface four memory one I O z One for the MV64360 integrated SRAM z One for the MV64360 internal registers space Each window is defined by base and size registers and can decode up to 4GB space except for the integrated SRAM which is fixed to 25...

Page 64: ...ts up to 512MB of address space resulting in total device space of 1 5GB Serial ports are the fourth and fifth devices on the MVME6100 Each bank has its own parameters register as shown in the following table 4 6 4 PCI PCI X Interfaces The MVME6100 provides two 32 64 bit PCI PCI X buses operating at a maximum frequency of 100 MHz when configured to PCI X mode and run at 33 or 66 MHz when running c...

Page 65: ...tion Each Ethernet interface is assigned an Ethernet Station Address The address is unique for each device The Ethernet Station Addresses are displayed on labels attached to the PMC front panel keep out area The MV64360 is not integrated with a PHY for the Ethernet interfaces External PHY is the Broadcom BCM5461S 10 100 1000BaseT Gigabit transceiver with SERDES interface Refer to Appendix C Relate...

Page 66: ...ing the I2O messaging unit refer to the MV64360 Data Sheet listed in Appendix C Related Documentation 4 6 10 Four Channel Independent DMA Controller The MV64360 incorporates four independent direct memory access IDMA engines Each IDMA engine has the capability to transfer data between any two interfaces Refer to the MV64360 Data Sheet listed in Appendix C Related Documentation for additional infor...

Page 67: ...e device 4 6 12 Interrupt Controller The MVME6100 uses the interrupt controller integrated into the MV64360 device to manage the MV64360 internal interrupts as well as the external interrupt requests The interrupts are routed to the MV64360 MPP pins from on board resources as shown in the MVME6100 Programmer s Guide The external interrupt sources include the following z On board PCI device interru...

Page 68: ...gned to the MPP pins as shown in the MVME6100 Programmer s Guide 4 7 VMEbus Interface The VMEbusinterface is providedby the Tsi148ASIC Refer tothe Tsi148 User s Manualavailable from Tundra Semiconductor for additional information as listed in Appendix C Related Documentation 2eSST operations are not supported on 3 row backplanes You must use VME64x VITA 1 5 compatible backplanes such as 5 row back...

Page 69: ...on the MVME6100 COM1 is an RS232 port and the TTL level signals are routed through appropriate EIA 232 drivers and receivers to an RJ 45 connector on the front panel Unused control inputs on COM1 and COM2 are wired active The reference clock frequency for the QUART is 1 8432 MHz All UART ports are capable of signaling at up to 115 Kbaud 4 12 PCI Mezzanine Card Slots The MVME6100 board supports two...

Page 70: ...ltage VIO 3 3V 5V tolerant or 5V selected by keying pin You cannot use 3 3V and 5 0V PMCs together the voltage keying pin on slots 1 and 2 must be identical When in 5 0V mode the bus runs at 33 MHz Mezzanine Type PMC PCI Mezzanine Card Mezzanine Size Double width and standard depth 150mm x 150mm with front panel PMC Connectors J11 J12 J13 J14 J21 J22 J23 and J24 32 64 bit PCI with front and rear I...

Page 71: ...x C Related Documentation for additional information and programming details 4 14 IDSEL Routing PCI device configuration registers are accessed by using the IDSEL signal of each PCI agent to an A D signal as defined in version 2 2 of the PCI specification IDSEL assignments to on board resources are specified in the MVME6100 Programmer s Guide 4 15 Reset Control Logic The sources of reset on the MV...

Page 72: ... Computer Installation and Use 6806800D58E 72 4 17 Processor JTAG COP Headers The MVME6100 provides JTAG COP connectors for JTAG COP emulator support RISCWatch COP J42 as well as supporting board boundary scan capabilities Boundary Scan header J8 ...

Page 73: ...ernet Connectors J9 J93 z PCI Mezzanine Card PMC Connectors J11 J14 J21 J24 z COM1 Connector J19 z VMEbus P1 Connector z VMEbus P2 Connector IPMC Mode The following headers are described in this chapter z SCON Header J7 z Boundary Scan Header J8 z PMC IPMC Selection Headers J10 J15 J18 J25 J28 z COM2 Header J29 z Front Rear Ethernet and Transition Module Options Header J30 z Processor JTAG COP Hea...

Page 74: ...ignments for this connector are as follows Table 5 1 PMC Expansion Connector J4 Pin Assignments Pin Signal Signal Pin 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PCIXP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK SDONE 24 25 DEVSEL SBO 26 27 GND GND 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND M66EN ...

Page 75: ...2 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 76: ...E5 C BE4 80 81 C BE7 C BE6 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 77: ...tors J11 J14 J21 J24 There are eight 64 pin SMT connectors on the MVME6100 to provide 32 64 bit PCI interfaces and P2 I O for two optional add on PMCs PMC slot connectors J14 and J24 contain the signals that go to VME P2 I O rows A C D and Z Table 5 2 Gigabit Ethernet Connectors J9 J93 Pin Assignment Pin Signal 1000 Mb s 10 100 Mb s 1 CT_BOARD 2 5V 2 5V 2 MDIO0 B1_DA 1 TD 3 MDIO0 B1_DA TD 4 MDIO1 ...

Page 78: ... 1 TCK 12V 2 3 GND INTA 4 5 INTB INTC 6 7 PMCPRSNT1 5V 8 9 INTD PCI_RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 PCIXCAP LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 ...

Page 79: ...onnector J12 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued P...

Page 80: ...52 53 3 3V GNT1B 54 55 Not Used GND 56 57 Not Used EREADY0 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 5 PMC Slot 1 Connector J13 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments contin...

Page 81: ... 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 Table 5 6 PMC Slot 1 Connector J14 Pin Assignments Pin Signal Signal Pin 1 PMC0_1 P2 C1 PMC0_2 P2 A1 2 Table 5 5 PMC Slot 1 Connector J13 Pin Assignments conti...

Page 82: ...PMC0_25 P2 C13 PMC0_26 P2 A13 26 27 PMC0_27 P2 C14 PMC0_28 P2 A14 28 29 PMC0_29 P2 C15 PMC0_30 P2 A15 30 31 PMC0_31 P2 C16 PMC0_32 P2 A16 32 33 PMC0_33 P2 C17 PMC0_34 P2 A17 34 35 PMC0_35 P2 C18 PMC0_36 P2 A18 36 37 PMC0_37 P2 C19 PMC0_38 P2 A19 38 39 PMC0_39 P2 C20 PMC0_40 P2 A20 40 41 PMC0_41 P2 C21 PMC0_42 P2 A21 42 43 PMC0_43 P2 C22 PMC0_44 P2 A22 44 45 PMC0_45 P2 C23 PMC0_46 P2 A23 46 47 PMC0...

Page 83: ...ctor J21 Pin Assignments Pin Signal Signal Pin 1 TCK 12V 2 3 GND INTC 4 5 INTD INTA 6 7 PMCPRSNT1 5V 8 9 INTB PCI_RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 PCIXCAP LOCK 40 Table 5 6 PMC Slot 1 Connect...

Page 84: ... 3 3V VIO AD03 58 59 AD02 AD01 60 61 AD00 5V 62 63 GND REQ64 64 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments continued...

Page 85: ... 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3V 50 51 AD07 REQ1B 52 53 3 3V GNT1B 54 55 Not Used GND 56 57 Not Used EREADY1 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments conti...

Page 86: ...55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments continued Pin Signal Sign...

Page 87: ...11 16 17 PMC1_17 P2 Z11 PMC1_18 P2 D12 18 19 PMC1_19 P2 D13 PMC1_20 P2 Z13 20 21 PMC1_21 P2 D14 PMC1_22 P2 D15 22 23 PMC1_23 P2 Z15 PMC1_24 P2 D16 24 25 PMC1_25 P2 D17 PMC1_26 P2 Z17 26 27 PMC1_27 P2 D18 PMC1_28 P2 D19 28 29 PMC1_29 P2 Z19 PMC1_30 P2 D20 30 31 PMC1_31 P2 D21 PMC1_32 P2 Z21 32 33 PMC1_33 P2 D22 PMC1_34 P2 D23 34 35 PMC1_35 P2 Z23 PMC1_36 P2 D24 36 37 PMC1_37 P2 D25 PMC1_38 P2 Z25 3...

Page 88: ...nts for this connector are as follows 47 Not Used Not Used 48 49 Not Used Not Used 50 51 Not Used Not Used 52 53 Not Used Not Used 54 55 Not Used Not Used 56 57 Not Used Not Used 58 59 Not Used Not Used 60 61 Not Used Not Used 62 63 Not Used Not Used 64 Table 5 10 PMC Slot 2 Connector J24 Pin Assignments continued Pin Signal Signal Pin Table 5 11 COM1 Connector J19 Pin Assignments Pin Signal 1 DCD...

Page 89: ...ved 4 5 Reserved D04 BG0OUT D12 Reserved 5 6 GND D05 BG1IN D13 Reserved 6 7 Reserved D06 BG1OUT D14 Reserved 7 8 GND D07 BG2IN D15 Reserved 8 9 Reserved GND BG2OUT GND Reserved Geographical Address parity 9 10 GND SYSCLK BG3IN SYSFAIL Reserved GA0 10 11 Reserved GND BG3OUT BERR Reserved GA1 11 12 GND DS1 BR0 SYSRESET Reserved 12 13 Reserved DS0 BR1 LWORD Reserved GA2 13 14 GND WRITE BR2 AM5 Reserv...

Page 90: ...erved 27 28 GND A03 IRQ3 A10 Reserved 28 29 Reserved A02 IRQ2 A09 Reserved 29 30 GND A01 IRQ1 A08 Reserved 30 31 Reserved 12V 5VSTDBY 12V Reserved 31 32 GND 5V 5V 5V Reserved 32 Table 5 12 VMEbus P1 Connector Pin Assignments continued ROW Z ROW A ROW B ROW C ROW D Table 5 13 VMEbus P2 Connector Pin Assignments PMC Mode ROW Z ROW A ROW B ROW C ROW D 1 PMC1_2 J24 2 PMC0_2 J14 2 5V PMC0_1 J30 D6 C6 o...

Page 91: ...7 J14 17 PMC1_13 J24 13 9 10 GND PMC0_2 0 J14 20 VA30 PMC0_19 J14 19 PMC1_15 J24 15 10 11 PMC1_17 J24 17 PMC0_2 2 J14 22 VA31 PMC0_21 J14 21 PMC1_16 J24 16 11 12 GND PMC0_2 4 J14 24 GND PMC0_23 J14 23 PMC1_18 J24 18 12 13 PMC1_20 J24 20 PMC0_2 6 J14 26 5V PMC0_25 J14 25 PMC1_19 J24 19 13 14 GND PMC0_2 8 J14 28 VD16 PMC0_27 J14 27 PMC1_21 J24 21 14 15 PMC1_23 J24 J23 PMC0_3 0 J14 30 VD17 PMC0_29 J1...

Page 92: ...1 J14 41 PMC1_31 J24 31 21 22 GND PMC0_4 4 J14 44 GND PMC0_43 J14 43 PMC1_33 J24 33 22 23 PMC1_35 J24 35 PMC0_4 6 J14 46 VD24 PMC0_45 J14 45 PMC1_34 J24 34 23 24 GND PMC0_4 8 J14 48 VD25 PMC0_47 J14 47 PMC1_36 J24 36 24 25 PMC1_38 J30 D7 C7 or P2_IO_GLAN1_M DIO_2 J30 B7 C7 PMC0_5 0 J14 50 VD26 PMC0_49 J14 49 PMC1_37 J24 37 25 26 GND PMC0_5 2 J14 52 VD27 PMC0_51 J14 51 PMC1_39 J24 39 26 27 PMC1_41 ...

Page 93: ...55 J14 55 RXB PMC1_42 J24 42 28 29 PMC1_44 J30 D9 C9 or P2_IO_GLAN1_M DIO_3 J30 B9 C9 PMC0_5 8 J14 58 VD30 PMC0_57 J14 57 RTSB PMC1_43 J24 43 29 30 GND PMC0_6 0 J14 60 VD31 PMC0_59 J14 59 CTSB PMC1_45 J24 45 30 31 PMC1_46 J30 D10 C10 or P2_IO_GLAN1_M DIO_3 J30 B10 C10 PMC0_6 2 J14 62 GND PMC0_61 J14 61 GND 31 32 GND PMC0_6 4 J14 64 5V PMC0_63 J14 63 VPC 32 Table 5 13 VMEbus P2 Connector Pin Assign...

Page 94: ..._24 J24 24 17 PMC2_26 REQ VD19 P ACK PMC2_25 J24 25 18 GND I O VD20 P BSY PMC2_27 J24 27 19 PMC2_29 J24 29 TXD3 VD21 P PE PMC2_28 J24 28 20 GND RXD3 VD22 P SEL PMC2_30 J24 30 21 PMC2_32 J24 32 RTS3 VD23 P IME PMC2_31 J24 31 22 GND CTS3 GND P FAULT PMC2_33 J24 33 23 PMC2_35 J24 35 DTR3 VD24 TXD1_232 PMC2_34 J24 34 24 GND DCD3 VD25 RXD1 PMC2_36 J24 36 25 PMC2_38 J24 38 TXD4 VD26 RTS1 PMC2_37 J24 37 ...

Page 95: ...D DB7 VA28 PRSTB PMC2_12 J24 12 9 DB12 DBP VA29 PRD0 PMC2_13 J24 13 10 GND ATN VA30 PRD1 PMC2_15 J24 15 11 DB13 BSY VA31 PRD2 PMC2_16 J24 16 12 GND ACK GND PRD3 PMC2_18 J24 18 13 DB14 RST 5V PRD4 PMC2_19 J24 19 14 GND MSG VD16 PRD5 PMC2_21 J24 21 15 DB15 SEL VD17 PRD6 PMC2_22 J24 22 16 GND D C VD18 PRD7 PMC2_24 J24 24 17 DBP1 REQ VD19 PRACK PMC2_25 J24 25 18 GND O I VD20 PRBSY PMC2_27 J24 27 19 PM...

Page 96: ...ge 18 for details on setting the headers 23 PMC2_35 J24 35 RTXC3 VD24 TXD1_232 PMC2_34 J24 34 24 GND TRXC3 VD25 RXD1_232 PMC2_36 J24 36 25 PMC2_38 J24 38 TXD4 VD26 RTS1_232 PMC2_37 J24 37 26 GND RXD4 VD27 CTS1_232 PMC2_39 J24 39 27 PMC2_41 J24 41 RTXC4 VD28 TXD2_232 PMC2_40 J24 40 28 GND TRXC4 VD29 RXD2_232 PMC2_42 J24 42 29 PMC2_44 J24 44 VD30 RTS2_232 PMC2_43 J24 43 30 GND 12VF VD31 CTS2_232 PMC...

Page 97: ...ed configures for auto SCON The pin assignments for this connector are as follows 5 3 2 Boundary Scan Header J8 The 14 pin boundary scan header provides an interface for programming the on board PLDs and for boundary scan testing debug purposes The pin assignments for this header are as follows Table 5 16 SCON Header J7 Pin Assignments Pin Signal 1 SCONEN_L 2 GND 3 SCONDIS_L Table 5 17 Boundary Sc...

Page 98: ...nous serial debug port COM2 only goes to the on board header as the default configuration The pin assignments for this header are as follows Table 5 18 PMC IPMC Configuration Jumper Block Pin Row 1 PMC I O Pin Row 2 P2 Pins Pin Row 3 IPMC Pins J28 PMC1_IO 2 P2_PMC1_IO 2 IPMC DB8_L J16 PMC1_IO 5 P2_PMC1_IO 5 IPMC DB9_L J18 PMC1_IO 8 P2_PMC1_IO 8 IPMC DB10_L J25 PMC1_IO 11 P2_PMC1_IO 11 IPMC DB11_L ...

Page 99: ...n Row D From PMC I O Row C To P2 Connector Row B From LAN2 Controller Row A To Front Panel Ethernet 1 PMC0_IO 13 P2a_C7 a VME P2 Fused 12V No Connect 2 PMC0_IO 60 P2_A30 Fused 12V No Connect 3 PMC0_IO 7 P2_C4 magnetic T2b 23 b Transformer for Ethernet port 2 MDI_0P J9c 2 c Ethernet port 2 front connector 4 PMC0_IO 5 P2_C3 magnetic T2 22 MDI_0N J9 3 5 PMC0_IO 3 P2_C2 magnetic T2 20 MDI_1P J9 4 6 PM...

Page 100: ...n The pin assignments for this header are as follows Some signals are actually resistor buffered versions of the named signal Table 5 21 Processor JTAG COP RISCWatch Header J42 Pin Assignments Pin Signal Signal Pin 1 CPU_TDO CPU_QACK_L 2 3 CPU_TDI CPU_TRST_L 4 5 CPU_QREQ_L PU CPU_VIO 6 7 CPU_TCK OPT PU CPU_VIO 8 9 CPU_TMS NC 10 11 CPU_SRST_L OPTPD_GND 12 13 CPU_HRST_L KEY no pin 14 15 CPU_CKSTPO_L...

Page 101: ...ed to 46 2 watts total of both PMC slots A 2 Environmental Specifications Table A 2 lists the environmental specifications along with the board dimensions Table A 1 Power Requirements Model Power MVME6100 0163 Typical 42W 5 V Maximum 51W 5 V MVME6100 0163 with IPMC712 761 Typical 46W 5 V Maximum 55W 5 V Table A 2 MVME6100 Specifications Characteristics Specifications Operating Temperature 0 to 55 ...

Page 102: ... 6U 4HP wide 233 mm x 160 mm x 20 mm 9 2 in x 6 3 in x 0 8 in MTBF 328 698 hours calculated based on BellCore Issue 6 Method 1 case 3 for the central office or environmentally controlled remote shelters or customer premise areas Table A 2 MVME6100 Specifications continued Characteristics Specifications ...

Page 103: ... refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table C 1 Emerson Network Power Embedded Computing Documents Document Title Publication Number MVME61006E Series Single Board Computer Programmer s...

Page 104: ...ntel Corporation Literature Center 19521 E 32nd Parkway Aurora CO 80011 8141 Web Site http developer intel com design flcomp datashts 290737 htm PCI6520 HB7 Transparent PCIx PCIx Bridge Preliminary Data Book PLX Technology Inc 870 Maude Avenue Sunnyvale California 94085 Web Site http www hintcorp com products hint default asp PCI6520 Ver 0 992 EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIF...

Page 105: ...semi com DS1621 TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site http www yeu com Table C 2 Manufacturers Documents continued Document Title and Source Publication Number Table C 3 Related Specifications Document Title and Source Publication Number VITA http www vita com VME64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer...

Page 106: ...omputer Installation and Use 6806800D58E 106 IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc P1386 1 Draft 2 0 Table C 3 Related Specifications continued Document Title and Source Publication Number ...

Page 107: ...ix provides systems integrators with information which can be used to conduct thermal evaluations of the board in their specific system configuration It identifies thermally significant components and lists the corresponding maximum allowable component operating temperatures It also provides example procedures for component level temperature measurements B 2 Thermally Significant Components The fo...

Page 108: ...f the component Air temperature refers to the ambient temperature near the component Table B 1 Thermally Significant Components Reference Designator Generic Description Max Allowable Component Temperature deg C Measurement Location U3 U11 U64 U72 DDR SDRAM 70 Air U84 U95 Gigabit Ethernet Transceiver 129 Case U82 U83 Cache 115 Case U45 U46 Programmable Logic Device 70 Air U32 PCI Bridge 70 Air U20 ...

Page 109: ...ignificant Components Primary Side 4248 0504 10 100 1000 DEBUG ABT RST LAN 2 LAN 1 J42 J8 J30 U20 J3 J19 J13 J14 J11 J12 J23 J24 J21 J22 P1 P2 U21 PCI MEZZANINE CARD PCI MEZZANINE CARD J4 U12 10 100 1000 J93 J9 J29 U1 J7 PMC IPMC U32 U7 U6 U5 U3 U4 U11 U10 U9 U8 U13 U18 U14 U15 U22 U30 U19 U17 U16 U23 U27 U25 ...

Page 110: ...e measurement methods For the specific types of measurements required for thermal evaluation of this board see Table B 1 B 3 1 Preparation Werecommend40AWG Americanwiregauge thermocouplesforallthermalmeasurements Larger gauge thermocouples can wick heat away from the components and disturb air flowing past the board Figure B 2 Thermally Significant Components Secondary Side ...

Page 111: ... component manufacturer s documentation listed in Appendix C Related Documentation B 3 3 Measuring Case Temperature Measure the case temperature at the center of the top of the component Make sure there is good thermal contact between the thermocouple junction and the component We recommend you use a thermally conductive adhesive such as Loctite 384 If components are covered by mechanical parts su...

Page 112: ...th thermal grease The grease should not contact the thermocouple junction Figure B 3 Mounting a Thermocouple Under a Heatsink HEATSINK BOTTOM VIEW ISOMETRIC VIEW Machined groove for thermocouple wire routing Thermocouple junction bonded to component Heatsink base Thermal pad Through hole for thermocouple junction clearance may require removal of fin material Also use for alignment guidance during ...

Page 113: ...ambient temperature by placing the thermocouple downstream of the component This method is conservative since it includes heating of the air by the component The following figure illustrates one method of mounting the thermocouple Figure B 4 Measuring Local Air Temperature Thermocouple junction PWB Tape thermocouple wire to top of component Air flow ...

Page 114: ...Thermal Validation MVME6100 Single Board Computer Installation and Use 6806800D58E 114 ...

Page 115: ...1 delete 47 display 45 edit 46 restore 47 delete VME settings 47 dimensions 101 display VME settings 45 E edit VME settings 46 environmental specifications 101 ESD precautions 18 evaluating thermal performance 107 F features hardware 59 feedback 14 firmware command utility 41 firmware scan 56 firmware startup sequence 57 firmware safe start 55 Flash memory 68 G GT 64260A CPU bus interface 63 I2C s...

Page 116: ... maximum 107 P physical dimensions 101 power requirements 101 power apply 29 processor 61 R relative humidity 101 remote start 48 restore VME settings 47 S settings VME 41 specifications 101 startup overview 17 switch abort reset 29 system controller 62 CPU bus interface 63 I2C serial interface devices 66 interrupt controller 67 memory controller interface 63 system memory 69 T temperature measure...

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Page 118: ...Network Power logo are trademarks and service marks of Emerson Electric Co All other product or service names are the property of their respective owners 2009 Emerson Electric Co Emerson Network Power The global leader in enabling Business Critical Continuity AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions Outside Plant Power Switching ...

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