Embedian SMARC T335x, User Manual

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Embedian, Inc.
55
SMART-BEE User’s Manual Document Revision v.1.2
3.2.3.4. SPI and I2C Header: CN18
Two sets of SPI bus and I2C bus are presented in CN18.
The following table shows the pin-out of the CN18 SPI and I2C header.
CN1
8
: Location on Board, H1
SPI/I2C Header: HEADER
DIP 14*2P 180D MALE 2.0mm
Edge
Finger
Sitara AM335x CPU Type
Header Pin Signal Name Function Pin# Ball Mode
Signal Name
1
Reserved
2
SPI1_
CS0#
SPI1 Master
Chip Select
0 output
P54 C12 3 SPI1_CS0
O
3
SPI0_
CS1#
SPI0 Master
Chip Select
1 output
P31 C15 0 SPI0_CS1
O
4
SPI1_
CS1#
SPI1 Master
Chip Select
1 output
P55 A15 4 SPI1_CS1
O
5
SPI0_
SCLK
SPI0 Master
Clock
output
P44 A17 0 SPIO_SCLK
O
6
SPI1_
SCLK
SPI1 Master
Clock output
P56 A13 3 SPI1_SCLK
O
7 SPI0_
MOSI
SPI0 Master
Data output
(output
from CPU,
input to SPI
device)
P46 B16 0 SPI0_D1 O
8 SPI1_
MOSI
SPI1 Master
Data output
(output
from CPU,
input to SPI
device)
P58 D12 3 SPI1_D1 O